section 7 - Index of

More documents

Recommendations

Info

RESET --------------------------------,~PROCESSOR ENTERS ----, r--RESET STATE1 ~INTERRUPT CONTROL CYCLE 1 f\ ~INTERRUPT CONTROL CYCLE 2l~FETCH n3 n4 - -1PROCESSOR LEAVES RESET STATEnop nA nB nC nO nEDECODE n2 SlOP - - f\~ nop nop nA nB nC nOEXECUTE n1 n2 STOP - ~nop nop nop nA nB nCSTOP CYCLE COUNT 1 2 3 4CLOCK STOPPEDJ~'~-IRESETINTERRUPTnNORMAL INSTRUCTION WORDnA, nB, nC = INSTRUCTIONS IN RESET ROUTINESTOP = INTERRUPT INSTRUCTION WORDFigure 7-19 STOP Instruction Sequence Recovering with RESET
Page 3 and 4:
DSP56K FAMILY INTRODUCTIONDSP56K CE
Page 5:
Motorola reserves the right to make
Page 8 and 9:
Table of Contents (Continued)Paragr
Page 10 and 11:
ParagraphNumberTable of Contents (C
Page 13 and 14:
FigureNumberList of Figures (Contin
Page 15:
List of Tables (Continued)TablePage
Page 19 and 20:
1.1 INTRODUCTIONThe DSP56K family i
Page 21 and 22:
Fewer componentsStable, determinist
Page 23 and 24:
Digital FilteringFinite Impulse Res
Page 25 and 26:
architecture matches the shape of t
Page 27 and 28:
• DSP56001 Compatibility - All me
Page 29:
SECTION 2DSP56K CENTRAL ARCHITECTUR
Page 32 and 33:
--I«a:w:ca.ffi~a. a.24-Bit 56KModu
Page 34 and 35:
-rectly addressable registers: the
Page 37 and 38:
3.1 DATA ARITHMETIC LOGIC UNITThis
Page 39 and 40:
3.2.1 Data ALU Input Registers (X1,
Page 41 and 42:
"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
Page 43 and 44:
3.2.4 Accumulator ShifterThe accumu
Page 45 and 46:
Table 3-1 Limited Data ValuesDestin
Page 47 and 48:
_--- N BITS ---_TWOS COMPLEMENT INT
Page 49 and 50:
CASE I: IF AO < $800000 (1/2), THEN
Page 51 and 52:
one instruction cycle. The ANDI ins
Page 53:
3.5 DATA ALU PROGRAMMING MODELThe D
Page 57 and 58:
4.1 ADDRESS GENERATION UNIT AND ADD
Page 59 and 60:
!---LOWADDRESS ALU -----I~.j.I.....
Page 61 and 62:
•••••••• _ ........
Page 63 and 64:
4.4.1 Address Register Indirect Mod
Page 65 and 66:
EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
Page 67 and 68:
EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
Page 69 and 70:
EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
Page 71 and 72:
Table 4-2 Address Modifier SummaryM
Page 73 and 74:
ADDRESS -f-_POINTERUPPER BOUNDARYiM
Page 75 and 76:
EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
Page 77 and 78:
oundary gives a 16-bit binary numbe
Page 79 and 80:
4.4.2.4 Address-Modifier-Type Encod
Page 81:
SECTION 5PROGRAM CONTROL UNIT-
Page 84 and 85:
X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
Page 86 and 87:
interruptible since they are fetche
Page 88 and 89:
PROGRAM CONTROL UNIT-23 1615 023 16
Page 90 and 91:
The GGR is a special purpose contro
Page 92 and 93:
If S 1 =0 and SO=O (no scaling)then
Page 94 and 95:
-23 876543210I * 1* JSO I * I Mel y
Page 96 and 97:
5.4.5.1 Stack Pointer (Bits 0-3)The
Page 98 and 99:
-DATA ARITHMETIC LOGIC UNITINPUT RE
Page 101 and 102:
6.1 INSTRUCTION SET INTRODUCTIONThe
Page 103 and 104:
shown in Figure 6-2. Most instructi
Page 105 and 106:
23 87 0L...-I ___-'-I_---'I BUS~ LS
Page 107 and 108:
The MR and CCR may be accessed indi
Page 109 and 110:
6.3.4 Operand ReferencesThe DSP sep
Page 111 and 112:
Some address register indirect mode
Page 113 and 114:
EXAMPLE A: IMMEDIATE INTO 24-BIT RE
Page 115 and 116:
EXAMPLE A: IMMEDIATE SHORT INTO AO,
Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
Page 119 and 120: Table 6-1 Addressing Modes SummaryA
Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
Page 127: SECTION 7PROCESSING STATES-
Page 130 and 131: Each instruction requires a minimum
Page 132 and 133: second instruction of the downloade
Page 134 and 135: The DO instruction is another instr
Page 136 and 137: SP and SSH/SSL register manipulatio
Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
Page 140 and 141: Table 7-2 Status Register Interrupt
Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
Page 144 and 145: interrupts makes it very useful for
Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
Page 152 and 153: 7.3.7 Interrupt Instruction Executi
Page 154 and 155: MAINPROGRAMMEMORYINTERRUPT SYNCHRON
Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
Page 164 and 165: The stop processing state halts all
Page 166 and 167: the first instruction fetch). If th
Page 171 and 172: 8.1 PORT A OVERVIEWPort A provides
Page 173 and 174: e subdivided into three additional
Page 175: WT) facility, which allows an exter
Page 179 and 180: 9.1 PLL CLOCK OSCILLATOR INTRODUCTI
Page 181 and 182: The charge pump loop filter receive
Page 183 and 184: shows the programming of the DFO-DF
Page 185 and 186: Table 9-4 Clock Output Disable Bits
Page 187 and 188: 9.4 PLL OPERATION CONSIDERATIONSThe
Page 189 and 190: chip clock. (Here, T3 is equal to t
Page 191: SECTION 10ON-CHIP EMULATION (OnCE)-
Page 194 and 195: ...I~W:I:0...ffi~0...0...24-BitS6KM
Page 196 and 197: 10.2.4 Debug Request Input (DR)The
Page 198 and 199: 10.3.1.2 Exit Command (EX) Bit 5If
Page 200 and 201: When BC3-BCO=0011, program memory b
Page 202 and 203: OSCKPAB XAB YABOSO OSI~-- MEMORY BU
Page 204 and 205: To initiate the trace mode of opera
Page 206 and 207: the trace counter is decremented af
Page 208 and 209: the external command controller whe
Page 210 and 211: The external command controller act
Page 212 and 213: -After 24 bits have been received t
Page 214 and 215: 10.11.4 Executing a Single-Word DSP
Page 216 and 217: PDS contains the second word of the
Page 219 and 220:
11.1 USER SUPPORTUser support from
Page 221 and 222:
the DSP56K family of processors•
Page 223 and 224:
11.3.3 Support Integrated Circuits:
Page 225 and 226:
I Document ID I Version Synopsis I
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
11.12 TRAINING COURSES - (602) 897-
Page 235 and 236:
ADAPTIVE SIGNAL PROCESSINGB. Widrow
Page 237 and 238:
Graphics:CGM AND CGID. B. Arnold an
Page 239 and 240:
NUMERICAL RECIPES IN C - THE ART OF
Page 241:
APPENDIX AINSTRUCTION SET DETAILSAr
Page 244 and 245:
word is optional, it is so indicate
Page 246 and 247:
Table A-1 Instruction Description N
Page 248 and 249:
Table A-1 Instruction Description N
Page 250 and 251:
A.4 ADDRESSING MODESThe addressing
Page 252 and 253:
Addressing ModeTable A-3 DSP56K Add
Page 254 and 255:
Table A-4 Addressing Mode Modifier
Page 256 and 257:
S (Scaling Bit)The scaling bit (S)
Page 258 and 259:
C (Carry Bit)Set if a carry is gene
Page 260 and 261:
The following notes apply to Table
Page 262 and 263:
ABS Absolute Value ABSOperation:I D
Page 264 and 265:
ACC Add Long with Carry ACCOperatio
Page 266 and 267:
ADD Add ADDOperation:S+D-+D (parall
Page 268 and 269:
ADDL Shift Left and Add Accumulator
Page 270 and 271:
ADDR Shift Right and Add Accumulato
Page 272 and 273:
AND Logical AND ANDOperation:S - 0[
Page 274 and 275:
ANDIAND Immediate with Control Regi
Page 276 and 277:
ASL Arithmetic Shift Accumulator Le
Page 278 and 279:
ASR Arithmetic Shift Accumulator Ri
Page 280 and 281:
BCHG Bit Test and Change BCHGOperat
Page 282 and 283:
BCHGBit Test and ChangeBCHGFor othe
Page 284 and 285:
BCHGBit Test and ChangeBCHGInstruct
Page 286 and 287:
BCHGBit Test and Ch~ngeBCHGInstruct
Page 288 and 289:
BCLR Bit Test and Clear BCLROperati
Page 290 and 291:
BCLRBit Test and ClearBCLRFor other
Page 292 and 293:
BCLRBit Test and ClearBCLRInstructi
Page 294 and 295:
BCLRBit Test and ClearBCLRInstructi
Page 296 and 297:
BSET Bit Test and Set BSElOperation
Page 298 and 299:
BSElBit Test and SetBSElFor other d
Page 300 and 301:
BSETBit Test and SetBSETInstruction
Page 302 and 303:
BSETBit Test and SetBSETInstruction
Page 304 and 305:
8TST Bit Test 8TSTOperation:Assembl
Page 306 and 307:
BTSTBit TestBTSTInstruction Format:
Page 308 and 309:
8TSTBit Test8TSTInstruction Format:
Page 310 and 311:
CLR Clear Accumulator CLROperation:
Page 312 and 313:
CMP Compare CMPOperation:Assembler
Page 314 and 315:
CMPM Compare Magnitude CMPMOperatio
Page 316 and 317:
DEBUG Enter Debug Mode DEB,UGOperat
Page 318 and 319:
DEBUGcc Enter Debug Mode Conditiona
Page 320 and 321:
DECDecrement by OneDECOperation:0-1
Page 322 and 323:
DIV Divide Interation DIVOperation:
Page 324 and 325:
DIV Divide Interation DIVExample: (
Page 326 and 327:
DIV Divide Interatlon DIVA complete
Page 328 and 329:
DOStart Hardware LoopDOOperation:As
Page 330 and 331:
DO Start Hardware Loop DOmented by
Page 332 and 333:
DOStart Hardware LoopDOExample:DO #
Page 334 and 335:
DO Start Hardware Loop DOInstructio
Page 336 and 337:
DO Start Hardware Loop DOInstructio
Page 338 and 339:
ENDDO End Current DO Loop ENDDOOper
Page 340 and 341:
EOR Logical Exclusive OR EOROperati
Page 342 and 343:
ILLEGALIllegal Instruction Interrup
Page 344 and 345:
INC Increment by One INCOperation:A
Page 346 and 347:
JccJump ConditionallyJccOperation:I
Page 348 and 349:
Jcc Jump Conditionally JccInstructi
Page 350 and 351:
JCLR Jump If Bit Clear JCLROperatio
Page 352 and 353:
JCLRJump if Bit ClearJCLRInstructio
Page 354 and 355:
JCLRJump if Bit ClearJCLRInstructio
Page 356 and 357:
JMPJumpJMPOperation:Oxxx --t PCea -
Page 358 and 359:
JScc Jump to Subroutine Conditional
Page 360 and 361:
JScc Jump to Subroutine Conditional
Page 362 and 363:
JSCLR Jump to Subroutine If Bit Cle
Page 364 and 365:
JSCLR Jump to Subroutine if Bit Cle
Page 366 and 367:
JSCLRJump to Subroutine if Bit Clea
Page 368 and 369:
JSCLR Jump to Subroutine if Bit Cle
Page 370 and 371:
JSETJump If Bit SetJSETOperation:If
Page 372 and 373:
JSETJump If Bit SetJSETInstruction
Page 374 and 375:
JSETJump if Bit SetJSETInstruction
Page 376 and 377:
JSR Jump to Subroutine JSROperation
Page 378 and 379:
JSSET Jump to Subroutine if Bit Set
Page 380 and 381:
JSSETJump to Subroutine If Bit SetJ
Page 382 and 383:
JSSETJump to Subroutine If Bit SetJ
Page 384 and 385:
LSL Logical ~hlft Left LSLOperation
Page 386 and 387:
LSR Logical Shift Right LSROperatio
Page 388 and 389:
LUALoad Updated AddressLUAOperation
Page 390 and 391:
MAC Signed Multiply-Accumulate MACO
Page 392 and 393:
MACSigned Multiply-AccumulateMACTim
Page 394 and 395:
MACR Signed Multiply-Accumulate and
Page 396 and 397:
MACR Signed Multiply-Accumulate and
Page 398 and 399:
MOVE Move Data MOVEOperation:S~DAss
Page 400 and 401:
MOVE Move Data MOVEParallel Move De
Page 402 and 403:
No Parallel Data MoveOperation:Asse
Page 404 and 405:
IImmediate Short Data MoveIOperatio
Page 406 and 407:
IImmediate Short Data MoveIConditio
Page 408 and 409:
RRegister to Register Data MoveROpe
Page 410 and 411:
R Register to Register Data Move RC
Page 412 and 413:
uAddress Register UpdateuOperation:
Page 414 and 415:
X: X Memory Data Move X:Operation:A
Page 416 and 417:
X: X Memory Data Move X:Instruction
Page 418 and 419:
X: X Memory Data MoveX:Instruction
Page 420 and 421:
X:RX Memory and Register Data MoveX
Page 422 and 423:
X:R X Memory and Register Data Move
Page 424 and 425:
X:R X Memory and Register Data Move
Page 426 and 427:
Y: V Memory Data Move Y:Operation:A
Page 428 and 429:
V: Y Memory Data Move V:Note: The M
Page 430 and 431:
V: Y Memory Data MoveV:Instruction
Page 432 and 433:
R:V Register and V Memory Data Move
Page 434 and 435:
R:Y Register and Y Memory Data Move
Page 436 and 437:
R:VRegister and V Memory Oata MoveR
Page 438 and 439:
L: Long Memory Data Move L:Operatio
Page 440 and 441:
L: Long Memory Data Move L:Instruct
Page 442 and 443:
X: V: xv Memory Data Move X: V:Oper
Page 444 and 445:
X: V: xv Memory Data Move X: V:Note
Page 446 and 447:
MOVEC Move Control Register MOVECOp
Page 448 and 449:
MOVEC Move Control Register MOVECA
Page 450 and 451:
MOVECMove Control RegisterMOVECRegi
Page 452 and 453:
MOVECMove Control RegisterMOVECInst
Page 454 and 455:
MOVEMMove Program MemoryMOVEMOperat
Page 456 and 457:
MOVEM Move Program Memory MOVEMExam
Page 458 and 459:
MOVEM Move Program Memory MOVEMS D
Page 460 and 461:
MOVEP Move Peripheral Data MOVEPOpe
Page 462 and 463:
_______-----'MOVEP Move Peripheral
Page 464 and 465:
MOVEPMove Peripheral DataMOVEPInstr
Page 466 and 467:
MOVEPMove Peripheral DataMOVEPInstr
Page 468 and 469:
MPY Signed Multiply MPYOperation:±
Page 470 and 471:
MPY Signed Multiply MPYInstruction
Page 472 and 473:
MPYR Signed Multiply and Round MPYR
Page 474 and 475:
MPYR Signed Multiply and Round MPYR
Page 476 and 477:
NEG Negate Accumulator NEGOperation
Page 478 and 479:
NOP No Operation NOPOperation:PC+1-
Page 480 and 481:
NORM Normalize Accumulator Iteratio
Page 482 and 483:
NOT Logical Complement NOTOperation
Page 484 and 485:
OR Logical Inclusive OR OROperation
Page 486 and 487:
ORI OR Immediate with Control Regis
Page 488 and 489:
REP Repeat Next Instruction REPOper
Page 490 and 491:
REP Repeat Next Instruction REPExpl
Page 492 and 493:
REPRepeat Next InstructionREPInstru
Page 494 and 495:
REP Repeat Next Instruction REPInst
Page 496 and 497:
RESETReset On-Chip Peripheral Devic
Page 498 and 499:
RND Round Accumulator RNDOperation:
Page 500 and 501:
RND Round Accumulator RNDCondition
Page 502 and 503:
ROL Rotate Left ROLOperation:r47 24
Page 504 and 505:
ROR Rotate Right ROROperation: c:c~
Page 506 and 507:
RTI Return from Interrupt RTIOperat
Page 508 and 509:
RTS Return from Subroutine RTSOpera
Page 510 and 511:
SBC Subtract Long with Carry secOpe
Page 512 and 513:
SBC Subtract Long with Carry SBCCon
Page 514 and 515:
STOP Stop Instruction Processing ST
Page 516 and 517:
SUB Subtract SUBOperation:O-S -4 D
Page 518 and 519:
SUBL Shift Left and Subtract Accumu
Page 520 and 521:
SUBR Shift Right and Subtract Accum
Page 522 and 523:
SWI Software Interrupt SWIOperation
Page 524 and 525:
Tee Transfer Conditionally TeeOpera
Page 526 and 527:
Tee Transfer Conditionally TeeInstr
Page 528 and 529:
TFR Transfer Data ALU Register TFRO
Page 530 and 531:
TST Test Accumulator TSTOperation:A
Page 532 and 533:
WAIT Wait for Interrupt WAITOperati
Page 534 and 535:
A.a INSTRUCTION TIMINGThis section
Page 536 and 537:
cycles that may be required over an
Page 538 and 539:
additional (if any) instruction pro
Page 540 and 541:
3. Evaluate the "ap" term using Tab
Page 542 and 543:
Table A-7 Parallel Data Move Timing
Page 544 and 545:
Table A-12 RTIIRTS Timing SummaryOp
Page 546 and 547:
A.9.1 Restrictions Near the End of
Page 548 and 549:
Immediately before ENDDOBCHG lA, lC
Page 550 and 551:
Immediately before JSCLR from SSH o
Page 552 and 553:
Section A.10.4 gives the encoding f
Page 554 and 555:
Table A-20 Five-Bit Register Encodi
Page 556 and 557:
A.10.2 Instruction Encoding for the
Page 558 and 559:
A.10.3 Instruction Encoding for Ins
Page 560 and 561:
JSETJSET#n,X:ea,xxxx#n,Y:ea,xxxx23
Page 562 and 563:
BCLRBCLR#n,X:pp#n,Y:pp23I 0 0 0 016
Page 564 and 565:
BCLR23#n,O0 0 0 0 1 016 15 871 o \
Page 566 and 567:
DODOX:ea,exprV:ea,expr23 16 15 87 0
Page 568 and 569:
MPYR (±)S,#n,DDEBUGccDEBUG23 16 15
Page 570 and 571:
ILLEGALRTINOP23 16 15 87 0I 0 0 0 0
Page 572 and 573:
Nonmultlply Instruction EncodingThe
Page 574 and 575:
EORS,D23 87 43 0DATA BUS MOVE FIELD
Page 576 and 577:
NOTD23 87 43 0DATA BUS MOVE FIELDSU
Page 579 and 580:
APPENDIX BBENCHMARK PROGRAMS-
Page 581 and 582:
B.1 INTRODUCTIONTable 8-1 provides
Page 583 and 584:
page 132,66,0,6opt rc.*************
Page 585 and 586:
;This program originally available
Page 587 and 588:
page 132,66,0,6opt rc...._..__.....
Page 589 and 590:
page 132,60,1,1;newlms2n.asm; New I
Page 591 and 592:
,; Main program to call the rfft-56
Page 593 and 594:
jle -'oopmove xO,rOmove y1,amove x:
Page 595 and 596:
FirstGrouplnPassdo nO,FirstGrouplnP
Page 597:
; Real input data are split into tw
Page 600 and 601:
zero (bit 2) .................... 5
Page 602 and 603:
-M- OnCE Commands .................
Page 604 and 605:
Saturation Arithmetic .............
Page 606:
DSP56K FAMILY INTRODUCTION_DSP56K C
show all

section 7 - Index of

Create successful ePaper yourself

Delete template?

Save as template?