section 7 - Index of
section 7 - Index of section 7 - Index of
The stop processing state halts all activity in the processor until one of the followingactions occurs:1. A low level is applied to the TRQA pin.2. A low level is applied to the RESET pin.3. A low level is applied to the DR pinEither of these actions will activate the oscillator, and, after a clock stabilization delay,clocks to the processor and peripherals will be re-enabled. The clock stabilization delayperiod is determined by the stop delay (SD) bit in the OMR.The stop sequence is composed of eight instruction cycles called stop cycles. They aredifferentiated from normal instruction cycles because the fourth cycle is stretched for anindeterminate period of time while the four-phase clock is turned off.-The STOP instruction is fetched in stop cycle 1 of Figure 7-17, decoded in stop cycle 2(which is where it is first recognized as a stop command), and executed in stop cycle 3.The next instruction (n4) is fetched during stop cycle 2 but is not decoded in stop cycle 3because, by that time, the STOP instruction prevents the decode. The processor stopsthe clock and enters the stop mode. The processor will stay in the stop mode until it isrestarted.FETCH n3 n4 - -DECODE n2 STOP - -EXECUTE n1 n2 STOP -u"n4t-.t-.111..'"STOP CYCLE COUNT 1 2 3 4IRQA INTERRUPT REQUEST A SIGNALn NORMAL INSTRUCTION WORDSTOP = INTERRUPT INSTRUCTION WORDCLOCK STOPPED~~ 5 6 7 8 (9)'II L RESUME STOP CYCLE COUNT 4,INTERRUPTS ENABLED131 072 T OR 16 T CYCLE COUNT STARTEDFigure 7-17 STOP Instruction Sequence
IRQA ---------------.,FETCH n3 n4 - -DECODE n2 STOP - -EXECUTE n1 n2 STOP ---ii1STOP CYCLE COUNT 1 2 3 4CLOCK STOPPED-.15 6 7 8 (9)L RESUME STOP CYCLE COUNT 4,INTERRUPTS ENABLEDIRQA INTERRUPT REQUEST A SIGNALn NORMAL INSTRUCTION WORDSTOP = INTERRUPT INSTRUCTION WORD"-- 131 072 T OR 16 T CYCLE COUNT STARTEDFigure 7-18 STOP Instruction Sequence Followed by IRQAFigure 7-18 shows the system being restarted by asserting the IRQA signal. If the exitfrom stop state was caused by a low level on the IRQA pin, then the processor will servicethe highest priority pending interrupt. If no interrupt is pending, then the processorresumes at the instruction following the STOP instruction that brought the processor intothe stop state.An IRQA deasserted before the end of the stop cycle count will not be recognized aspending. If IRQA is asserted when the stop cycle count completes, then an IRQA interruptwill be recognized as pending and will be arbitrated with any other interrupts.Specifically, when IRQA is asserted, the internal clock generator is started and begins adelay determined by the SO bit of the OMR. When the chip uses the internal clock oscillator,the SO bit should be set to zero, to allow a longer delay time of 128K T cycles(131,072 T cycles) so that the clock oscillator may stabilize. When the chip uses a stableexternal clock, the SO bit may be set to one to allow a shorter (16 T cycle) delay time anda faster start up of the chip.For example, assume that SD=O so that the 128K T counter is used. During the 128K Tcount, the processor ignores interrupts until the last few counts and, at that time, beginsto synchronize them. At the end of the 128K T cycle delay period, the chip restartsinstruction processing, completes stop cycle 4 (interrupt arbitration occurs at this time),and executes stop cycles 5, 6, 7, and 8 (it takes 17T from the end of the 128K T delay to
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The stop processing state halts all activity in the processor until one <strong>of</strong> the followingactions occurs:1. A low level is applied to the TRQA pin.2. A low level is applied to the RESET pin.3. A low level is applied to the DR pinEither <strong>of</strong> these actions will activate the oscillator, and, after a clock stabilization delay,clocks to the processor and peripherals will be re-enabled. The clock stabilization delayperiod is determined by the stop delay (SD) bit in the OMR.The stop sequence is composed <strong>of</strong> eight instruction cycles called stop cycles. They aredifferentiated from normal instruction cycles because the fourth cycle is stretched for anindeterminate period <strong>of</strong> time while the four-phase clock is turned <strong>of</strong>f.-The STOP instruction is fetched in stop cycle 1 <strong>of</strong> Figure 7-17, decoded in stop cycle 2(which is where it is first recognized as a stop command), and executed in stop cycle 3.The next instruction (n4) is fetched during stop cycle 2 but is not decoded in stop cycle 3because, by that time, the STOP instruction prevents the decode. The processor stopsthe clock and enters the stop mode. The processor will stay in the stop mode until it isrestarted.FETCH n3 n4 - -DECODE n2 STOP - -EXECUTE n1 n2 STOP -u"n4t-.t-.111..'"STOP CYCLE COUNT 1 2 3 4IRQA INTERRUPT REQUEST A SIGNALn NORMAL INSTRUCTION WORDSTOP = INTERRUPT INSTRUCTION WORDCLOCK STOPPED~~ 5 6 7 8 (9)'II L RESUME STOP CYCLE COUNT 4,INTERRUPTS ENABLED131 072 T OR 16 T CYCLE COUNT STARTEDFigure 7-17 STOP Instruction Sequence
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