section 7 - Index of

INTERRUPT CONTROL CYCLE 1rINTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDINGiINTERRUPT CONTROL CYCLE 2iFETCH n3 n4 - - - - - - ii1 ii2DECODE n2 WNr - - - - - - - ii1EXECUTE n1 n2 WNr - - - - - - -INSTRUCTION CYCLE COUNT 1 2 3 4 5 6 7 8 9 10n4ii2ii111INTERRUPT '------------~-----------~INTERRUPT INSTRUCTION WORDEQUIVALENT TO EIGHT NOPsn = NORMAL INSTRUCTION WORDFigure 7-16 Simultaneous Wait Instruction and Interrupt7.6 STOP PROCESSING STATEThe STOP instruction· brings the processor into the stop processing state, which is thelowest power consumption state. In the stop state, the clock oscillator is gated off;whereas, in the wait state, the clock oscillator remains active. The chip clears all peripheralinterrupts and external interrupts (IROA, IROB, and NMI) when it enters the stopstate. Trace or stack errors that were pending, remain pending. The priority levels of theperipherals remain as they were before the STOP instruction was executed. The on-chipperipherals are held in their respective individual reset states while in the stop state.