section 7 - Index of

7.5 WAIT PROCESSING STATEThe WAIT instruction brings the processor into the wait processing state which is one oftwo low power-consumption states. Asserting the OnCE's debug request pin releases.the DSP from the wait state. In the wait state, the internal clock is disabled from all internalcircuitry except the internal peripherals. All internal processing is halted until anunmasked interrupt occurs, the Debug Request pin of the OnCE is asserted, or the DSPis reset.-Figure 7-15 shows a WAIT instruction being fetched, decoded, and executed. It isfetched as n3 in this example and, during decode, is recognized as a WAIT instruction.The following instruction (n4) is aborted, and the internal clock is disabled from all internalcircuitry except the internal peripherals. The processor stays in this state until aninterrupt or reset is recognized. The response time is variable due to the timing of theinterrupt with respect to the internal clock. Figure 7-15 shows the result of a fast interruptbringing the processor out of the wait state. The two appropriate interrupt vectors arefetched and put in the instruction pipe. The next instruction fetched is n4, which had beenaborted earlier. Instruction execution proceeds normally from this point.,rINTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDING~----------------~--~--~--~,INTERRUPT CONTROL CYCLE 1~----------------~--~--+---~~,~--~--~--~--+---~~INTERRUPT CONTROL CYCLE 2FETCH n3 n4 - ~ ii1 ii2 n4 n5r------------------r--~--+---~~,~--_r--_r--~--+_--r_~DECODE n2 WNf - ii1 ii2 n4r------------------r--~--+---~~~~--_r--_r--~--+_--r_~EXECUTEn1 n2 WNf ... ii1 ii2INSTRUCTION CYCLE COUNT= INTERRUPT= INTERRUPT INSTRUCTION WORDn = NORMAL INSTRUCTION WORD1 2 3 4~ 5 6 7 8 9 10L ONLY INTERNAL PERIPHERALSRECEIVE CLOCKFigure 7-15 Wait Instruction TimingFigure 7-16 shows an example of the WAIT instruction being executed at the same timethat an interrupt is pending. Instruction n4 is aborted as before. The WAIT instructioncauses a five-instruction-cycle delay from the time it is decoded, after which the interruptis processed normally. The internal clocks are not turned off, and the net effect is that ofexecuting eight NOP instructions between the execution of n2 and ii1.