section 7 - Index of
section 7 - Index of section 7 - Index of
MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZIDfN) RE
MAINPROGRAMFETCHES~~I~-lI~~INTEARlPTF81DN3n6n7n8n9rINTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDINGINTERRUPT CONTROL CYCLE 1 IINTERRUPT CONTROL CYCLE 2 1%(a) Instruction Fetches from Memoryr-- INTERRUPTS RE ENABLEDIiFETCH REP n2 REPn4REPn6n7n8 iiI 112 n9DECODE REP NOP n2n2 n2 REP NOPn4n4 n4 REP NOPn6n6n6 n7 n8 111 i2 n9EXECUTE REP /lOPn2 n2 n2 REPNOPn4 n4 n4 REP NOP n6n6 n6 n7 n8 il i2 n9INSTRUCTION CYCLE COUNT 1 2 3 45 6 7 8910 11 12 1314 1516 17 18 19 20 21 22i = INTERRUPTii = INTERRUPT INSTRUCTION WORDn = NORMAL INSTRUCTION WORDi% = INTERRUPT REJECTED(b) Program Controller PipelineFigure 7-14 Interrupting Sequential REP Instructions
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 144 and 145: interrupts makes it very useful for
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
- Page 152 and 153: 7.3.7 Interrupt Instruction Executi
- Page 154 and 155: MAINPROGRAMMEMORYINTERRUPT SYNCHRON
- Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
- Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
- Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
- Page 164 and 165: The stop processing state halts all
- Page 166 and 167: the first instruction fetch). If th
- Page 168: RESET -----------------------------
- Page 172 and 173: 16 - BIT INTERNALADDRESS BUSESX ADD
- Page 174 and 175: 8.2.2.1 Address (AO-A15)These three
- Page 177: SECTION 9PLL CLOCK OSCILLATOR-
- Page 180 and 181: X MEMORYRAM/ROMEXPANSION24-Bit56KMo
- Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
- Page 184 and 185: cleared. To enable rapid recovery w
- Page 186 and 187: -CLVCCVCC for the CKOUT output. The
- Page 188 and 189: 4. For all input frequencies which
- Page 190 and 191: While the PLL is regaining lock, th
- Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
- Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
- Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
- Page 199 and 200: shifted in (so a new command is ava
- Page 201 and 202: 10.3.4.4 Software Debug Occurrence
- Page 203 and 204: 10.4.4 Memory High Address Comparat
- Page 205 and 206: 10.6.1 External Debug Request Durin
- Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
- Page 209 and 210: are serially available to the exter
MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZIDfN) RE
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