section 7 - Index of

mented to one (see Figure 7-13). During the execution of n2 in Figure 7-13, no interruptswill be serviced. When LC finally decrements to one, the fetches are reinitiated, andpending interrupts can be serviced.Sequential REP packages will cause pending interrupts to be rejected until the sequenceof REP packages ends. REP packages are not interruptible because the instructionbeing repeated is not refetched. While that instruction is repeating, no instructions arefetched or decoded, and an interrupt can not be inserted. For example, in Figure 7-14, ifn1, n3, and n5 are all REP instructions, no interrupts will be serviced until the last REPinstruction (n5 and its repeated instruction, n6) completes execution.7.4 RESET PROCESSING STATEThe processor enters the reset processing state when a hardware reset occurs and theexternal RESET pin is asserted. The reset state:1. resets internal peripheral devices;2. sets the modifier registers to $FFFF;3. clears the interrupt priority register;4. sets the SCR to $FFFF, thereby inserting 15 wait states in all external memoryaccesses;5. clears the stack pointer;6. clears the scaling mode, trace mode, loop flag, double precision multiplymode, and condition code bits of the SR, and sets the interrupt mask bits ofthe SR;7. clears the data ROM enable bit, the stop delay bit, and the internal Y memorydisable bit, and8. the DSP remains in the reset state until the RESET pin is deasserted.When the processor deasserts the reset state:9. it loads the chip operating mode bits of the OMR from the external mode selectpins (MODA, MODS, MODC), and10. begins program execution at program memory address defined by the state ofbits MODA, MODS, and MODC in the OMR. The first instruction must befetched and then decoded before executing. Therefore, the first instructionexecution is two instruction cycles after the first instruction fetch.