section 7 - Index of
section 7 - Index of section 7 - Index of
MAINPROGRAMFAST INTERRUPTVECTORLONG INTERRUPTSUBROUTINEn1n2-..---(a) Instruction Fetches from MemoryINTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDINGr INTERRUPTSRE-ENABLEDINTERRUPT CONTROL CYCLE 1iINTERRUPT CONTROL CYCLE 2FETCHin1ii1JSR- ii3 ii4 ii5iin RTl -n2DECODEn1ii1JSR f\OI ii3 ii4 ii5ii6 iin RTlf\OIn2EXECUTEn1ii1 JSR f\OI ii3 ii4ii5 ii6 iinRTlf\OIn2INSTRUCTION CYCLE COUNT 1 2INTERRUPTINTERRUPT INSTRUCTION WORDn = NORMAL INSTRUCTION WORD3 45 6 7 8 910 11 1213 1415(b) Program Controller PipelineFigure 7-12 JSR Second Instruction of a Fast Interrupt
mented to one (see Figure 7-13). During the execution of n2 in Figure 7-13, no interruptswill be serviced. When LC finally decrements to one, the fetches are reinitiated, andpending interrupts can be serviced.Sequential REP packages will cause pending interrupts to be rejected until the sequenceof REP packages ends. REP packages are not interruptible because the instructionbeing repeated is not refetched. While that instruction is repeating, no instructions arefetched or decoded, and an interrupt can not be inserted. For example, in Figure 7-14, ifn1, n3, and n5 are all REP instructions, no interrupts will be serviced until the last REPinstruction (n5 and its repeated instruction, n6) completes execution.7.4 RESET PROCESSING STATEThe processor enters the reset processing state when a hardware reset occurs and theexternal RESET pin is asserted. The reset state:1. resets internal peripheral devices;2. sets the modifier registers to $FFFF;3. clears the interrupt priority register;4. sets the SCR to $FFFF, thereby inserting 15 wait states in all external memoryaccesses;5. clears the stack pointer;6. clears the scaling mode, trace mode, loop flag, double precision multiplymode, and condition code bits of the SR, and sets the interrupt mask bits ofthe SR;7. clears the data ROM enable bit, the stop delay bit, and the internal Y memorydisable bit, and8. the DSP remains in the reset state until the RESET pin is deasserted.When the processor deasserts the reset state:9. it loads the chip operating mode bits of the OMR from the external mode selectpins (MODA, MODS, MODC), and10. begins program execution at program memory address defined by the state ofbits MODA, MODS, and MODC in the OMR. The first instruction must befetched and then decoded before executing. Therefore, the first instructionexecution is two instruction cycles after the first instruction fetch.
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 144 and 145: interrupts makes it very useful for
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
- Page 152 and 153: 7.3.7 Interrupt Instruction Executi
- Page 154 and 155: MAINPROGRAMMEMORYINTERRUPT SYNCHRON
- Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
- Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
- Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
- Page 164 and 165: The stop processing state halts all
- Page 166 and 167: the first instruction fetch). If th
- Page 168: RESET -----------------------------
- Page 172 and 173: 16 - BIT INTERNALADDRESS BUSESX ADD
- Page 174 and 175: 8.2.2.1 Address (AO-A15)These three
- Page 177: SECTION 9PLL CLOCK OSCILLATOR-
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- Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
- Page 184 and 185: cleared. To enable rapid recovery w
- Page 186 and 187: -CLVCCVCC for the CKOUT output. The
- Page 188 and 189: 4. For all input frequencies which
- Page 190 and 191: While the PLL is regaining lock, th
- Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
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- Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
- Page 199 and 200: shifted in (so a new command is ava
- Page 201 and 202: 10.3.4.4 Software Debug Occurrence
- Page 203 and 204: 10.4.4 Memory High Address Comparat
- Page 205 and 206: 10.6.1 External Debug Request Durin
- Page 207 and 208: PABCIRCULARBUFFERPOINTERDSCKDSOFigu
MAINPROGRAMFAST INTERRUPTVECTORLONG INTERRUPTSUBROUTINEn1n2-..---(a) Instruction Fetches from MemoryINTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDINGr INTERRUPTSRE-ENABLEDINTERRUPT CONTROL CYCLE 1iINTERRUPT CONTROL CYCLE 2FETCHin1ii1JSR- ii3 ii4 ii5iin RTl -n2DECODEn1ii1JSR f\OI ii3 ii4 ii5ii6 iin RTlf\OIn2EXECUTEn1ii1 JSR f\OI ii3 ii4ii5 ii6 iinRTlf\OIn2INSTRUCTION CYCLE COUNT 1 2INTERRUPTINTERRUPT INSTRUCTION WORDn = NORMAL INSTRUCTION WORD3 45 6 7 8 910 11 1213 1415(b) Program Controller PipelineFigure 7-12 JSR Second Instruction <strong>of</strong> a Fast Interrupt
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