section 7 - Index of
section 7 - Index of section 7 - Index of
MAINPROGRAMMEMORYINTERRUPT SYNCHRONIZEDAND RECOGNIZEDAS PENDING_ADDITIONAL INTERRUPTSDISABLED FAST INTERRUPT DURINGn1n2it==~C=~):""-'------J::====~~-.--l1--__ n_3 __--fn4INTERRUPTS- 1-----=:-----1RE-ENABLED { n5ADDITIONAL INTERRUPTSDISABLED DURING I n7FAST INTERRUPT I----n-a-----it---n~6r-JF~-_____ .l::::::=~~_.-lINTERRUPTS- I----n-g----fRE-ENABLED-ii = INTERRUPT INSTRUCTIONn = NORMAL INSTRUCTION(a) Instruction Fetches from Memory.---INTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDING.--- INTERRUPTS RE-ENABLED61cyeINTERRUPT CONTROL CYCLE 1iiINTERRUPT CONTROL CYCLE 2iiFETCHn1n2 ii1 ii2 n3 n4 n5n6ii1ii2DECODEn1 n2 ii1 ii2 n3 n4n5n6ii1ii2EXECUTEn1 n2 ii1 ii2 n3n4n5n6ii1ii2INSTRUCTION CYCLE COUNT 12 3 4 5 6 78 9101112nINTERRUPTINTERRUPT INSTRUCTION WORD= NORMAL INSTRUCTION WORD(b) Program Controller PipelineFigure 7-9 Two Consecutive Fast Interrupts
6. The fast interrupt returns without an RT/'7. Normal instruction fetching resumes using the PC following the completion ofthe fast interrupt routine.8. A fast interrupt is not interruptible.9. A JSR instruction within the fast interrupt routine forms a long interrupt routine.10. The primary application is to move data between memory and I/O devices.The execution of a long interrupt routine always conforms to the following rules:1. A JSR to the starting address of the interrupt service routine is located at oneof the two interrupt vector addresses.2. During execution of the JSR instruction, the PC and SR are stacked. The interruptmask bits of the SR are updated to mask interrupts of the same or lowerpriority. The loop flag, trace bit, double precision multiply mode bit, and scalingmode bits are reset.3. The first instruction word of the next interrupt service (of higher IPL) will reachthe decoder only after the decoding of at least four instructions following thedecoding of the first instruction of the previous interrupt.-4. The interrupt service routine can be interrupted - i.e., nested interrupts aresupported.5. The long interrupt routine, which can be any length, should be terminated byan RTI, which restores the PC and SR from the stack.Figure 7-10 illustrates the effect of a long interrupt routine on the instruction pipeline. Ashort JSR (a JSR with 12-bit absolute address) is used to form the long interrupt routine.For this example, word 6 of the long interrupt routine is an RT/' The point at which interruptsare re-enabled and subsequent interrupts are allowed is shown to illustrate thenon-interruptible nature of the early instructions in the long interrupt service routine.Either one of the two instructions of the fast interrupt can be the JSR instruction thatforms the long interrupt. Figure 7-11 and Figure 7-12 show the two possible cases. If thefirst fast interrupt vector instruction is the JSR, the second instruction is never used.A REP instruction and the instruction that follows it are treated as a Single two-wordinstruction, regardless of how many times it repeats the second instruction of the pair.Instruction fetches are suspended and will be reactivated only after the LC is decre-
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 144 and 145: interrupts makes it very useful for
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
- Page 152 and 153: 7.3.7 Interrupt Instruction Executi
- Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
- Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
- Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
- Page 162 and 163: 7.5 WAIT PROCESSING STATEThe WAIT i
- Page 164 and 165: The stop processing state halts all
- Page 166 and 167: the first instruction fetch). If th
- Page 168: RESET -----------------------------
- Page 172 and 173: 16 - BIT INTERNALADDRESS BUSESX ADD
- Page 174 and 175: 8.2.2.1 Address (AO-A15)These three
- Page 177: SECTION 9PLL CLOCK OSCILLATOR-
- Page 180 and 181: X MEMORYRAM/ROMEXPANSION24-Bit56KMo
- Page 182 and 183: 23 22 21 20 19 18 17 16 15 14 13 12
- Page 184 and 185: cleared. To enable rapid recovery w
- Page 186 and 187: -CLVCCVCC for the CKOUT output. The
- Page 188 and 189: 4. For all input frequencies which
- Page 190 and 191: While the PLL is regaining lock, th
- Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
- Page 195 and 196: 10.2.2 Debug Serial Clock/Chip Stat
- Page 197 and 198: 76543210I R/W I GO I EX I RS41 RS31
- Page 199 and 200: shifted in (so a new command is ava
- Page 201 and 202: 10.3.4.4 Software Debug Occurrence
- Page 203 and 204: 10.4.4 Memory High Address Comparat
MAINPROGRAMMEMORYINTERRUPT SYNCHRONIZEDAND RECOGNIZEDAS PENDING_ADDITIONAL INTERRUPTSDISABLED FAST INTERRUPT DURINGn1n2it==~C=~):""-'------J::====~~-.--l1--__ n_3 __--fn4INTERRUPTS- 1-----=:-----1RE-ENABLED { n5ADDITIONAL INTERRUPTSDISABLED DURING I n7FAST INTERRUPT I----n-a-----it---n~6r-JF~-_____ .l::::::=~~_.-lINTERRUPTS- I----n-g----fRE-ENABLED-ii = INTERRUPT INSTRUCTIONn = NORMAL INSTRUCTION(a) Instruction Fetches from Memory.---INTERRUPT SYNCHRONIZED ANDRECOGNIZED AS PENDING.--- INTERRUPTS RE-ENABLED61cyeINTERRUPT CONTROL CYCLE 1iiINTERRUPT CONTROL CYCLE 2iiFETCHn1n2 ii1 ii2 n3 n4 n5n6ii1ii2DECODEn1 n2 ii1 ii2 n3 n4n5n6ii1ii2EXECUTEn1 n2 ii1 ii2 n3n4n5n6ii1ii2INSTRUCTION CYCLE COUNT 12 3 4 5 6 78 9101112nINTERRUPTINTERRUPT INSTRUCTION WORD= NORMAL INSTRUCTION WORD(b) Program Controller PipelineFigure 7-9 Two Consecutive Fast Interrupts