section 7 - Index of
section 7 - Index of section 7 - Index of
interrupts makes it very useful for setting breakpoints in monitor programs. The JSRinstruction does not affect the interrupt mask.The III is also a nonmaskable interrupt (IPL 3). It is serviced immediately following theexecution or the attempted execution of an illegal instruction (any undefined operationcode). Ills are fatal errors. Only a long interrupt routine should be used for the III routine.RTI or RTS should not be used at the end of the interrupt routine because, during the IIIservice, the JSR located in the III' vector will normally stack the address of the illegalinstruction (see Figure 7-4). Returning from the interrupt routine would cause the processorto attempt to execute the illegal interrupt again and cause an infinite loop which canonly be broken by cycling power. This long interrupt (see Figure 7-4) can be used as adiagnostic tool to allow the programmer to examine the stack (MOVE SSH, dest) andlocate the illegal instruction, or the application program can be restarted with the hopethat the failure was a soft error. The illegal instruction is useful for triggering the illegalinterrupt service routine to see if the III routine can recover from illegal instructions.-INTERRUPT CONTROL CYCLE 1INTERRUPT CONTROL CYCLE 2ii*i i*FETCH n3 n4DECODE n2 n3EXECUTE n1 n2INSTRUCTION BEING DECODED 1n5 ii1 ii3SWI - - -n3 SWI NOP NOPii4 sw1 sw2 sw3 sw4JSR - sw1 sw2 sw3NOP JSR - sw1 sw2i = INTERRUPT REQUESTi* = INTERRUPT REQUEST GENERATED BY SWIii1 = FIRST VECTOR OF INTERRUPT iii3 = FIRST SWI VECTOR (ONE-WORD JSR)ii4 = SECOND SWI VECTORn = NORMAL INSTRUCTION WORDn4 =SWIsw = INSTRUCTIONS PERTAINING TO THE SWI LONG INTERRUPT ROUTINEFigure 7-3 Interrupting an SWI
MAINPROGRAMFETCHESFAST INTERRUPTSERVICE ROUTINEFETCHESINFINITELOOP{II (NOP)1--__ "_6__--1NO FETCHNO FETCH(a) Instruction Fetches from MemoryILLEGAL INSTRUCTION INTERRUPTRECOGNIZED AS PENDINGILLEGAL INSTRUCTION INTERRUPTRECOGNIZED AS PENDINGINTERRUPT CONTROL CYCLE 1iINTERRUPT CONTROL CYCLE 2iFETCHDECODEEXECUTEINSTRUCTION CYCLE COUNT 1n1 n2 n3n1 n2n12 3 4n4 n5 n6 -n3 n4 II -rQ rG Ill- NJP5 6 7 8- ii1 ii2 n5- - i1 ii2 /I- - - ii1 ii2 I\Ol9 10 11 12 13 14iINTERRUPTii INTERRUPT INSTRUCTION WORDII = ILLEGAL INSTRUCTION" = NORMAL INSTRUCTION WORD(b) Program Controller PipelineFigure 7-4 Illegal Instruction Interrupt Serviced by a Fast Interrupt
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- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
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- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
- Page 152 and 153: 7.3.7 Interrupt Instruction Executi
- Page 154 and 155: MAINPROGRAMMEMORYINTERRUPT SYNCHRON
- Page 156 and 157: MAINPROGRAMFETCHESINTERRUPTSYNCHRON
- Page 158 and 159: MAINPROGRAMFAST INTERRUPTVECTORLONG
- Page 160 and 161: MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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- Page 164 and 165: The stop processing state halts all
- Page 166 and 167: the first instruction fetch). If th
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- Page 177: SECTION 9PLL CLOCK OSCILLATOR-
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- Page 184 and 185: cleared. To enable rapid recovery w
- Page 186 and 187: -CLVCCVCC for the CKOUT output. The
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- Page 190 and 191: While the PLL is regaining lock, th
- Page 193 and 194: 10.1 ON-CHIP EMULATION INTRODUCTION
MAINPROGRAMFETCHESFAST INTERRUPTSERVICE ROUTINEFETCHESINFINITELOOP{II (NOP)1--__ "_6__--1NO FETCHNO FETCH(a) Instruction Fetches from MemoryILLEGAL INSTRUCTION INTERRUPTRECOGNIZED AS PENDINGILLEGAL INSTRUCTION INTERRUPTRECOGNIZED AS PENDINGINTERRUPT CONTROL CYCLE 1iINTERRUPT CONTROL CYCLE 2iFETCHDECODEEXECUTEINSTRUCTION CYCLE COUNT 1n1 n2 n3n1 n2n12 3 4n4 n5 n6 -n3 n4 II -rQ rG Ill- NJP5 6 7 8- ii1 ii2 n5- - i1 ii2 /I- - - ii1 ii2 I\Ol9 10 11 12 13 14iINTERRUPTii INTERRUPT INSTRUCTION WORDII = ILLEGAL INSTRUCTION" = NORMAL INSTRUCTION WORD(b) Program Controller PipelineFigure 7-4 Illegal Instruction Interrupt Serviced by a Fast Interrupt
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