section 7 - Index of
section 7 - Index of section 7 - Index of
7.3.3 Interrupt SourcesInterrupts can originate from any of the vector addresses listed in Table 7-6, whichshows the corresponding interrupt starting address for each interrupt source. Theseaddresses are located in the first 64 locations of program memory.Table 7-6 Interrupt Sources-InterruptStarting AddressIPL$0000 3 Hardware RESET$0002 3 Stack Error$0004 3 Trace$0006 3 SWI$0008 0-2 IROA$OOOA 0-2 IROBInterrupt Source: : Vectors available for peripherals$001E 3 NMI: : Vectors available for peripherals$003E 3 Illegal InstructionWhen an interrupt occurs, the instruction at the interrupt starting address is fetched first.Because the program flow is directed to a different starting address for each interrupt,the interrupt structure of the DSP56K can be described as "vectored". A vectored interruptstructure has low execution overhead. If it is known beforehand that certain interruptswill not be used, those interrupt vector locations can be used for program or datastorage.7.3.3.1 Hardware Interrupt SourcesThere are two types of hardware interrupts in the DSP56K: internal and external. Theinternal interrupt sources include all of the on-chip peripheral devices. For further informationon a device's internal interrupt sources, see the device's individual User's Manual.The external hardware interrupt sources are the RESET, NMI, IROA, and IROB pins onthe program interrupt controller in the Program Control Unit.The level sensitive RESET interrupt is the highest priority interrupt with an IPL of 3. IROAand IROB can be programmed to one of three priority levels: 0, 1, or 2 - all of which aremaskable. IROA and IROB have independent enable control and can be programmed tobe level sensitive or edge sensitive. Since level-sensitive interrupts will not be cleared
automatically when they are serviced, they must be cleared by other means to preventmultiple interrupts. Edge-sensitive interrupts are latched as pending on the high-to-Iowtransition of the interrupt input and are automatically cleared when the interrupt is serviced.When either the IROA or IROB pin is disabled in the interrupt priority register, the interruptrequest coming in on the pin will be ignored, regardless of whether the input wasdefined as level sensitive or edge sensitive. If the interrupt input is defined as edge sensitive,its edge-detection latch will remain in the reset state for as long as the'interrupt pinis disabled. If the interrupt is defined as level-sensitive, its edge-detection latch will stayin the reset state. If the level-sensitive interrupt is disabled while it is pending it will becancelled. However, if the interrupt has been fetched, it normally will not be cancelled.The processor begins interrupt service by fetching the instruction word in the first vectorlocation. The interrupt is considered finished when the processor fetches the instructionword in the second vector location.In an edge-triggered interrupt, the internal latch is automatically cleared when the secondvector location is fetched. The fetch of the first vector location does not guarantee thatthe second location will be fetched. Figure 7-3 illustrates the one case where the secondvector location is not fetched. The SWI instruction in the figure discards the fetch of thefirst interrupt vector to ensure that the SWI vectors will be fetched. Instruction n4 isdecoded as an SWI while ii1 is being fetched. Execution of the SWI requires that ii1 bediscarded and the two SWI vectors (ii3 and ii4) be fetched instead.CAUTIONOn all level-sensitive interrupts, the interrupt must be externally released beforeinterrupts are internally re-enabled. Otherwise, the processor will be interruptedrepeatedly until the release of the level-sensitive interrupt occurs.The edge sensitive NMI is a priority 3 interrupt and cannot be masked. Only RESET andillegal instruction have higher priority than NMI.software interrupt (SWI) and illegal instruc7.3.3.2 Software Interrupt SourcesThere are two software interrupt sources -tion interrupt (III).SWI is a nonmaskable interrupt (IPL 3), which is serviced immediately following the SWIinstruction execution, usually using a long interrupt service routine. The differencebetween an SWI and a JSR instruction is that the SWI sets the interrupt mask to preventinterrupts below IPL 3 from being serviced. The SWI's ability to mask out lower level
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automatically when they are serviced, they must be cleared by other means to preventmultiple interrupts. Edge-sensitive interrupts are latched as pending on the high-to-Iowtransition <strong>of</strong> the interrupt input and are automatically cleared when the interrupt is serviced.When either the IROA or IROB pin is disabled in the interrupt priority register, the interruptrequest coming in on the pin will be ignored, regardless <strong>of</strong> whether the input wasdefined as level sensitive or edge sensitive. If the interrupt input is defined as edge sensitive,its edge-detection latch will remain in the reset state for as long as the'interrupt pinis disabled. If the interrupt is defined as level-sensitive, its edge-detection latch will stayin the reset state. If the level-sensitive interrupt is disabled while it is pending it will becancelled. However, if the interrupt has been fetched, it normally will not be cancelled.The processor begins interrupt service by fetching the instruction word in the first vectorlocation. The interrupt is considered finished when the processor fetches the instructionword in the second vector location.In an edge-triggered interrupt, the internal latch is automatically cleared when the secondvector location is fetched. The fetch <strong>of</strong> the first vector location does not guarantee thatthe second location will be fetched. Figure 7-3 illustrates the one case where the secondvector location is not fetched. The SWI instruction in the figure discards the fetch <strong>of</strong> thefirst interrupt vector to ensure that the SWI vectors will be fetched. Instruction n4 isdecoded as an SWI while ii1 is being fetched. Execution <strong>of</strong> the SWI requires that ii1 bediscarded and the two SWI vectors (ii3 and ii4) be fetched instead.CAUTIONOn all level-sensitive interrupts, the interrupt must be externally released beforeinterrupts are internally re-enabled. Otherwise, the processor will be interruptedrepeatedly until the release <strong>of</strong> the level-sensitive interrupt occurs.The edge sensitive NMI is a priority 3 interrupt and cannot be masked. Only RESET andillegal instruction have higher priority than NMI.s<strong>of</strong>tware interrupt (SWI) and illegal instruc7.3.3.2 S<strong>of</strong>tware Interrupt SourcesThere are two s<strong>of</strong>tware interrupt sources -tion interrupt (III).SWI is a nonmaskable interrupt (IPL 3), which is serviced immediately following the SWIinstruction execution, usually using a long interrupt service routine. The differencebetween an SWI and a JSR instruction is that the SWI sets the interrupt mask to preventinterrupts below IPL 3 from being serviced. The SWI's ability to mask out lower level
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