section 7 - Index of
section 7 - Index of section 7 - Index of
Table 7-2 Status Register Interrupt Mask Bits11 10 Exceptions Permitted Exceptions Masked0 0 IPLO, 1,2,3 None0 1 IPL 1, 2, 3 IPL 01 0 IPL2,3 IPL 0,11 1 IPL 3 IPL 0, 1,2rent processor priority level. However, level 3 interrupts are not maskable and thereforecan always interrupt the processor. DSP56K Family central processor interrupt sourcesand their IPLs are listed in Table 7-6. For information on on-chip peripheral interrupt prioritylevels, see the individual DSP56K family member's User's Manual.-7.3.2.1 Interrupt Priority LevelsThe IPL for each on-chip peripheral device (HI, SSI, SCI) and for each external interruptsource (IRQA, IRQ8) can be programmed to one of the three maskable priority levels(IPL 0, 1, or 2) under software control. IPLs are set by writing to the interrupt priority registershown in Figure 7-2. This read/write register is located in program memory ataddress $FFFF. It specifies the IPL for each of the interrupting devices including IRQA,IRQ8 and each peripheral device. (For specific peripheral information, see the specificDSP56K family member's User's Manual.) In addition, it specifies the trigger mode of theexternal interrupt sources and is used to enable or disable the individual external inter~rupts. The interrupt priority register is cleared on RESET or by the reset instruction.Table 7-3 defines the IPL bits. Table 7-4 defines the external interrupt trigger mode bits.23 ........................................................ 1 0 9 8 7 6 5 4 3 2 0'---'----'--- IRQA MODE~~--~------------IRQBMODE~--'-__ -L...---' __________ RESERVED FOR EXPANSION'--_________....1...-_____________ RESERVED FOR PERIPHERAL IPL LEVELSBits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility.Figure 7-2 Interrupt Priority Register (Addr X:$FFFF)
Table 7-3 Interrupt Priority Level BitsTable 7-4 External InterruptxxL1 xxLO Enabled IPL IxL2 Trigger Mode0 0 No - 0 Level0 1 Yes 0 1 Negative Edge1 0 Yes 11 1 Yes 27.3.2.2 Exception Priorities Within an IPLIf more than one interrupt is pending when an instruction is executed, the processor willservice the interrupt with the highest priority level first. When multiple interrupt requestswith the same IPL are pending, a second fixed-priority structure within that IPL determineswhich interrupt the processor will service. The fixed priority of interrupts within anIPL and the interrupt enable bits for all interrupts are shown in Table 7-5.Table 7-5 Central Processor Interrupt Priorities Within an IPLPriority Exception Enabled By Bit No.X DataMemoryAddressLevel 3 (Nonmaskable)Highest Hardware RESET - - -III - - -NMI - - -Stack Error - - -Trace - - -Lowest SWI - - -Levels 0, 1,2 (Maskable)Higher IROA (External Interrupt) IROA Mode Bits o and 1 $FFFFLower IROB (External Interrupt) IROB Mode Bits 3 and 4 $FFFF
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Table 7-3 Interrupt Priority Level BitsTable 7-4 External InterruptxxL1 xxLO Enabled IPL IxL2 Trigger Mode0 0 No - 0 Level0 1 Yes 0 1 Negative Edge1 0 Yes 11 1 Yes 27.3.2.2 Exception Priorities Within an IPLIf more than one interrupt is pending when an instruction is executed, the processor willservice the interrupt with the highest priority level first. When multiple interrupt requestswith the same IPL are pending, a second fixed-priority structure within that IPL determineswhich interrupt the processor will service. The fixed priority <strong>of</strong> interrupts within anIPL and the interrupt enable bits for all interrupts are shown in Table 7-5.Table 7-5 Central Processor Interrupt Priorities Within an IPLPriority Exception Enabled By Bit No.X DataMemoryAddressLevel 3 (Nonmaskable)Highest Hardware RESET - - -III - - -NMI - - -Stack Error - - -Trace - - -Lowest SWI - - -Levels 0, 1,2 (Maskable)Higher IROA (External Interrupt) IROA Mode Bits o and 1 $FFFFLower IROB (External Interrupt) IROB Mode Bits 3 and 4 $FFFF
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