section 7 - Index of
section 7 - Index of section 7 - Index of
7.3.1 Interrupt TypesThe DSP56K relies on two types of interrupt routines: fast and long. The fast interruptfetches only two words and then automatically resumes execution of the main program;whereas, the long interrupt must be told to return to the main program by executing anRTI instruction. The fast routine consists of two automatically inserted interrupt instructionwords. These words can contain any unrestricted, single two-word instruction or anytwo one-word instructions (see Section A.9 in APPENDIX A - INSTRUCTION SETDETAILS for a list of restrictions). Fast interrupt routines are never interruptible.CAUTIONStatus is not preserved during a fast interrupt routine; therefore, instructionsthat modify status should not be used at the interrupt starting address andinterrupt starting address + 1.-If one of the instructions in the fast routine is a JSR, then a long interrupt routine isformed. The following actions occur during execution of the JSR instruction when itoccurs in the interrupt starting address or in the interrupt starting address +1:1. The PC (containing the return address) and the SR are stacked.2. The loop flag is reset.3. The scaling mode bits are reset.4. The IPL is raised to disallow further interrupts at the same or lower levels(except that hardware RESET, NMI, stack error, trace, and SWI can alwaysinterrupt).5. The trace bit in the SR is cleared (in the DSP56000/56001 only).The long interrupt routine should be terminated by an RTI. Long interrupt routines areinterruptible by higher priority interrupts. Figure 7-1 shows examples of fast and longinterrupts.7.3.2 Interrupt Priority StructureInterrupts are organized in a flexible priority structure. Each interrupt has an associatedinterrupt priority level (IPL) that can range from zero to three. Levels 0 (lowest level), 1,and 2 are maskable. Level 3 is the highest IPL and is not maskable. The only IPL 3 interruptsare RESET, illegal instruction interrupt (III), nonmaskable interrupt (NMI), stackerror, trace, and software interrupt (SWI). The interrupt mask bits (11, 10) in the SR reflectthe current priority level and indicate the IPL needed for an interrupt source to interruptthe processor (see Table 7-2). Interrupts are inhibited for all priority levels below the cur-
$0100MAINPROGRAMFAST INTERRUPT SERVICE ROUTINESSI RECEIVE DATA$0101$0102MACRMOVEINTERRUPTRECOGNIZED$0103$0104MACREP$OOOCMOVEPxxxxxx$0105MAC$0106(a) DSP56K Fast InterruptLONG INTERRUPT SERVICE ROUTINE$0100MAINPROGRAMSSI RECEIVE DATAWITH EXCEPTION STATUS$0101 MACR$0102 MOVE$0103 MAC$0104 REPJSR INSTRUCTIONFORMS LONGINTERRUPT SERVICE$0105 MAC$0106(b) DSP56K Long Inte~ruptFigure 7-1 Fast and Long Interrupt Examples
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7.3.1 Interrupt TypesThe DSP56K relies on two types <strong>of</strong> interrupt routines: fast and long. The fast interruptfetches only two words and then automatically resumes execution <strong>of</strong> the main program;whereas, the long interrupt must be told to return to the main program by executing anRTI instruction. The fast routine consists <strong>of</strong> two automatically inserted interrupt instructionwords. These words can contain any unrestricted, single two-word instruction or anytwo one-word instructions (see Section A.9 in APPENDIX A - INSTRUCTION SETDETAILS for a list <strong>of</strong> restrictions). Fast interrupt routines are never interruptible.CAUTIONStatus is not preserved during a fast interrupt routine; therefore, instructionsthat modify status should not be used at the interrupt starting address andinterrupt starting address + 1.-If one <strong>of</strong> the instructions in the fast routine is a JSR, then a long interrupt routine isformed. The following actions occur during execution <strong>of</strong> the JSR instruction when itoccurs in the interrupt starting address or in the interrupt starting address +1:1. The PC (containing the return address) and the SR are stacked.2. The loop flag is reset.3. The scaling mode bits are reset.4. The IPL is raised to disallow further interrupts at the same or lower levels(except that hardware RESET, NMI, stack error, trace, and SWI can alwaysinterrupt).5. The trace bit in the SR is cleared (in the DSP56000/56001 only).The long interrupt routine should be terminated by an RTI. Long interrupt routines areinterruptible by higher priority interrupts. Figure 7-1 shows examples <strong>of</strong> fast and longinterrupts.7.3.2 Interrupt Priority StructureInterrupts are organized in a flexible priority structure. Each interrupt has an associatedinterrupt priority level (IPL) that can range from zero to three. Levels 0 (lowest level), 1,and 2 are maskable. Level 3 is the highest IPL and is not maskable. The only IPL 3 interruptsare RESET, illegal instruction interrupt (III), nonmaskable interrupt (NMI), stackerror, trace, and s<strong>of</strong>tware interrupt (SWI). The interrupt mask bits (11, 10) in the SR reflectthe current priority level and indicate the IPL needed for an interrupt source to interruptthe processor (see Table 7-2). Interrupts are inhibited for all priority levels below the cur-
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