section 7 - Index of

the main uses of interrupts is to transfer data between OSP memory or registers and aperipheral device. When such an interrupt occurs, a limited context switch with minimaloverhead is ideal. A fast interrupt accomplishes a limited context switch. The processorrelies on a long interrupt when it must accomplish a more complex task to service theinterrupt. Fast interrupts and long interrupts are described in more detail in Section7.3.1.There are many sources for interrupts on the OSP56K family of chips, and some of thesesources can generate more than one interrupt. The OSP56K family of processors featuresa prioritized interrupt vector scheme with 32 vectors to provide fast interrupt service.The interrupt priority structure is discussed in Section 7.3.2. The following listoutlines how the OSP56K processes interrupts:1. A hardware interrupt is synchronized with the OSP clock, and the interruptpending flag for that particular hardware interrupt is set. An interrupt sourcecan have only one interrupt pending at any given time.2. All pending interrupts (external and internal) are arbitrated to select whichinterrupt will be processed. The arbiter automatically ignores any interruptswith an IPL lower than the interrupt mask level in the SR and selects theremaining interrupt with the highest IPL.3. The interrupt controller then freezes the program counter (PC) and fetches twoinstructions at the two interrupt vector addresses associated with the selectedinterrupt.-. 4. The interrupt controller jams the two instructions into the instruction streamand releases the PC, which is used for the next instruction fetch. The nextinterrupt arbitration then begins.If neither instruction is a change of program-flow instruction (Le., a JSR), the state of themachine is not saved on the stack, and a fast interrupt is executed. A long interruptoccurs if one of the interrupt instructions fetched is a JSR instruction. The PC is immediatelyreleased, the SR and the PC are saved in the stack, and the jump instruction controlswhere the next instruction shall be fetched. While either an unconditional jump or aconditional jump can be used to form a long interrupt, they do not store the PC on thestack. Therefore, there is no return path. ./Activities 2 and 3 listed above require two additional control cycles, which effectivelymake the Interrupt pipeline five levels deep.