section 7 - Index of
section 7 - Index of section 7 - Index of
Each instruction requires a minimum of three instruction cycles (12 clock phases) to befetched, decoded, and executed. This means that there is a delay of three instructioncycles on powerup to fill the pipe. A new instruction may begin immediately following theprevious instruction. Two-word instructions require a minimum of four instruction cyclesto execute (three cycles for the first instruction word to move through the pipe and executeand one more cycle for the second word to execute). A new instruction may startafter two instruction cycles.-The pipeline is normally transparent to the user. However, there are certain instructionsequencedependent situations where the pipeline will affect the program execution.Such situations are best described by case studies. Most of these restricted sequencesoccur because 1) all addresses are formed during instruction decode, or 2) they are theresult of contention for an internal resource such as the status register (SR). If the executionof an instruction depends on the relative location of the instruction in a sequence ofinstructions, there is a pipeline effect. To test for a suspected pipeline effect, comparebetween the execution of the suspect instruction 1) when it directly follows the previousinstruction and 2) when four NOPs are inserted between the two. If there is a difference,it is caused by a pipeline effect. The DSP56K assembler flags instruction sequences withpotential pipeline effects so that the user can determine if the operation will execute asexpected.Case 1: The following two examples show similar code sequences.1. No pipeline effect:ORI #xx,CCRJcc xxxx;Changes eeR at the end of execution time slot;Reads condition codes in SR in its execution time slotThe Jcc will test the bits modified by the ORI without any pipeline effect in the code segmentabove.2. Instruction that started execution during decode:ORI #04,OMR ;Sets DE bit at execution time slotMOVE x:$100,a ;Reads external RAM instead of internal ROMA pipeline effect occurs in example 2 because the address of the MOVE is formed at itsdecode time before the ORI changes the DE bit (which changes the memory map) in theORI's execution time slot. The following code produces the expected results of readingthe internal ROM:ORI #04,OMRNOPMOVE x:$1 OO,a;Sets DE bit at execution time slot;Delays the MOVE so it will read the updated memory map;Reads internal ROM
Case 2: One of the more common sequences where pipeline effects are apparent is asfollows:;Move a number into register Rn (n=0-7).MOVE #xx,RnMOVE X:(Rn),A;Use the new contents of Rn to address memory.In this case, before the first MOVE instruction has written Rn during its execution cycle,the second MOVE has accessed the old Rn, using the old contents of Rn. This isbecause the address for indirect moves is formed during the decode cycle. This overlappinginstruction execution in the pipeline causes the pipeline effect. One instruction cycleshould be allowed after an address register has been written by a MOVE instructionbefore the new contents are available for use as an address register by another MOVEinstruction. The proper instruction sequence is as follows:MOVEXO,RnNOPMOVE X:(Rn),A;Move a number into register Rn.;Execute any instruction or instruction;sequence not using Rn.Use the new contents of Rn.Case 3: A situation related to Case 2 can be seen in the boot ROM code shown in APPENDIX A of the DSP56001 Technical Data Sheet. At the end of the bootstrap operation,the operation mode register (OMR) is changed to mode #2, and then the program that wasloaded is executed. This process is accomplished in the last three instructions:--BOOTEND MOVEC #2,OMR ;Set the operating mode to 2;(and trigger an exit from;bootstrap mode).ANDI #$O,CCR ;Clear SR as if RESET and;introduce delay needed for;Op. Mode change.JMP
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Case 2: One <strong>of</strong> the more common sequences where pipeline effects are apparent is asfollows:;Move a number into register Rn (n=0-7).MOVE #xx,RnMOVE X:(Rn),A;Use the new contents <strong>of</strong> Rn to address memory.In this case, before the first MOVE instruction has written Rn during its execution cycle,the second MOVE has accessed the old Rn, using the old contents <strong>of</strong> Rn. This isbecause the address for indirect moves is formed during the decode cycle. This overlappinginstruction execution in the pipeline causes the pipeline effect. One instruction cycleshould be allowed after an address register has been written by a MOVE instructionbefore the new contents are available for use as an address register by another MOVEinstruction. The proper instruction sequence is as follows:MOVEXO,RnNOPMOVE X:(Rn),A;Move a number into register Rn.;Execute any instruction or instruction;sequence not using Rn.Use the new contents <strong>of</strong> Rn.Case 3: A situation related to Case 2 can be seen in the boot ROM code shown in APPENDIX A <strong>of</strong> the DSP56001 Technical Data Sheet. At the end <strong>of</strong> the bootstrap operation,the operation mode register (OMR) is changed to mode #2, and then the program that wasloaded is executed. This process is accomplished in the last three instructions:--BOOTEND MOVEC #2,OMR ;Set the operating mode to 2;(and trigger an exit from;bootstrap mode).ANDI #$O,CCR ;Clear SR as if RESET and;introduce delay needed for;Op. Mode change.JMP
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