section 7 - Index of

FigureNumberList of Figures (Continued)TitlePageNumber7-13 Interrupting an REP Instruction ................................... 7-347-14 Interrupting Sequential REP Instructions ........................... 7-357-15 Wait Instruction Timing ......................................... 7-367-16 Simultaneous Wait Instruction and Interrupt ......................... 7-377-17 STOP Instruction Sequence ................................... " 7-387-18 STOP Instruction Sequence Followed by IRQA ...................... 7-397-19 STOP Instruction Sequence Recovering with RESET ................. 7-428-1 Port A Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-49-1 Pll Block Diagram ....................................... . . . .. 9-39-2 DSP56K Block Diagram ........................................ 9-49-3 Pll Control Register (PCTl) .................................... 9-610-1 OnCE Block Diagram .......................................... 10-310-2 DSP56K Block Diagram ........................................ 10-410-3 OnCE Controller and Serial Interface ............................ " 10-610-4 OnCE Command Register ...................................... 10-710-5 OnCE Status and Control Register (OSCR) . . . . . . . . . . . . . . . . . . . . . . . .. 10-910-6 OnCE Memory Breakpoint logic .................................. 10-1210-7 OnCE Trace logic Block Diagram ................................ 10-1410-8 OnCE Pipeline Information and GOB Registers ...................... 10-1610-9 OnCE PAB FIFO ....................................... .' ...... 10-17B-1 20-Tap FIR Filter Example ...................................... B-5B-2 Radix 2, In-Place, Decimation-In-Time FFT .......................... B-7B-3 8-Pole 4-Multiply Cascaded Canonic IIR Filter . . . . . . . . . . . . . . . . . . . . . . . B-9B-4 lMS FIR Adaptive Filter ........................................ B-11B-5 Real Input FFT Based on Glenn Bergland Algorithm ................... B-12