section 7 - Index of

7.1 PROCESSING STATESThe DSP56K processor is always in one of five processing states: normal, exception,reset, wait, or stop. This section describes each of the processing states.7.2 NORMAL PROCESSING STATEThe normal processing state is associated with instruction execution. Details about normalprocessing of the individual instructions can be found in APPENDIX A - INSTRUC­TION SET DETAILS. Instructions are executed using a three-stage pipeline, which isdescribed in the following paragraphs.7.2.1 Instruction PipelineDSP56K instruction execution occurs in a three-stage pipeline, which allows mostinstructions to execute at a rate of one instruction per instruction cycle. However, certaininstructions require additional time to execute: instructions longer than one word, instructionsusing an addressing mode that requires more than one cycle, and instructions thatcause a control-flow change. In the latter case, a cycle is needed to clear the pipeline.Pipelining allows instruction executions to overlap so that the fetch-decode-executeoperations of a given instruction occur concurrently with the fetch-decode-execute operationsof other instructions. Specifically, while the processor is executing one instruction,it is decoding the next instruction, and fetching the next instruction from program memory.The processor fetches only one word per cycle, so if an instruction is two words inlength, it fetches the additional word before it fetches the next instruction.Table 7-1 demonstrates pipelining. F1, D1, and E1 refer to the fetch, decode, and executeoperations, respectively, of the first instruction. The third instruction, which containsan instruction extension word, takes two instruction cycles to execute. The extensionword will be either an absolute address or immediate data. Although it takes threeinstruction cycles for the pipeline to fill and the first instruction to execute, an instructionusually executes on each instruction cycle thereafter.Table 7-1 Instruction PipeliningInstruction CycleOperation1 2 3 4 5 6 7 . ·Fetch F1 F2 F3 F3e F4 FS F6 . ·Oecode 01 02 03 03e 04 05 . Execute E1 E2 E3 E3e E4 . ·