section 7 - Index of

section 7 - Index of section 7 - Index of

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-47~3XlXIa 23XO55I I A223 8755I I 6223 87DATA ARITHMETIC LOGIC UNITINPUT REGISTERSI47Ia 23ACCUMULATOR REGISTERSAIAlIa 23 023BI61Ia 23 023YYlIYOIa 23a~CCOQQC:~:=::=2!:=~ ::Q=:~::::::I'O'OQ::a:~~::::::a::o::::O:Q::cmo :CIfQ:::o:coC:::Q: ::'Oco:::: ::::Q:::CQO~C: ~::C2:::C::Q2:Q:: : :::~ ,r~::2:::: Q;~IC:C~ ::~'-~.... ~1~:mQ:mm:Q::J:: UQO!Qc:::mmt:: H:ncH :m::N: :::tam;:: QU::: :m::cv;;:;:;~:~;:~EN~~;~;~~:Q~:~CI~;::::l:: :::mQ: ::ml:: ::m.m aHQQQ~Q::c:m ceca ~~~l23 1615 a 23 1615 a 23 1615 aR7 N7 M7* * *R6N6M6***R5N5M5R4N4M4- *- *R3N3M3***R2N2M2***R1N1M1**RONOMO***POINTERREGISTERSOFFSETREGISTERSAOsoMODIFIERREGISTERSaIaaIaUPPER FILELOWER FILE23 1615PROGRAM CONTROL UNIT023 1615LOOP ADDRESSREGISTER (LA)LOOP COUNTER (LC)r2,;;...3....;1..:,6..:..15'--_____ --,O 23 1615 87I * I II * I MR I CCR'---1-- P - R - O -=G-:R-=A-:-M---' STATUSCOUNTER (PC) REGISTER (SR)31 SSH 1615 SSL23 6 5I--____ t--___ -jl _I * I23 8 7 6 5 4 3 2 1 aI1* Isol*IMCI YO IOEIM6IMAIOPERATING MODE REGISTER (OMR)STACK POINTER (SP)* READ AS ZERO, SHOULD BE WRIDENWITH ZERO FOR FUTURE COMPATIBILITYIt READ AS SIGN EXTENSION BITS,WRIDEN AS DON'T CARESYSTEM STACKFigure 6-1 DSP56K Central Processing Module Programming Model

shown in Figure 6-2. Most instructions specify data movement on the XDB, YDB, and dataALU operations in the same operation word. The DSP56K performs each of these operationsin parallel.~ 87 0I OPCODEDATA BUS MOVEMENT IxlxlxlxlxlxlxlxOPTIONAL EFFECTIVE ADDRESS EXTENSIONFigure 6-2 General Format of an Instruction Operation WordThe data bus movement field provides the operand reference type. It selects the type ofmemory or register reference to be made, the direction of transfer, and the effectiveaddress(es) for data movement on the XDB and YDB. This field may require additionalinformation to fully specify the operand for certain addressing modes. An effectiveaddress extension word following the operation word provides an immediate data addressor an absolute address if required (see Section 6.3.5.3 for the description of specialaddressing modes). Examples of operations that may include the extension word includethe move operations X:, X:R, V:, R:Y, and L:. Additional information is presented inAPPENDIX A - INSTRUCTION SET DETAILS.The opcode field of the operation word specifies the data ALU operation or the programcontrol unit operation to be performed, and any additional operands required by theinstruction. Only those data ALU and program control unit operations that can accompanydata bus movement will be specified in the opcode field of the instruction. Other data ALU,program control unit, and all address ALU operations will be specified in an instructionword with a different format. These formats include operation words which contain shortimmediate data or short absolute addresses (see Section 6.3.5.3 for the description ofspecial addressing modes).6.3.1 Operand SizesOperand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, aword is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (seeFigure 6-3). The operand size for each instruction is either explicitly encoded in theinstruction or implicitly defined by the instruction operation. Implicit instructions supportsome subset of the five sizes shown in Figure 6-3.

shown in Figure 6-2. Most instructions specify data movement on the XDB, YDB, and dataALU operations in the same operation word. The DSP56K performs each <strong>of</strong> these operationsin parallel.~ 87 0I OPCODEDATA BUS MOVEMENT IxlxlxlxlxlxlxlxOPTIONAL EFFECTIVE ADDRESS EXTENSIONFigure 6-2 General Format <strong>of</strong> an Instruction Operation WordThe data bus movement field provides the operand reference type. It selects the type <strong>of</strong>memory or register reference to be made, the direction <strong>of</strong> transfer, and the effectiveaddress(es) for data movement on the XDB and YDB. This field may require additionalinformation to fully specify the operand for certain addressing modes. An effectiveaddress extension word following the operation word provides an immediate data addressor an absolute address if required (see Section 6.3.5.3 for the description <strong>of</strong> specialaddressing modes). Examples <strong>of</strong> operations that may include the extension word includethe move operations X:, X:R, V:, R:Y, and L:. Additional information is presented inAPPENDIX A - INSTRUCTION SET DETAILS.The opcode field <strong>of</strong> the operation word specifies the data ALU operation or the programcontrol unit operation to be performed, and any additional operands required by theinstruction. Only those data ALU and program control unit operations that can accompanydata bus movement will be specified in the opcode field <strong>of</strong> the instruction. Other data ALU,program control unit, and all address ALU operations will be specified in an instructionword with a different format. These formats include operation words which contain shortimmediate data or short absolute addresses (see Section 6.3.5.3 for the description <strong>of</strong>special addressing modes).6.3.1 Operand SizesOperand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, aword is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (seeFigure 6-3). The operand size for each instruction is either explicitly encoded in theinstruction or implicitly defined by the instruction operation. Implicit instructions supportsome subset <strong>of</strong> the five sizes shown in Figure 6-3.

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