section 7 - Index of
section 7 - Index of section 7 - Index of
-47~3XlXIa 23XO55I I A223 8755I I 6223 87DATA ARITHMETIC LOGIC UNITINPUT REGISTERSI47Ia 23ACCUMULATOR REGISTERSAIAlIa 23 023BI61Ia 23 023YYlIYOIa 23a~CCOQQC:~:=::=2!:=~ ::Q=:~::::::I'O'OQ::a:~~::::::a::o::::O:Q::cmo :CIfQ:::o:coC:::Q: ::'Oco:::: ::::Q:::CQO~C: ~::C2:::C::Q2:Q:: : :::~ ,r~::2:::: Q;~IC:C~ ::~'-~.... ~1~:mQ:mm:Q::J:: UQO!Qc:::mmt:: H:ncH :m::N: :::tam;:: QU::: :m::cv;;:;:;~:~;:~EN~~;~;~~:Q~:~CI~;::::l:: :::mQ: ::ml:: ::m.m aHQQQ~Q::c:m ceca ~~~l23 1615 a 23 1615 a 23 1615 aR7 N7 M7* * *R6N6M6***R5N5M5R4N4M4- *- *R3N3M3***R2N2M2***R1N1M1**RONOMO***POINTERREGISTERSOFFSETREGISTERSAOsoMODIFIERREGISTERSaIaaIaUPPER FILELOWER FILE23 1615PROGRAM CONTROL UNIT023 1615LOOP ADDRESSREGISTER (LA)LOOP COUNTER (LC)r2,;;...3....;1..:,6..:..15'--_____ --,O 23 1615 87I * I II * I MR I CCR'---1-- P - R - O -=G-:R-=A-:-M---' STATUSCOUNTER (PC) REGISTER (SR)31 SSH 1615 SSL23 6 5I--____ t--___ -jl _I * I23 8 7 6 5 4 3 2 1 aI1* Isol*IMCI YO IOEIM6IMAIOPERATING MODE REGISTER (OMR)STACK POINTER (SP)* READ AS ZERO, SHOULD BE WRIDENWITH ZERO FOR FUTURE COMPATIBILITYIt READ AS SIGN EXTENSION BITS,WRIDEN AS DON'T CARESYSTEM STACKFigure 6-1 DSP56K Central Processing Module Programming Model
shown in Figure 6-2. Most instructions specify data movement on the XDB, YDB, and dataALU operations in the same operation word. The DSP56K performs each of these operationsin parallel.~ 87 0I OPCODEDATA BUS MOVEMENT IxlxlxlxlxlxlxlxOPTIONAL EFFECTIVE ADDRESS EXTENSIONFigure 6-2 General Format of an Instruction Operation WordThe data bus movement field provides the operand reference type. It selects the type ofmemory or register reference to be made, the direction of transfer, and the effectiveaddress(es) for data movement on the XDB and YDB. This field may require additionalinformation to fully specify the operand for certain addressing modes. An effectiveaddress extension word following the operation word provides an immediate data addressor an absolute address if required (see Section 6.3.5.3 for the description of specialaddressing modes). Examples of operations that may include the extension word includethe move operations X:, X:R, V:, R:Y, and L:. Additional information is presented inAPPENDIX A - INSTRUCTION SET DETAILS.The opcode field of the operation word specifies the data ALU operation or the programcontrol unit operation to be performed, and any additional operands required by theinstruction. Only those data ALU and program control unit operations that can accompanydata bus movement will be specified in the opcode field of the instruction. Other data ALU,program control unit, and all address ALU operations will be specified in an instructionword with a different format. These formats include operation words which contain shortimmediate data or short absolute addresses (see Section 6.3.5.3 for the description ofspecial addressing modes).6.3.1 Operand SizesOperand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, aword is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (seeFigure 6-3). The operand size for each instruction is either explicitly encoded in theinstruction or implicitly defined by the instruction operation. Implicit instructions supportsome subset of the five sizes shown in Figure 6-3.
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
- Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
- Page 61 and 62: •••••••• _ ........
- Page 63 and 64: 4.4.1 Address Register Indirect Mod
- Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
- Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
- Page 69 and 70: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
- Page 71 and 72: Table 4-2 Address Modifier SummaryM
- Page 73 and 74: ADDRESS -f-_POINTERUPPER BOUNDARYiM
- Page 75 and 76: EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
- Page 77 and 78: oundary gives a 16-bit binary numbe
- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
- Page 101: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 144 and 145: interrupts makes it very useful for
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
- Page 148 and 149: 7.3.3.3 Other Interrupt SourcesOthe
- Page 150 and 151: 7.3.4 Interrupt ArbitrationInterrup
shown in Figure 6-2. Most instructions specify data movement on the XDB, YDB, and dataALU operations in the same operation word. The DSP56K performs each <strong>of</strong> these operationsin parallel.~ 87 0I OPCODEDATA BUS MOVEMENT IxlxlxlxlxlxlxlxOPTIONAL EFFECTIVE ADDRESS EXTENSIONFigure 6-2 General Format <strong>of</strong> an Instruction Operation WordThe data bus movement field provides the operand reference type. It selects the type <strong>of</strong>memory or register reference to be made, the direction <strong>of</strong> transfer, and the effectiveaddress(es) for data movement on the XDB and YDB. This field may require additionalinformation to fully specify the operand for certain addressing modes. An effectiveaddress extension word following the operation word provides an immediate data addressor an absolute address if required (see Section 6.3.5.3 for the description <strong>of</strong> specialaddressing modes). Examples <strong>of</strong> operations that may include the extension word includethe move operations X:, X:R, V:, R:Y, and L:. Additional information is presented inAPPENDIX A - INSTRUCTION SET DETAILS.The opcode field <strong>of</strong> the operation word specifies the data ALU operation or the programcontrol unit operation to be performed, and any additional operands required by theinstruction. Only those data ALU and program control unit operations that can accompanydata bus movement will be specified in the opcode field <strong>of</strong> the instruction. Other data ALU,program control unit, and all address ALU operations will be specified in an instructionword with a different format. These formats include operation words which contain shortimmediate data or short absolute addresses (see Section 6.3.5.3 for the description <strong>of</strong>special addressing modes).6.3.1 Operand SizesOperand sizes are defined as follows: a byte is 8 bits long, a short word is16 bits long, aword is 24 bits long, a long word is 48 bits long, and an accumulator is 56 bits long (seeFigure 6-3). The operand size for each instruction is either explicitly encoded in theinstruction or implicitly defined by the instruction operation. Implicit instructions supportsome subset <strong>of</strong> the five sizes shown in Figure 6-3.