MC95FB204 - abov.co.kr

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MC95FB20416.3 ADC OperationAlign bit set “0”ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4ADCRH[7:0]ADCRL[7:4]ADCRL[3:0] bits are “0”Align bit set “1”ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRL3 ADCRL2 ADCRL1 ADCRL0ADCRH[4:0]ADCRH[7:4] bits are “0”ADCRL[7:0]Figure 16.4 ADC Operation for Align bit88 July 17, 2012 Ver.1.7
MC95FB204SET ADCM2Select ADC Clock & Data Align Bit.SET ADCMADC enable & Select AN Input Channel.Converting STARTStart ADC Conversion.NAFLAG = 1?YIf Conversion is completed, AFLG is set “1” and ADCinterrupt is occurred.READ ADCRH/LAfter Conversion is completed, read ADCRH and ADCRL.ADC ENDFigure 16.5 A/D Converter Operation Flow16.4 Register MapTable 16-1 Register MapName Address Dir Default DescriptionADCM 9AH R/W 8FH A/D Converter Mode RegisterADCRH 9BH R - A/D Converter Result High RegisterADCRL 9CH R - A/D Converter Result Low RegisterADCM2 9BH R/W 01H A/D Converter Mode 2 RegisterALCPR0 92H R/W 00H ADC Leakage Current Protection Register 0ALCPR1 93H R/W 00H ADC Leakage Current Protection Register 116.5 ADC Register descriptionThe ADC Register consists of A/D Converter Mode Register (ADCM), A/D Converter Result HighRegister (ADCRH), A/D Converter Result Low Register (ADCRL), A/D Converter Mode 2 Register(ADCM2).July 17, 2012 Ver.1.7 89
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ABOV SEMICONDUCTOR Co., Ltd.8-BIT M
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MC95FB204VERSION 0.2 Preliminary (S
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MC95FB20410.5 Interrupt Sequence ..
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MC95FB204List of FiguresFigure 1.1
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MC95FB204List of TablesTable 1-1 Or
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MC95FB2041.3 Ordering InformationTa
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MC95FB204Figure 1.2 Single Programm
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MC95FB204MC95FB2043. Pin Assignment
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MC95FB204Figure 4.2 20 pin TSSOP pa
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MC95FB2046. Port Structures6.1 Gene
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MC95FB2047. Electrical Characterist
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MC95FB204Note) -STOP1: WDT running
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MC95FB2047.9 AC CharacteristicsTabl
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MC95FB2047.11 Typical Characteristi
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MC95FB204FFFFH0FFFH4KBytes0000HFigu
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MC95FB2047FH7F776F7E766E7D756D7C 7B
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MC95FB204July 17, 2012 Ver.1.7 33
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MC95FB204Address Function Symbol R/
Page 37 and 38: MC95FB204Address Function Symbol R/
Page 39 and 40: MC95FB204ACF0Auxiliary Carry FlagGe
Page 41 and 42: MC95FB2049.2.6 Register MapTable 9-
Page 43 and 44: MC95FB2049.4 P1 Port9.4.1 P1 Port D
Page 45 and 46: MC95FB2049.5 P2 Port9.5.1 P2 Port D
Page 47 and 48: MC95FB20410. Interrupt Controller10
Page 49 and 50: MC95FB20410.3 Block DiagramIEDS0IE[
Page 51 and 52: MC95FB2041IE.EA Flag 1IEx.y 123Pr
Page 53 and 54: MC95FB20410.7 Multi InterruptIf two
Page 55 and 56: MC95FB20410.10 Saving/Restore Gener
Page 57 and 58: MC95FB204IE2 AAH R/W 00H Interrupt
Page 59 and 60: MC95FB204R R R/W R/W R/W R/W R/W R/
Page 61 and 62: MC95FB20411. CC/CV BlockCC/CV means
Page 63 and 64: MC95FB204When the current of R SENS
Page 65 and 66: MC95FB20412. Clock Generator12.1 Ov
Page 67 and 68: MC95FB204Note) by CBYS bit, reflect
Page 69 and 70: MC95FB20413.4 Bit Interval Timer Re
Page 71 and 72: MC95FB204WDTMR 8D R/W 00H Watch Dog
Page 73 and 74: MC95FB20415. Timer/PWM15.1 Overview
Page 75 and 76: MC95FB204Match with T0DR/T1DRT0DR/T
Page 77 and 78: MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
Page 79 and 80: MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
Page 81 and 82: MC95FB204T1CR[1:0] = 10 H(2us)PWM1H
Page 83 and 84: MC95FB204T0 (Timer 0 Register: Read
Page 85 and 86: MC95FB204Initial value : 00HCDR1[7:
Page 87: MC95FB20416.2 Block Diagram÷2fxPre
Page 91 and 92: MC95FB204ADDM11 ADDM10 ADDM9 ADDM8
Page 93 and 94: MC95FB20417. Power Down Operation17
Page 95 and 96: MC95FB20417.4 STOP modeThe power co
Page 97 and 98: MC95FB20417.5.1 Register MapTable 1
Page 99 and 100: MC95FB20418.4 RESET Noise Canceller
Page 101 and 102: MC95FB204:VDD Input:Internal OSCRes
Page 103 and 104: MC95FB20419. On-chip Debug System19
Page 105 and 106: MC95FB204Figure 19.2 10-bit transmi
Page 107 and 108: MC95FB204Acknowledge bittransmissio
Page 109 and 110: MC95FB20420.2.2 Register descriptio
Page 111 and 112: MC95FB2047 6 5 4 3 2 1 0ARL7 ARL6 A
Page 113 and 114: MC95FB20420.3 Memory map20.3.1 Flas
Page 115 and 116: MC95FB204Master ResetPage Buffer Re
Page 117 and 118: Step 5. Set erase mode. FMR:1001_00
Page 119 and 120: MC95FB20420.4.2 Summary of Flash Pr
Page 121 and 122: MC95FB20420.6 SecurityMC95FB204 pro
Page 123 and 124: MC95FB20422. APPENDIX22.1 Instructi
Page 125 and 126: MC95FB204SETB C Set carry 1 1 D3SET
Page 127: MC95FB20422.2.3 Preventative measur
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MC95FB204 - abov.co.kr

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