MC95FB204 - abov.co.kr

MC95FB204Figure 15.11 Example of Changing the Period in Absolute Duty Cycle at 4Mhz ................................ 81Figure 16.1 ADC Block Diagram ......................................................................................................... 87Figure 16.2 A/D Analog Input Pin Connecting Capacitor .................................................................... 87Figure 16.3 A/D Power(AVDD) Pin Connecting Capacitor ................................................................. 87Figure 16.4 ADC Operation for Align bit ............................................................................................. 88Figure 16.5 A/D Converter Operation Flow ......................................................................................... 89Figure 17.1 IDLE Mode Release Timing by External Interrupt ........................................................... 94Figure 17.2 STOP Mode Release Timing by External Interrupt ........................................................... 95Figure 17.3 STOP1, 2 Mode Release Flow .......................................................................................... 96Figure 18.1 RESET Block Diagram ..................................................................................................... 98Figure 18.2 Reset noise canceller time diagram ................................................................................... 99Figure 18.3 Fast VDD rising time......................................................................................................... 99Figure 18.4 Internal RESET Release Timing On Power-Up .............................................................. 100Figure 18.5 Configuration timing when Power-on ............................................................................. 100Figure 18.6 Boot Process Wave Form ................................................................................................ 101Figure 18.7 Timing Diagram after RESET ......................................................................................... 102Figure 18.8 Oscillator generating waveform example ........................................................................ 102Figure 19.1 Block Diagram of On-chip Debug System ...................................................................... 104Figure 19.2 10-bit transmission packet ............................................................................................... 105Figure 19.3 Data transfer on the twin bus ........................................................................................... 105Figure 19.4 Bit transfer on the serial bus ............................................................................................ 106Figure 19.5 Start and stop condition ................................................................................................... 106Figure 19.6 Acknowledge on the serial bus ........................................................................................ 106Figure 19.7 Clock synchronization during wait procedure ................................................................. 107Figure 19.8 Connection of transmission ............................................................................................. 107Figure 20.1 Flash Memory Map ......................................................................................................... 113Figure 20.2 Address configuration of Flash memory ......................................................................... 113Figure 20.3 The sequence of page program and erase of Flash memory ............................................ 114Figure 20.4 The sequence of bulk erase of Flash memory ................................................................. 115Figure 20.5 ISP mode ......................................................................................................................... 1208 July 17, 2012 Ver.1.7