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<strong>MC95FB204</strong>Match with T0DR/T1DRT0DR/T1DRValuen-2n-1nCount Pulse PeriodPCPUp-<strong>co</strong>unt6543210Interrupt Period= PCP x (n+1)TIMETimer 0, 1(T0IF, T1IF)InterruptOccurInterruptOccurInterruptOccurInterruptFigure 15.2 Timer/Event Counter0, 1 ExampleT0DR/T1DRValueDisableEnableClear&StartSTOPUp-<strong>co</strong>untTIMETimer 0, 1(T0IF, T1IF)InterruptOccurInterruptOccurInterruptT0ST, T1STStart&StopT0ST,T1ST = 1T0ST,T1ST = 0T0ST,T1ST = 1T0CN, T1CNControl <strong>co</strong>untT0CN,T1CN = 1T0CN,T1CN = 1T0CN,T1CN = 015.3 16-Bit Timer/Counter ModeFigure 15.3 Operation Example of Timer/Event Counter0, 1The timer register is being run with all 16bits. A 16-bit timer/<strong>co</strong>unter register T0, T1 are incremented from0000H to FFFFH until it matches T0DR, T1DR and then resets to 0000H. the match output generates the Timer0 interrupt ( no timer 1 interrupt). The clock source is selected from T0CK[2:0] and T1CK[1:0] must set 11bJuly 17, 2012 Ver.1.7 75
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