MC95FB204 - abov.co.kr

MC95FB204List of FiguresFigure 1.1 OCD Debugger and Pin description .................................................................................... 12Figure 1.2 Single Programmer .............................................................................................................. 13Figure 1.3 Gang Programmer ............................................................................................................... 13Figure 2.1 MC95FB204 block diagram ................................................................................................ 14Figure 3.1 MC95FB204 20 SOP/TSSOP Pin assignment .................................................................... 15Figure 4.1 20 pin SOP package ............................................................................................................ 16Figure 4.2 20 pin TSSOP package ........................................................................................................ 17Figure 6.1 General Purpose I/O Port ..................................................................................................... 19Figure 6.2 External Interrupt I/O Port ................................................................................................... 20Figure 7.1 AC Timing ........................................................................................................................... 25Figure 8.1 Program memory ................................................................................................................. 29Figure 8.2 Data memory map ............................................................................................................... 30Figure 8.3 Lower 128 bytes RAM ........................................................................................................ 31Figure 9.1 Debounce Function .............................................................................................................. 46Figure 10.1 External Interrupt Description ........................................................................................... 48Figure 10.2 Block Diagram of Interrupt ............................................................................................... 49Figure 10.3 Interrupt Vector Address Table ......................................................................................... 51Figure 10.4 Interrupt flag result effective Timing ................................................................................ 52Figure 10.5 Interrupt Enable Register effective Timing ....................................................................... 52Figure 10.6 Execution of Multi Interrupt .............................................................................................. 53Figure 10.7 Interrupt Response Timing Diagram ................................................................................. 54Figure 10.8 Correspondence between vector Table address and the entry address of ISP ................... 54Figure 10.9 Saving/Restore Process Diagram & Sample Source .......................................................... 55Figure 10.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction .......................... 55Figure 11.1 CC/CV charging process ................................................................................................... 61Figure 11.2 CC/CV application block diagram .................................................................................... 62Figure 12.1 Clock Generator Block Diagram ....................................................................................... 65Figure 13.1 BIT Block Diagram ........................................................................................................... 68Figure 14.1 WDT Block Diagram ........................................................................................................ 70Figure 14.2 WDT Interrupt Timing Waveform .................................................................................... 72Figure 15.1 8 Bit Timer/Event Counter0, 1 Block Diagram ................................................................. 74Figure 15.2 Timer/Event Counter0, 1 Example .................................................................................... 75Figure 15.3 Operation Example of Timer/Event Counter0, 1 ............................................................... 75Figure 15.4 16 Bit Timer/Event Counter0, 1 Block Diagram ............................................................... 76Figure 15.5 8-bit Capture Mode for Timer0, 1 ..................................................................................... 77Figure 15.6 Input Capture Mode Operation of Timer 0, 1 .................................................................... 78Figure 15.7 Express Timer Overflow in Capture Mode ....................................................................... 78Figure 15.8 16-bit Capture Mode of Timer 0, 1 .................................................................................... 79Figure 15.9 PWM Mode ....................................................................................................................... 80Figure 15.10 Example of PWM at 4MHz ............................................................................................. 80July 17, 2012 Ver.1.7 7