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<strong>MC95FB204</strong>13.4 Bit Interval Timer Register descriptionThe Bit Interval Timer Register <strong>co</strong>nsists of BIT Clock <strong>co</strong>ntrol register (BCCR) and Basic IntervalTimer register (BITR). If BCLR bit set to ‘1’, BITR be<strong>co</strong>mes ‘0’ and then <strong>co</strong>unts up. After 1 machinecycle, BCLR bit is cleared as ‘0’ automatically.13.5 Register description for Bit Interval TimerBCCR (BIT Clock Control Register) : 8BH7 6 5 4 3 2 1 0BITF - - - BCLR BCK2 BCK1 BCK0R/W R R R R/W R/W R/W R/WInitial value : 05HBITF When BIT Interrupt occurs, this bit be<strong>co</strong>mes ‘1’. For clearing bit, write ‘0’to this bit.0 no generation1 generationBCLR If BCLK Bit is written to ‘1’, BIT Counter is cleared as ‘0’BCK[2:0]0 Free Running1 Clear CounterSelect BIT overflow periodBCK2 BCK1 BCK00 0 0 f BIT / 20 0 1 f BIT / 40 1 0 f BIT / 80 1 1 f BIT / 161 0 0 f BIT / 321 0 1 f BIT / 64 (default)1 1 0 f BIT / 1281 1 1 f BIT / 256BITR (Basic Interval Timer Register) : 8CH7 6 5 4 3 2 1 0BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0R R R R R R R RInitial value : 00HBIT[7:0]BIT CounterJuly 17, 2012 Ver.1.7 69
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