MC95FB204 - abov.co.kr

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MC95FB20416.3 ADC Operation ........................................................................................................................................ 8816.4 Register Map ............................................................................................................................................ 8916.5 ADC Register description ........................................................................................................................ 8916.6 Register description for ADC .................................................................................................................. 9017. Power Down Operation .................................................................................................................................. 9317.1 Overview .................................................................................................................................................. 9317.2 Peripheral Operation In IDLE/STOP Mode ............................................................................................. 9317.3 IDLE mode .............................................................................................................................................. 9317.4 STOP mode .............................................................................................................................................. 9517.5 Release Operation of STOP1, 2 Mode ..................................................................................................... 9618. RESET ............................................................................................................................................................ 9818.1 Overview .................................................................................................................................................. 9818.2 Reset source ............................................................................................................................................. 9818.3 Block Diagram ......................................................................................................................................... 9818.4 RESET Noise Canceller ........................................................................................................................... 9918.5 Power On RESET .................................................................................................................................... 9918.6 External RESETB Input ......................................................................................................................... 10219. On-chip Debug System ................................................................................................................................. 10319.1 Overview ................................................................................................................................................ 10319.2 Two-pin external interface ..................................................................................................................... 10420. Memory Programming.................................................................................................................................. 10820.1 Overview ................................................................................................................................................ 10820.2 Flash Control and status register ............................................................................................................ 10820.3 Memory map .......................................................................................................................................... 11320.4 Serial In-System Program Mode ............................................................................................................ 11420.5 Mode entrance method of ISP ................................................................................................................ 12020.6 Security .................................................................................................................................................. 12121. Configure option ........................................................................................................................................... 12221.1 Configure option Control Register ......................................................................................................... 12222. APPENDIX .................................................................................................................................................. 12322.1 Instruction Table .................................................................................................................................... 12322.2 Instructions on how to use the input port. .............................................................................................. 1266 July 17, 2012 Ver.1.7
MC95FB204List of FiguresFigure 1.1 OCD Debugger and Pin description .................................................................................... 12Figure 1.2 Single Programmer .............................................................................................................. 13Figure 1.3 Gang Programmer ............................................................................................................... 13Figure 2.1 MC95FB204 block diagram ................................................................................................ 14Figure 3.1 MC95FB204 20 SOP/TSSOP Pin assignment .................................................................... 15Figure 4.1 20 pin SOP package ............................................................................................................ 16Figure 4.2 20 pin TSSOP package ........................................................................................................ 17Figure 6.1 General Purpose I/O Port ..................................................................................................... 19Figure 6.2 External Interrupt I/O Port ................................................................................................... 20Figure 7.1 AC Timing ........................................................................................................................... 25Figure 8.1 Program memory ................................................................................................................. 29Figure 8.2 Data memory map ............................................................................................................... 30Figure 8.3 Lower 128 bytes RAM ........................................................................................................ 31Figure 9.1 Debounce Function .............................................................................................................. 46Figure 10.1 External Interrupt Description ........................................................................................... 48Figure 10.2 Block Diagram of Interrupt ............................................................................................... 49Figure 10.3 Interrupt Vector Address Table ......................................................................................... 51Figure 10.4 Interrupt flag result effective Timing ................................................................................ 52Figure 10.5 Interrupt Enable Register effective Timing ....................................................................... 52Figure 10.6 Execution of Multi Interrupt .............................................................................................. 53Figure 10.7 Interrupt Response Timing Diagram ................................................................................. 54Figure 10.8 Correspondence between vector Table address and the entry address of ISP ................... 54Figure 10.9 Saving/Restore Process Diagram & Sample Source .......................................................... 55Figure 10.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction .......................... 55Figure 11.1 CC/CV charging process ................................................................................................... 61Figure 11.2 CC/CV application block diagram .................................................................................... 62Figure 12.1 Clock Generator Block Diagram ....................................................................................... 65Figure 13.1 BIT Block Diagram ........................................................................................................... 68Figure 14.1 WDT Block Diagram ........................................................................................................ 70Figure 14.2 WDT Interrupt Timing Waveform .................................................................................... 72Figure 15.1 8 Bit Timer/Event Counter0, 1 Block Diagram ................................................................. 74Figure 15.2 Timer/Event Counter0, 1 Example .................................................................................... 75Figure 15.3 Operation Example of Timer/Event Counter0, 1 ............................................................... 75Figure 15.4 16 Bit Timer/Event Counter0, 1 Block Diagram ............................................................... 76Figure 15.5 8-bit Capture Mode for Timer0, 1 ..................................................................................... 77Figure 15.6 Input Capture Mode Operation of Timer 0, 1 .................................................................... 78Figure 15.7 Express Timer Overflow in Capture Mode ....................................................................... 78Figure 15.8 16-bit Capture Mode of Timer 0, 1 .................................................................................... 79Figure 15.9 PWM Mode ....................................................................................................................... 80Figure 15.10 Example of PWM at 4MHz ............................................................................................. 80July 17, 2012 Ver.1.7 7
Page 1 and 2: ABOV SEMICONDUCTOR Co., Ltd.8-BIT M
Page 3 and 4: MC95FB204VERSION 0.2 Preliminary (S
Page 5: MC95FB20410.5 Interrupt Sequence ..
Page 9 and 10: MC95FB204List of TablesTable 1-1 Or
Page 11 and 12: MC95FB2041.3 Ordering InformationTa
Page 13 and 14: MC95FB204Figure 1.2 Single Programm
Page 15 and 16: MC95FB204MC95FB2043. Pin Assignment
Page 17 and 18: MC95FB204Figure 4.2 20 pin TSSOP pa
Page 19 and 20: MC95FB2046. Port Structures6.1 Gene
Page 21 and 22: MC95FB2047. Electrical Characterist
Page 23 and 24: MC95FB204Note) -STOP1: WDT running
Page 25 and 26: MC95FB2047.9 AC CharacteristicsTabl
Page 27 and 28: MC95FB2047.11 Typical Characteristi
Page 29 and 30: MC95FB204FFFFH0FFFH4KBytes0000HFigu
Page 31 and 32: MC95FB2047FH7F776F7E766E7D756D7C 7B
Page 33 and 34: MC95FB204July 17, 2012 Ver.1.7 33
Page 35 and 36: MC95FB204Address Function Symbol R/
Page 37 and 38: MC95FB204Address Function Symbol R/
Page 39 and 40: MC95FB204ACF0Auxiliary Carry FlagGe
Page 41 and 42: MC95FB2049.2.6 Register MapTable 9-
Page 43 and 44: MC95FB2049.4 P1 Port9.4.1 P1 Port D
Page 45 and 46: MC95FB2049.5 P2 Port9.5.1 P2 Port D
Page 47 and 48: MC95FB20410. Interrupt Controller10
Page 49 and 50: MC95FB20410.3 Block DiagramIEDS0IE[
Page 51 and 52: MC95FB2041IE.EA Flag 1IEx.y 123Pr
Page 53 and 54: MC95FB20410.7 Multi InterruptIf two
Page 55 and 56: MC95FB20410.10 Saving/Restore Gener
Page 57 and 58:
MC95FB204IE2 AAH R/W 00H Interrupt
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MC95FB204R R R/W R/W R/W R/W R/W R/
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MC95FB20411. CC/CV BlockCC/CV means
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MC95FB204When the current of R SENS
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MC95FB20412. Clock Generator12.1 Ov
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MC95FB204Note) by CBYS bit, reflect
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MC95FB20413.4 Bit Interval Timer Re
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MC95FB204WDTMR 8D R/W 00H Watch Dog
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MC95FB20415. Timer/PWM15.1 Overview
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MC95FB204Match with T0DR/T1DRT0DR/T
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MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
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MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
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MC95FB204T1CR[1:0] = 10 H(2us)PWM1H
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MC95FB204T0 (Timer 0 Register: Read
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MC95FB204Initial value : 00HCDR1[7:
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MC95FB20416.2 Block Diagram÷2fxPre
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MC95FB204SET ADCM2Select ADC Clock
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MC95FB204ADDM11 ADDM10 ADDM9 ADDM8
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MC95FB20417. Power Down Operation17
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MC95FB20417.4 STOP modeThe power co
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MC95FB20417.5.1 Register MapTable 1
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MC95FB20418.4 RESET Noise Canceller
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MC95FB204:VDD Input:Internal OSCRes
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MC95FB20419. On-chip Debug System19
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MC95FB204Figure 19.2 10-bit transmi
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MC95FB204Acknowledge bittransmissio
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MC95FB20420.2.2 Register descriptio
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MC95FB2047 6 5 4 3 2 1 0ARL7 ARL6 A
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MC95FB20420.3 Memory map20.3.1 Flas
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MC95FB204Master ResetPage Buffer Re
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Step 5. Set erase mode. FMR:1001_00
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MC95FB20420.4.2 Summary of Flash Pr
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MC95FB20420.6 SecurityMC95FB204 pro
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MC95FB20422. APPENDIX22.1 Instructi
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MC95FB204SETB C Set carry 1 1 D3SET
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MC95FB20422.2.3 Preventative measur
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MC95FB204 - abov.co.kr

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