MC95FB204 - abov.co.kr

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MC95FB204P2DB (P2 Debounce Enable Register) : D8H7 6 5 4 3 2 1 0- - - - - P22DB P21DB P20DB- - - - - R/W R/W R/WInitial value : 00HP2DB[2:0]Configure debounce of P2 port0 disable1 disableExternal PortPin SignalMin. 5 clock countingClockPort DataFigure 9.1 Debounce Function46 July 17, 2012 Ver.1.7
MC95FB20410. Interrupt Controller10.1 OverviewThe MC95FB204 supports up to 25 interrupt sources. The interrupts have separate enable registerbits associated with them, allowing software control. They can also have four levels of priorityassigned to them. The non-maskable interrupt source is always enabled with a higher priority thanany other interrupt source, and is not controllable by software. The interrupt controller has followingfeatures:- receive the request from 24 interrupt source- 6 group priority- 4 priority levels- Multi Interrupt possibility- If the requests of different priority levels are received simultaneously, the request of higherpriority level is serviced- Each interrupt source can control by EA bit and each IEx bit- Interrupt latency: 3~9 machine cycles in single interrupt systemThe non-maskable interrupt is always enabled. The maskable interrupts are enabled through fourpair of interrupt enable registers (IE, IE1, IE2, IE3). Bits of IE, IE1, IE2, IE3 register each individuallyenable/disable a particular interrupt source. Overall control is provided by bit 7 of IE (EA). When EA isset to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled ordisabled through the other bits of the interrupt enable registers. The MC95FB204 supports a fourlevelpriority scheme. Each maskable interrupt is individually assigned to one of four priority levels bywriting to IP or IP1.Interrupt default mode is level-trigger basically but if needed, it is able to change edge-trigger mode.Table 10-1 shows the Interrupt Group Priority Level that is available for sharing interrupt priority.Priority sets two bit which is to IP and IP1 register about group. Interrupt service routine serviceshigher priority. If two requests of different priority levels are received simultaneously, the request ofhigher priority level is serviced. If the request of same or lower priority level is received, that request isnot serviced.InterruptGroupTable 10-1 Interrupt Group Priority Level0 (Bit0) Interrupt0 Interrupt6 Interrupt12 Interrupt18 Highest1 (Bit1) Interrupt1 Interrupt7 Interrupt13 Interrupt192 (Bit2) Interrupt2 Interrupt8 Interrupt14 Interrupt203 (Bit3) Interrupt3 Interrupt9 Interrupt15 Interrupt214 (Bit4) Interrupt4 Interrupt10 Interrupt16 Interrupt225 (Bit5) Interrupt5 Interrupt11 Interrupt17 Interrupt23 LowestJuly 17, 2012 Ver.1.7 47
Page 1 and 2: ABOV SEMICONDUCTOR Co., Ltd.8-BIT M
Page 3 and 4: MC95FB204VERSION 0.2 Preliminary (S
Page 5 and 6: MC95FB20410.5 Interrupt Sequence ..
Page 7 and 8: MC95FB204List of FiguresFigure 1.1
Page 9 and 10: MC95FB204List of TablesTable 1-1 Or
Page 11 and 12: MC95FB2041.3 Ordering InformationTa
Page 13 and 14: MC95FB204Figure 1.2 Single Programm
Page 15 and 16: MC95FB204MC95FB2043. Pin Assignment
Page 17 and 18: MC95FB204Figure 4.2 20 pin TSSOP pa
Page 19 and 20: MC95FB2046. Port Structures6.1 Gene
Page 21 and 22: MC95FB2047. Electrical Characterist
Page 23 and 24: MC95FB204Note) -STOP1: WDT running
Page 25 and 26: MC95FB2047.9 AC CharacteristicsTabl
Page 27 and 28: MC95FB2047.11 Typical Characteristi
Page 29 and 30: MC95FB204FFFFH0FFFH4KBytes0000HFigu
Page 31 and 32: MC95FB2047FH7F776F7E766E7D756D7C 7B
Page 33 and 34: MC95FB204July 17, 2012 Ver.1.7 33
Page 35 and 36: MC95FB204Address Function Symbol R/
Page 37 and 38: MC95FB204Address Function Symbol R/
Page 39 and 40: MC95FB204ACF0Auxiliary Carry FlagGe
Page 41 and 42: MC95FB2049.2.6 Register MapTable 9-
Page 43 and 44: MC95FB2049.4 P1 Port9.4.1 P1 Port D
Page 45: MC95FB2049.5 P2 Port9.5.1 P2 Port D
Page 49 and 50: MC95FB20410.3 Block DiagramIEDS0IE[
Page 51 and 52: MC95FB2041IE.EA Flag 1IEx.y 123Pr
Page 53 and 54: MC95FB20410.7 Multi InterruptIf two
Page 55 and 56: MC95FB20410.10 Saving/Restore Gener
Page 57 and 58: MC95FB204IE2 AAH R/W 00H Interrupt
Page 59 and 60: MC95FB204R R R/W R/W R/W R/W R/W R/
Page 61 and 62: MC95FB20411. CC/CV BlockCC/CV means
Page 63 and 64: MC95FB204When the current of R SENS
Page 65 and 66: MC95FB20412. Clock Generator12.1 Ov
Page 67 and 68: MC95FB204Note) by CBYS bit, reflect
Page 69 and 70: MC95FB20413.4 Bit Interval Timer Re
Page 71 and 72: MC95FB204WDTMR 8D R/W 00H Watch Dog
Page 73 and 74: MC95FB20415. Timer/PWM15.1 Overview
Page 75 and 76: MC95FB204Match with T0DR/T1DRT0DR/T
Page 77 and 78: MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
Page 79 and 80: MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
Page 81 and 82: MC95FB204T1CR[1:0] = 10 H(2us)PWM1H
Page 83 and 84: MC95FB204T0 (Timer 0 Register: Read
Page 85 and 86: MC95FB204Initial value : 00HCDR1[7:
Page 87 and 88: MC95FB20416.2 Block Diagram÷2fxPre
Page 89 and 90: MC95FB204SET ADCM2Select ADC Clock
Page 91 and 92: MC95FB204ADDM11 ADDM10 ADDM9 ADDM8
Page 93 and 94: MC95FB20417. Power Down Operation17
Page 95 and 96: MC95FB20417.4 STOP modeThe power co
Page 97 and 98:
MC95FB20417.5.1 Register MapTable 1
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MC95FB20418.4 RESET Noise Canceller
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MC95FB204:VDD Input:Internal OSCRes
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MC95FB20419. On-chip Debug System19
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MC95FB204Figure 19.2 10-bit transmi
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MC95FB204Acknowledge bittransmissio
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MC95FB20420.2.2 Register descriptio
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MC95FB2047 6 5 4 3 2 1 0ARL7 ARL6 A
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MC95FB20420.3 Memory map20.3.1 Flas
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MC95FB204Master ResetPage Buffer Re
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Step 5. Set erase mode. FMR:1001_00
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MC95FB20420.4.2 Summary of Flash Pr
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MC95FB20420.6 SecurityMC95FB204 pro
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MC95FB20422. APPENDIX22.1 Instructi
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MC95FB204SETB C Set carry 1 1 D3SET
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MC95FB20422.2.3 Preventative measur
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MC95FB204 - abov.co.kr

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