MC95FB204 - abov.co.kr

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MC95FB2042. Block DiagramP06/DSCLP07/DSDAP00/ OutCVSSP02/ IctrlP03/ VctrlCC/CVOn –ChipDebugP0PORTP07~P00AN2/P05/EC0AVREF/ .AN0/P10/ PWM1OP04/ T0TIMER&PWMM8051CORERAM(256B)P1PORTP2PORTP15~P10P22~P20P11/ INT0P12/ INT1INTERRUPCONTROLLERFLASH(4K byte)BITPWM1O/ .AVREF/ P10/AN0T0/ .REFOUT/ P04/AN1EC0/ P05/AN2(DSCL)/ P06/AN3(DSDA)/ P07/AN4INT0/ P11/AN5INT1/ P12/AN6P13/AN7P14/AN8P15/AN9P01/V SENSE12-BITADCPower onResetINT-RC OSC8MHzINT-WDT OSC1MHz(low quality)VoltageDownConvertorWDTCLOCK/SYSTEMCONXIN /P20XOUT /P21RESETB /P22VDDVSSFigure 2.1 MC95FB204 block diagram14 July 17, 2012 Ver.1.7
MC95FB204MC95FB2043. Pin AssignmentVDD120VSSP10 / PWM1O / AN0 / AVREF219P02 / IctrlP03 / Vctrl318CVSSP04 / T0O / REFOUT / AN1417P01 / VsenseP05 / EC0 / AN2516P00 / OutP06 / AN3 / (DSCL)615P22 / RESETBP07 / AN4 / (DSDA)714P21 / XOUTP11 / INT0 / AN5813P20 / XINP12 / INT1 / AN6912P15 / AN9P13 / AN710 11P14 / AN8Figure 3.1 MC95FB204 20 SOP/TSSOP Pin assignmentNOTE)- On On-Chip Debugging, ISP uses P0[6:7] pin as DSCL, DSDA.- Above functions are written in pin priority order. Most left side function has a lowest priority.For example, In pin 2, if P10, PWM1O, AN0 and AVREF are set, AVREF will be operated.July 17, 2012 Ver.1.7 15
Page 1 and 2: ABOV SEMICONDUCTOR Co., Ltd.8-BIT M
Page 3 and 4: MC95FB204VERSION 0.2 Preliminary (S
Page 5 and 6: MC95FB20410.5 Interrupt Sequence ..
Page 7 and 8: MC95FB204List of FiguresFigure 1.1
Page 9 and 10: MC95FB204List of TablesTable 1-1 Or
Page 11 and 12: MC95FB2041.3 Ordering InformationTa
Page 13: MC95FB204Figure 1.2 Single Programm
Page 17 and 18: MC95FB204Figure 4.2 20 pin TSSOP pa
Page 19 and 20: MC95FB2046. Port Structures6.1 Gene
Page 21 and 22: MC95FB2047. Electrical Characterist
Page 23 and 24: MC95FB204Note) -STOP1: WDT running
Page 25 and 26: MC95FB2047.9 AC CharacteristicsTabl
Page 27 and 28: MC95FB2047.11 Typical Characteristi
Page 29 and 30: MC95FB204FFFFH0FFFH4KBytes0000HFigu
Page 31 and 32: MC95FB2047FH7F776F7E766E7D756D7C 7B
Page 33 and 34: MC95FB204July 17, 2012 Ver.1.7 33
Page 35 and 36: MC95FB204Address Function Symbol R/
Page 37 and 38: MC95FB204Address Function Symbol R/
Page 39 and 40: MC95FB204ACF0Auxiliary Carry FlagGe
Page 41 and 42: MC95FB2049.2.6 Register MapTable 9-
Page 43 and 44: MC95FB2049.4 P1 Port9.4.1 P1 Port D
Page 45 and 46: MC95FB2049.5 P2 Port9.5.1 P2 Port D
Page 47 and 48: MC95FB20410. Interrupt Controller10
Page 49 and 50: MC95FB20410.3 Block DiagramIEDS0IE[
Page 51 and 52: MC95FB2041IE.EA Flag 1IEx.y 123Pr
Page 53 and 54: MC95FB20410.7 Multi InterruptIf two
Page 55 and 56: MC95FB20410.10 Saving/Restore Gener
Page 57 and 58: MC95FB204IE2 AAH R/W 00H Interrupt
Page 59 and 60: MC95FB204R R R/W R/W R/W R/W R/W R/
Page 61 and 62: MC95FB20411. CC/CV BlockCC/CV means
Page 63 and 64: MC95FB204When the current of R SENS
Page 65 and 66:
MC95FB20412. Clock Generator12.1 Ov
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MC95FB204Note) by CBYS bit, reflect
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MC95FB20413.4 Bit Interval Timer Re
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MC95FB204WDTMR 8D R/W 00H Watch Dog
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MC95FB20415. Timer/PWM15.1 Overview
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MC95FB204Match with T0DR/T1DRT0DR/T
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MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
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MC95FB204T0CRT0EN T0PE CAP0 T0CK2 T
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MC95FB204T1CR[1:0] = 10 H(2us)PWM1H
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MC95FB204T0 (Timer 0 Register: Read
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MC95FB204Initial value : 00HCDR1[7:
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MC95FB20416.2 Block Diagram÷2fxPre
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MC95FB204SET ADCM2Select ADC Clock
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MC95FB204ADDM11 ADDM10 ADDM9 ADDM8
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MC95FB20417. Power Down Operation17
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MC95FB20417.4 STOP modeThe power co
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MC95FB20417.5.1 Register MapTable 1
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MC95FB20418.4 RESET Noise Canceller
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MC95FB204:VDD Input:Internal OSCRes
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MC95FB20419. On-chip Debug System19
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MC95FB204Figure 19.2 10-bit transmi
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MC95FB204Acknowledge bittransmissio
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MC95FB20420.2.2 Register descriptio
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MC95FB2047 6 5 4 3 2 1 0ARL7 ARL6 A
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MC95FB20420.3 Memory map20.3.1 Flas
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MC95FB204Master ResetPage Buffer Re
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Step 5. Set erase mode. FMR:1001_00
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MC95FB20420.4.2 Summary of Flash Pr
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MC95FB20420.6 SecurityMC95FB204 pro
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MC95FB20422. APPENDIX22.1 Instructi
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MC95FB204SETB C Set carry 1 1 D3SET
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MC95FB20422.2.3 Preventative measur
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