邏輯分析儀的概念與原理 - Leaptronix

- - -- -

-oooo

-ooooo( Embedded )

ooooooo( Skew )

-Data InExternal CLKInternal CLKDisplayBufferASICCPUMemoryTrigger Level

- ( Timing )ooo

- ( Timing )o-LALALA

- ( Timing )o-DataLALA

- (State)oooSignalProbe

- (State)o(Hold Time)DCLK(Setup Time)

-oooo ( Event )- ( Level )- ( Examination )--

-oooPattern trigger : - Ch 1 Ch 2 Ch 11Ch 20

-oEdge trigger : ( )-Logic H or Logic L TTL Vt 1.5V.1.5V “H”; 1.5V ”L”

-o-Data InputClockDCLKQData OutputData InputClockD Q Data OutputCLK

-oData InputDQData OutputClockCLKData InputClockData Output

-ooo( Deeper memory )

-o-A: End of memory All pre-trigger-B: Center of memory ½ , ½-C: Beginning of memory All post-triggerPRE-Trigger data Trigger point Post-Trigger dataABC

-o-

- (Glitch )o

- (Skew )oCh 1Ch 2ProbeCh 1Ch 2Skew

- PC Base Standalone Pc Base Windows Standalone (Parallel Port.....)PC BasePC

- PC Base Standalone Pc BaseStandalone

- LA-1001673GTLA52011683ATiming200MHz200/500MHz(full/half channels)2GHz400/800MHz(full/half channels)State100MHz150MHz235MHz200MHzChannel32343434Memory64K~1M64K/128K(full/half channel)512K/1M(full/half channel)512K/1M(full/half channel)Built-in display5.7inch,320*240,ColorColor10.4inch,1024*768,Color12.1inch,ColorChannel-to-ChannelSkew2ns (typical)2ns (typical)900ps (typical)

-TimingStateClock BUS Clock Clock

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