Traffic Management for the Available Bit Rate (ABR) Service in ...

2. Some switch schemes have a processing requirement for both the forward and
backward going RM cell. This requires extra processing at the switch. Another
related problem which arises in this case is that the switch scheme requires
exchange of information from one port to another (the ingress chip to the egress
chip). The assumption made by the scheme is that the switch has a shared
memory which is used for tables facilitating the information exchange. This
assumption is based on the fact that early switches had the VC table (which
maps a cell of a VC from one port to another) was in such a shared memory.
The problem with the shared memory is that in the worst case it needs to
support accesses from all ports in a single cell time. Modern switches have
evolved to use cheaper (and slower memory) to build a distributed VC table {
based on the assumption that VC label allocations are relatively static (written
only during connection setup, read by the local port only), and local between
pairs of ports (except point-to-multipoint VCs which could involve multiple
ports). One disadvantage of the distributed memory implementation is that
sharing information between ports via memory is not possible. A solution to this
problem is to haveacheap low speed shared memory (DRAM) for storing shared
tables which are accessed when RM cells are processed. We take advantage of
the fact that RM cells on every VC arrive at a frequency of at most one in
Nrm = 32 cells. Even in the case when RM cells of multiple VCs arrive
together, they need to be processed at a rate much smaller than the link rate.
As mentioned before, RM cells can be staggered with respect to the data stream
as long as the sequence integrity on a VC is maintained.
368