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Traffic Management for the Available Bit Rate (ABR) Service in ...

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With an enhanced UBR service, applications like le transfer and WWW brows<strong>in</strong>g<br />

and download<strong>in</strong>g become viable over this service.<br />

The service categories of ATM can also be compared to those o ered by air-<br />

l<strong>in</strong>es [51]. CBR is con rmed reservations with no recourse if you do not show up.<br />

VBR is like con rmed reservation but you do not pay ifyou do not show up.<strong>ABR</strong> is<br />

standby. You get to go if seats are available. Hav<strong>in</strong>g standby service is good <strong>for</strong> <strong>the</strong><br />

airl<strong>in</strong>e. They can ll <strong>the</strong>ir seats that would o<strong>the</strong>rwise would have gone empty. The<br />

service is also good <strong>for</strong> passengers. They can travel cheaply particularly if <strong>the</strong>y don't<br />

have to be at <strong>the</strong>ir dest<strong>in</strong>ations at a certa<strong>in</strong> time. UBR service is not currently o ered<br />

by <strong>the</strong> airl<strong>in</strong>es. Passengers travell<strong>in</strong>g on UBR class may beallowed to board a plane<br />

but may be strangled at <strong>the</strong> subsequent airports <strong>for</strong>ever if seats are not available.<br />

<strong>ABR</strong> users would generally be asked to stay home as much as possible if <strong>the</strong>ir routes<br />

are congested.<br />

10.2 Issues <strong>in</strong> <strong>ABR</strong> Implementation Complexity<br />

From an architecture viewpo<strong>in</strong>t, currently, <strong>ABR</strong> is a complex service to implement.<br />

The importantarchitectural tradeo s we will encounter <strong>in</strong>volve requirements <strong>in</strong> terms<br />

of process<strong>in</strong>g speed, latency, memory, and compactness. We will encounter process<strong>in</strong>g<br />

speed mismatches <strong>for</strong> RM cells versus data cells. Fur<strong>the</strong>r, <strong>the</strong> RM cell might need to<br />

be processed <strong>in</strong> both <strong>the</strong> <strong>for</strong>ward and reverse directions. The latency issue arises when<br />

RM cells are processed separately, and/or <strong>in</strong> software, and/or block on a slow shared<br />

DRAM <strong>for</strong> <strong>in</strong><strong>for</strong>mation access. Memory requirements and access speed requirements<br />

vary depend<strong>in</strong>g upon <strong>the</strong> RM cell process<strong>in</strong>g strategy. Compactness and overall cost<br />

depends upon <strong>the</strong> particular implementation (<strong>for</strong> example: ASIC or FPGA). In this<br />

366

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