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8MbSMART 3 BOOT BLOCK FLASH MEMORYSELF-TIMED BLOCK ERASE SEQUENCE 1StartCOMPLETE BLOCK ERASESTATUS-CHECK SEQUENCEStart (ERASE completed)WRITE 20hSR3 = 0?NOVPPError5, 6YESVPP = 3.3V or 5VSR4, 5 = 1?YESCommand Sequence Error6WRITE D0h,Block AddressNOSR5 = 0?NOBLOCK ERASE Error6STATUS REGISTERREADERASEBusyYESERASE SuccessfulSR7 = 1?NONOSuspend ERASE?YESComplete Status2Check (optional)YESSuspend 4SequenceERASE Complete 3ERASE ResumedNOTE:1. Sequence may be repeated to erase additional blocks.2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register iscleared.3. To return to the array read mode, the FFh command must be issued.4. Refer to the ERASE SUSPEND flowchart for more information.5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITEor ERASE operations are allowed by the CEL.6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.8Mb Smart 3 Boot Block Flash MemoryQ10_3.p65 – Rev. 3, Pub. 10/0116Micron Technology, Inc., reserves the right to change products or specifications without notice.©2001, Micron Technology, Inc.
8MbSMART 3 BOOT BLOCK FLASH MEMORYERASE SUSPEND/RESUME SEQUENCEStart (ERASE in progress)WRITE B0h(ERASE SUSPEND)VPP = 3.3V or 5VSTATUS REGISTERREADSR7 = 1?NOYESSR6 = 1?NOYESWRITE FFh(READ ARRAY)ERASE CompletedDoneReading?NOYESWRITE D0h(ERASE RESUME)Resume ERASE8Mb Smart 3 Boot Block Flash MemoryQ10_3.p65 – Rev. 3, Pub. 10/0117Micron Technology, Inc., reserves the right to change products or specifications without notice.©2001, Micron Technology, Inc.
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