Si6913DQ Dual P-Channel 12 V (D-S) MOSFET - Vishay

Si6913DQVishay SiliconixDual P-Channel 12 V (D-S) MOSFETPRODUCT SUMMARYV DS (V) R DS(on) () I D (A)0.021 at V GS = - 4.5 V - 5.8- 120.028 at V GS = - 2.5 V - 5.00.037 at V GS = - 1.8 V - 4.4FEATURES• TrenchFET ® Power MOSFETs• Material categorization:For definitions of compliance please seewww.vishay.com/doc?99912APPLICATIONS• Load Switch• Battery SwitchTSSOP-8S 1S 2D 1 1S 1 2S 1 3G 1 48765D 2S 2S 2G 2G 1D 1G 2D 2Top ViewOrdering Information:Si6913DQ-T1-E3 (Lead (Pb)-free)Si6913DQ-T1-GE3 (Lead (Pb)-free and Halogen-free)P-Channel MOSFETP-Channel MOSFETABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)Parameter Symbol 10 s Steady State UnitDrain-Source Voltage V DS - 12VGate-Source Voltage V GS ± 8Continuous Drain Current (T J = 150 °C) a T A = 25 °C- 5.8 - 4.9I DT A = 70 °C - 4.6 - 3.9APulsed Drain Current (10 µs Pulse Width) I DM - 30Continuous Source Current (Diode Conduction) a I S - 1 - 0.7T A = 25 °CMaximum Power Dissipation a 1.14 0.83P D WT A = 70 °C 0.73 0.53Operating Junction and Storage Temperature Range T J , T stg - 55 to 150 °CTHERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient at 10 s86 110R thJASteady State 124 150°C/WMaximum Junction-to-Foot (Drain) Steady State R thJF 52 65Notes:a. Surface mounted on 1" x 1" FR4 board.Document Number: 72368S12-1359-Rev. C, 11-Jun-12For technical questions, contact: pmostechsupport@vishay.comwww.vishay.com1This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si6913DQVishay SiliconixDrain-Source On-State Resistance a R DS(on)SPECIFICATIONS (T J = 25 °C, unless otherwise noted)Parameter Symbol Test Conditions Min. Typ. Max. UnitStaticGate Threshold Voltage V GS(th) V DS = V GS , I D = - 400 µA - 0.4 - 0.9 VGate-Body Leakage I GSS V DS = 0 V, V GS = ± 8 V ± 100 nAV DS = - 12 V, V GS = 0 V - 1Zero Gate Voltage Drain Current I DSSV DS = - 12 V, V GS = 0 V, T J = 70 °C - 25µAOn-State Drain Current a I D(on) V DS - 5 V, V GS = - 4.5 V - 20 AV GS = - 2.5 V, I D = - 5 A 0.021 0.028 V GS - 4.5 V, I D = - 5.8 A 0.016 0.021V GS = - 1.8 V, I D = - 4.4 A 0.029 0.037Forward Transconductance a g fs V DS = - 5 V, I D = - 5.8 A 25 SDiode Forward Voltage a V SD I S = - 1 A, V GS = 0 V - 0.61 - 1.1 VDynamic bTotal Gate ChargeQ g18.5 28Gate-Source Charge Q gs V DS = - 6 V, V GS = - 4.5 V, I D = - 5.8 A2.7nCGate-Drain Charge Q gd 5Gate Resistance R g f = 1 MHz 4.6 Turn-On Delay Timet d(on)45 70Rise Time t r V DD = - 6 V, R L = 6 80 120Turn-Off Delay Time t d(off) I D - 1 A, V GEN = - 4.5 V, R G = 6 130 200 nsFall Time t f 80 120Source-Drain Reverse Recovery Time t rr I F = - 1 A, dI/dt = 100 A/µs 65 100Notes:a. Pulse test; pulse width 300 µs, duty cycle 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)30V GS = 5 thru 2.5 V2 V30T C = - 55 °C242425 °C- Drain Current (A)I D181261.5 V- Drain Current (A)I D18126125 °C00 1 2 3 4 5V DS - Drain-to-Source Voltage (V)Output Characteristics00.0 0.5 1.0 1.5 2.0 2.5V GS - Gate-to-Source Voltage (V)Transfer CharacteristicsDocument Number: 72368S12-1359-Rev. C, 11-Jun-12For technical questions, contact: pmostechsupport@vishay.comwww.vishay.com2This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si6913DQVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)0.103500R DS(on) - On-Resistance ()0.080.060.040.02V GS = 1.8 VV GS = 2.5 VV GS = 4.5 VC - Capacitance (pF)30002500200015001000500C rssC ossC iss0.000 5 10 15 20 25 30I D - Drain Current (A)On-Resistance vs. Drain Current00 2 4 6 8 10 12V DS - Drain-to-Source Voltage (V)Capacitance61.6- Gate-to-Source Voltage (V)5432V DS = 6 VI D = 5.8 A- On-Resistance (Normalized)1.41.21.0V GS = 4.5 VI D = 5.8 AV GS1R DS(on)0.800 5 10 15 20 25 30Q g - Total Gate Charge (nC)Gate Charge0.6- 50 - 25 0 25 50 75 100 125 150T J - Junction Temperature (°C)On-Resistance vs. Junction Temperature300.08- Source Current (A)I S101T J = 150 °CT J = 25 °CR DS(on) - On-Resistance ()0.070.060.050.040.030.02I D = 5.8 A0.010.10.0 0.3 0.6 0.9 1.2 1.5V SD - Source-to-Drain Voltage (V)Source-Drain Diode Forward Voltage0.000 1 2 3 4 5 6 7 8V GS - Gate-to-Source Voltage (V)On-Resistance vs. Gate-to-Source VoltageDocument Number: 72368S12-1359-Rev. C, 11-Jun-12For technical questions, contact: pmostechsupport@vishay.comwww.vishay.com3This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si6913DQVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)0.41000.380Variance (V)V GS(th)0.20.10.0I D = 400 µAPower (W)6040- 0.120- 0.2- 50 - 25 0 25 50 75 100 125 150T J - Temperature (°C)Threshold Voltage00.001 0.01 0.1 110Time (s)Single Pulse Power, Junction-to-Ambient100Limited by R * DS(on)- Drain Current (A)I D1010.1T C = 25 °CSingle Pulse1 ms10 ms100 ms1 s10 sDC0.010.1 1 10 100V DS - Drain-to-Source Voltage (V)*V GS > minimum V GS at which R DS(on) is specifiedSafe Operating Area, Junction-to-Case2Normalized Effective TransientThermal Impedance10.1Duty Cycle = 0.50.20.10.050.023. T JM - T A = P DM Z (t) thJASingle Pulse4. Surface Mounted0.0110 -4 10 -3 10 -2 10 -11 10 100600Square Wave Pulse Duration (s)Notes:P DMNormalized Thermal Transient Impedance, Junction-to-Ambientt 1t 2 t 11. Duty Cycle, D =t 22. Per Unit Base = R thJA = 124 °C/WDocument Number: 72368S12-1359-Rev. C, 11-Jun-12For technical questions, contact: pmostechsupport@vishay.comwww.vishay.com4This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si6913DQVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)2Normalized Effective TransientThermal Impedance10.1Duty Cycle = 0.50.20.10.050.02Single Pulse0.0110 -410 -3 10 -2 1 10Square Wave Pulse Duration (s)Normalized Thermal Transient Impedance, Junction-to-Foot10 -1Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?72368.Document Number: 72368S12-1359-Rev. C, 11-Jun-12For technical questions, contact: pmostechsupport@vishay.comwww.vishay.com5This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package InformationVishay SiliconixJEDEC Part Number: MO-153R 0.10Corners)AA2A1BDeE1CR 0.10(4 Corners)ELL10.25 (Gage Plane)K1Dim Min Nom MaxA – – 1.20A 1 0.05 0.10 0.15A 2 0.80 1.00 1.05B 0.19 0.28 0.30C – 0.127 –D 2.90 3.00 3.10E 6.20 6.40 6.60E 1 4.30 4.40 4.50e – 0.65 –L 0.45 0.60 0.75L 1 0.90 1.00 1.10Y – – 0.10K1 0 3 6ECN: S-03946—Rev. G, 09-Jul-01DWG: 5844Document Number: 7120106-Jul-01www.vishay.com1

LITTLE FOOT TSSOP-8The Next Step in Surface-Mount Power MOSFETsAN1001Vishay SiliconixWharton McDaniel and David OldhamWhen Vishay Siliconix introduced its LITTLE FOOTMOSFETs, it was the first time that power MOSFETs had beenoffered in a true surface-mount package, the SOIC. LITTLEFOOT immediately found a home in new small form factor diskdrives, computers, and cellular phones.The new LITTLE FOOT TSSOP-8 power MOSFETs are thenatural evolutionary response to the continuing demands ofmany markets for smaller and smaller packages. LITTLEFOOT TSSOP-8 MOSFETs have a smaller footprint and alower profile than LITTLE FOOT SOICs, while maintaining lowr DS(on) and high thermal performance. Vishay Siliconix hasaccomplished this by putting one or two high-density MOSFETdie in a standard 8-pin TSSOP package mounted on a customleadframe.THE TSSOP-8 PACKAGEThis is the low profile demanded by applications such asPCMCIA cards.It reduces the power package to the same height as manyresistors and capacitors in 0805 and 0605 sizes. It also allowsplacement on the “passive” side of the PC board.The standard pinouts of the LITTLE FOOT TSSOP-8packages have been changed from the standard establishedby LITTLE FOOT. This change minimizes the contribution ofinterconnection resistance to r DS(on) and maximizes thetransfer of heat out of the package.Figure 2 shows the pinouts for a single-die TSSOP. Notice thatboth sides of the package have Source and Drainconnections, whereas LITTLE FOOT has the Source and Gateconnections on one side of the package, and the Drainconnections are on the opposite side.LITTLE FOOT TSSOP-8 power MOSFETs requireapproximately half the PC board area of an equivalent LITTLEFOOT device (Figure 1). In addition to the reduction in boardarea, the package height has been reduced to 1.1 mm.DrainSourceSourceGateDrainSourceSourceDrainFigure 2.Pinouts for Single Die TSSOPTop ViewFigure 3 shows the standard pinouts for a dual-die TSSOP-8.In this case, the connections for each individual MOSFEToccupy one side.Side ViewDrain 1Source 1Source 1Gate 1Drain 2Source 2Source 2Gate 2Figure 1.An TSSOP-8 Package Next to a SOIC-8 Packagewith Views from Both Top and SideFigure 3.Pinouts for Dual-Die TSSOPDocument Number: 7057112-Dec-03www.vishay.com1

AN1001Vishay SiliconixBecause the TSSOP has a fine pitch foot print, the pad layoutis somewhat more demanding than the layout of the SOIC.Careful attention must be paid to silkscreen-to-pad andsoldermask-to-pad clearances. Also, fiduciary marks may berequired. The design and spacing of the pads must be dealtwith carefully. The pads must be sized to hold enough solderpaste to form a good joint, but should not be so large or soplaced as to extend under the body, increasing the potential forsolder bridging. The pad pattern should allow for typical pickand place errors of 0.25 mm. See Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs,(http://www.vishay.com/doc?72286), for the recommendedpad pattern for PC board layout.THERMAL ISSUESLITTLE FOOT TSSOP MOSFETs have been given thermalratings using the same methods used for LITTLE FOOT. Themaximum thermal resistance junction-to-ambient is 83C/Wfor the single die and 125C/W for dual-die parts. TSSOP relieson a leadframe similar to LITTLE FOOT to remove heat fromthe package. The single- and dual-die leadframes are shownin Figure 4.Figure 5.The actual test is based on dissipating a known amount ofpower in the device for a known period of time so the junctiontemperature is raised to 150C. The starting and endingjunction temperatures are determined by measuring theforward drop of the body diode. The thermal resistance for thatpulse width is defined by the temperature rise of the junctionabove ambient and the power of the pulse, Tja/P.Figure 6 shows the single pulse power curve of the Si6436DQlaid over the curve of the Si9936DY to give a comparison of thethermal performance. The die in the two devices haveequivalent die areas, making this a comparison of thepackaging. This comparison shows that the TSSOP packageperforms as well as the SOIC out to 150 ms, with long-termperformance being 0.5 W less. Although the thermalperformance is less, LITTLE FOOT TSSOP will operate in alarge percentage of applications that are currently beingserved by LITTLE FOOT.14.012.010.0a) 8-Pin Single-Pad TSSOPPower (W)8.06.04.0Si99362.0Si6436www.vishay.com2b) 8-Pin Dual-Pad TSSOPFigure 4.LeadframeThe MOSFETs are characterized using a single pulse powertest. For this test the device mounted on a one-square-inchpiece of copper clad FR-4 PC board, such as those shown inFigure 5. The single pulse power test determines themaximum amount of power the part can handle for a givenpulse width and defines the thermal resistancejunction-to-ambient. The test is run for pulse widths rangingfrom approximately 10 ms to 100 seconds. The thermalresistance at 30 seconds is the rated thermal resistance for thepart. This rating was chosen to allow comparison of packagesand leadframes. At longer pulse widths, the PC board thermalcharateristics become dominant, making all parts look thesame.0.00.1 1 10 100Time (Sec.)Figure 6. Comparison of Thermal PerformanceCONCLUSIONTSSOP power MOSFETs provide a significant reduction in PCboard footprint and package height, allowing reduction inboard size and application where SOICs will not fit. This isaccomplished using a standard IC package and a customleadframe, combining small size with good power handlingcapability.For the TSSOP-8 package outline visit:http://www.vishay.com/doc?71201For the SOIC-8 package outline visit:http://www.vishay.com/doc?71192Document Number: 7057112-Dec-03

AN806Vishay SiliconixMounting LITTLE FOOT TSSOP-8 Power MOSFETsWharton McDanielSurface-mounted LITTLE FOOT power MOSFETs use integratedcircuit and small-signal packages which have been been modifiedto provide the heat transfer capabilities required by power devices.Leadframe materials and design, molding compounds, and dieattach materials have been changed, while the footprint of thepackages remains the same.See Application Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay SiliconixMOSFET, (http://www.vishay.com/doc?72286), for the basisof the pad design for a LITTLE FOOT TSSOP-8 power MOSFETpackage footprint. In converting the footprint to the pad set for apower device, designers must make two connections: an electricalconnection and a thermal connection, to draw heat away from thepackage.In the case of the TSSOP-8 package, the thermal connectionsare very simple. Pins 1, 5, and 8 are the drain of the MOSFETfor a single MOSFET package and are connected together. Inthe dual package, pins 1 and 8 are the two drains. For asmall-signal device or integrated circuit, typical connectionswould be made with traces that are 0.020 inches wide. Sincethe drain pins also provide the thermal connection to thepackage, this level of connection is inadequate. The totalcross section of the copper may be adequate to carry thecurrent required for the application, but it presents a largethermal impedance. Also, heat spreads in a circular fashionfrom the heat source. In this case the drain pins are the heatsources when looking at heat spread on the PC board.The pad patterns with copper spreading for the single-MOSFETTSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2)show the starting point for utilizing the board area available for theheat-spreading copper. To create this pattern, a plane of copperoverlies the drain pins. The copper plane connects the drain pinselectrically, but more importantly provides planar copper to drawheat from the drain leads and start the process of spreading theheat so it can be dissipated into the ambient air. These patternsuse all the available area underneath the body for this purpose.0.0320.80.0180.450.0731.780.0911.650.2847.60.0260.660.1223.1FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern withCopper SpreadingSince surface-mounted packages are small, and reflow solderingis the most common way in which these are affixed to the PCboard, “thermal” connections from the planar copper to the padshave not been used. Even if additional planar copper area is used,there should be no problems in the soldering process. The actualsolder connections are defined by the solder mask openings. Bycombining the basic footprint with the copper plane on the drainpins, the solder mask generation occurs automatically.0.0320.80.0180.450.2847.60.0260.660.1223.1A final item to keep in mind is the width of the power traces. Theabsolute minimum power trace width must be determined by theamount of current it has to carry. For thermal reasons, thisminimum width should be at least 0.020 inches. The use of widetraces connected to the drain plane provides a low impedancepath for heat to move away from the device.0.0731.780.1183.54FIGURE 1. Single MOSFET TSSOP-8 PadPattern with Copper SpreadingDocument Number: 7073817-Dec-03www.vishay.com1

Application Note 826Vishay SiliconixRECOMMENDED MINIMUM PADS FOR TSSOP-80.092(2.337)0.026(0.660)0.040(1.016)0.262(6.655)0.182(4.623)0.014(0.356)0.012(0.305)Recommended Minimum PadsDimensions in Inches/(mm)Return to IndexReturn to IndexAPPLICATION NOTEDocument Number: 72611www.vishay.comRevision: 21-Jan-08 27

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