Sdc-19204 10-, 12-, 14-, Or 16-Bit Industrial Synchro-To-Digital

+ V MAXS1-S3 = V SINθMAXcounter is an incremental integrator. Therefore, there are twostages of integration, making the converter a Type II trackingTABLE 1. SDC-19204/6 SPECIFICATIONS (CONTINUED)PARAMETER VALUE DESCRIPTIONPOWER SUPPLY CHARACTERISTICSNominal Voltage and Range+15 VDC ±5%+5 VDC ±10% -15 VDC ±5% Note: When analog outputsMax Voltage w/o Damage+18 V+8 V-18 V are not required groundMax Current25 mA10 mA15 mA -15 V (pin 36).TEMPERATURE RANGESOperating0° C to +70° CStorage-40° C to +120° CPHYSICAL CHARACTERISTICSSize1.14 x 2.02 x 0.23 inches40-pin TDIP(28.96 x 51.3 x 5.84 mm)Weight0.46 oz(13gm)INTRODUCTIONThe SDC-19204/6 Series are small, 40-pin TDIP synchro-to-digitalCONVERTER OPERATIONAs shown in FIGURE 1, the converter section of the SDC-hybrid converters. As shown in the block diagram (FIGURE 19204/6 contains a high accuracy control transformer, demodu-1), the SDC-19204/6 can be broken down into five functional lator, error processor, voltage-controlled oscillator (VCO),parts:up/down counter, zero-set timing, and reference conditioner. Theconverter produces a digital angle φ which tracks the analog1. Signal Input Option2. Converterinput angle θ to within the specified accuracy of the converter.3. Analog Conditioner4. Power Supply ConditionerThe control transformer performs the following trigonometric5. Digital Interface.computation:sin(θ - φ) = sinθcosφ - cosθsinφWhere :SIGNAL INPUTθ is angle theta, representing the resolver shaft position.φ is digital angle phi, contained in the up/down counter.In a synchro, shaft angle data is transmitted as the ratio of carrieramplitudes across the input terminals. Synchro signals, which The tracking process consists of continually adjusting φ to makeare of the form sinθcosωt, sin(θ+120°)cosωt and (θ - φ) → 0, so that φ will repeat the shaft position θ. The outputsin(θ+240°)cosωt are internally converted to resolver format;of the demodulator is an analog DC level proportional to sin(θ -sinθcosωt and cosθcosωt. FIGURE 2 illustrates synchro signalsφ). The error processor receives its input from the demodulatoras a function of the angle θ.and integrates this sin(θ - φ) error signal, which then drives theVCO. The VCO’s clock pulses are accumulated by the up/downcounter. The velocity voltage accuracy, linearity and offset aredetermined by the quality of the VCO. Functionally, the up/downservo.In Phase withREF of Converterand R2-R1 of CX.- V MAX030 90 150 210 270 330S2-S1 = V SIN(θ + 240°)MAX360S3-S2 = V SIN(θ + 120°)MAXθ (DEGREES)CCWStandard Synchro Control Transmitter (CX) Outputs as aFunction of CCW Rotation From Electrical Zero (EZ).FIGURE 2. SYNCHRO SIGNALSIn a Type II servo, the VCO always settles to a counting ratewhich makes dφ/dt equal to dθ/dt without lag. The output data willalways be fresh and available as long as the maximum trackingrate of the converter is not exceeded.The reference conditioner is a comparator that produces thesquare wave reference voltage which drives the demodulator. Itis single-ended ground based with an input Z of 100k ohms min,110k ohms nominal, resistive.MINIMIZING ERROR DUE TO QUADRATURE. In those applicationswhere highest accuracy is needed, the reference (REF)input can be phase-shifted by adding a capacitor in series withthe REF input (pin 40) to add a phase lead equal to the nominalphase lead of the synchro input. To determine the capacitor’svalue, see FIGURE 3.3

SDC-19204/6sensitivity can be increased with an external resistor. Refer toVELOCITY PROGRAMMING section for more information.REFC40100k10kVaPOWER SUPPLY CONDITIONERThe power supply conditioner lowers the internal power supplyvoltage to the custom CMOS chip to +11 V from the +15 V supply.The +11 V will track the +15 V. Internal analog ground is onehalf of +11 V or +5.5 V, nom.Note: Choose C such that the V a -to-REF phase lead is equal to thesynchro-to-REF phase lead plus 9 µs.QUADRATURE VOLTAGES. In a synchro, quadrature voltagesare, by definition, the resulting 90° fundamental signal in thenulled out error voltage (e) in the converter. A digital positionerror will result due to the interaction of this quadrature voltageand a reference phase shift between the converter signal andreference inputs. The magnitude of this error is given by the followingformula:Magnitude of Error = (Quadrature Voltage/F.S. signal) • tan(α)Where:Magnitude of Error is in radians.Quadrature Voltage is in volts.Full-Scale signal is in volts.α = signal to REF phase shift.An example of the magnitude of error is as follows:Let: Quadrature Voltage = 11.8 mVLet: F.S. signal = 11.8 VLet: a = 6°Then: Magnitude of Error = 0.35 min ≈ 1 LSBin the 16th bit.Note: Quadrature is composed of static quadrature which isspecified by the resolver supplier plus the speed voltage which isdetermined by the following formula:Speed Voltage = (rotational speed/carrier freq) • F.S. signalWhere :FIGURE 3. PHASE SHIFTING THE REF INPUTSpeed Voltage is the quadrature due to rotation.Rotational speed is the RPS (rotations per second)of the synchro.Carrier frequency is the REF in Hz.ANALOG CONDITIONERThe Analog Conditioner section performs three functions. It convertsanalog ground from 5.5 V to 0 V, provides a gain of 2 for ACError (e) and a gain of 2.2 for Velocity (VEL). The velocity scalingVINTERNAL DC REFERENCE VOLTAGE (V). This internal voltageis not required externally for normal operation of the converter.It is used as the internal DC reference common with thedirect input option. It is nominally +5.5 V and is proportional tothe +15 VDC supply.DIGITAL INTERFACEThe digital interface circuitry performs three main functions:1. Latches the output bits during an Inhibit (INH) command,allowing stable data to be read.2. Furnishes parallel tri-state data formats.3. Acts as a buffer between the internal CMOS logic and theexternal TTL logic.By applying an Inhibit (INH) command to the SDC-19204/6 thedata will lock in the output transparent latch without interferingwith the continuous tracking of the converter’s feedback loop.Therefore, the digital angle φ is always updated, and the INH canbe applied for an arbitrary amount of time. The InhibitTransparent Latch and the 50 ns delay are part of the inhibit circuitry.For further information, see the INHIBIT (INH, pin 9) paragraph.The BIT detect circuitry monitors the error level (D) fromthe demodulator and the LOS (loss of signal) detector detectsdisconnected resolver inputs.LOGIC INPUT/OUTPUTThe digital angle outputs are buffered and provided in a two-byteformat. The first byte contains the MSBs (bits 1-8) and is enabledby placing EM (pin 10) to a logic 0. Depending on the user programmedresolution, the second byte contains the LSBs and isenabled by placing EL (pin 11) to a logic 0. The second byte willcontain either bits 9-10 (10-bit resolution), bits 9-12 (12-bit resolution),bits 9-14 (14-bit resolution) or bits 9-16 (16-bit resolution).All unused LSBs will be at logic 0. TABLE 2 lists the angularweight for the digital angle outputs.The digital angle outputs are valid 150 ns after EM or EL is activatedwith a logic 0, and are high impedance within 100 ns, max,after EL and EM are set to logic 1. Both enables are internallypulled up to +5 V by -10 µA max current sources.DIGITAL ANGLE OUTPUT TIMINGThe digital angle output is 10, 12, 14, or 16 parallel data bits. Alllogic outputs are short-circuit proof to ground and +5 V. The CB(Converter Busy) output is a positive, 0.4 to 0.7 µs pulse.4

The digital output data changes approximately 50 ns after theleading edge of the CB pulse because of an internal delay(shown in FIGURE 1). Data is valid 0.2 µs after the leading edgeof CB (see FIGURE 4). The angle is determined by the sum ofthe bits at logic 1.CBTABLE 2 DIGITAL ANGLE OUTPUTSBIT DEG/BIT MIN/BIT1 (MSB ALL MODES)2345678910 (LSB 10-BIT MODE)1112 (LSB 12-BIT MODE)1314 (LSB 14-BIT MODE)1516 (LSB 16-BIT MODE)180904522.511.255.6252.8131.4050.70310.35160.17580.08790.04390.02200.01100.0055Note: EM enables the 8 MSBs and EL enables the LSBs.6.1 µs MINDEPENDS UPON dφ/dt10800540027001350675387.5168.584.3842.1921.0910.555.272.641.320.660.330.4-0.7µsAn INH input, regardless of its duration, does not affect the converterupdate. A simple method of interfacing to a computerasynchronous to CB is:INH(1) Apply INH.(2) Wait 0.3 µs, min.(3) Transfer the data.(4) Release INH.ASYNCHROUS TO CB0.3 µs MAX;; ;;DATAVALIDFIGURE 5. INHIBIT TIMINGAs long as the converter maximum tracking rate is not exceeded,there will be no velocity lag in the converter output althoughmomentary acceleration errors remain. If a step input occurs, aswhen the power is initially applied, the response will be criticallydamped. FIGURE 6 shows the response to a step input. After initialslewing at the maximum tracking rate of the converter, thereis one overshoot (which is inherent in a Type II servo). The overshootsettling to a final value is a function of the small signal settlingtime.0.2 µs MAXDATAVALID; ;FIGURE 4. CB TIMINGθ 2OVERSHOOTINHIBIT (INH, PIN 9)When an Inhibit (INH) input is applied to the SDC-19204/6 theOutput Transparent Latch is locked, causing the output data bitsto remain stable while data is being transferred (see FIGURE 5).The output data bits are stable 0.3 µs after INH is driven to logic0. A logic 0 at the T input of the Inhibit Transparent Latch latchesthe data; a logic 1 applied to T allows the bits to change. Thislatch also prevents the transmission of invalid data when there isan overlap between CB and INH. While the counter is not beingupdated, CB is at logic 0 and the INH latch is transparent; whenCB goes to logic 1, the INH latch is locked. If CB occurs after INHhas been applied, the latch will remain locked and its data willnot change until CB returns to logic 0; if INH is applied duringCB, the latch will not lock until the CB pulse is over. The purposeof the 50 ns delay is to prevent a race condition between CB andINH where the up-down counter begins to change as an INH isapplied.θ 1DATA TRANSFERSSMALL SIGNALSETTLING TIMEMAX SLOPE EQUALSTRACKING RATE (SLEW RATE)FIGURE 6. RESPONSE TO A STEP INPUTDigital output data from the SDC-19204/6 can be transferred to8-bit and 16-bit bus systems. For 8-bit systems, the MSB andLSB bytes are transferred sequentially (see FIGURES 7A and7B). For 16-bit systems, all bits are transferred at the same time(see FIGURES 8A and 8B).5

ELEM(MSB) BIT 1ELBIT 2EMBIT 3BIT 4BIT 5BIT 6BIT 7SDC-19204/6 BIT 8BIT 9BIT 10BIT 11BIT 12BIT 13BIT 14BIT 15(LSB) BIT 16INHD7D6D5D4D3D2D1D08 BIT BUS(MSB) BIT 1BIT 2BIT 3BIT 4BIT 5BIT 6BIT 7BIT 8SDC-19204/6BIT 9BIT 10BIT 11BIT 12BIT 13BIT 14BIT 15(LSB) BIT 16INHD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D016 BIT BUSFIGURE 7A. 8-BIT BUS DATA TRANSFERFIGURE 8A. 16-BIT BUS DATA TRANSFERINH300 ns MINEM150 ns MININHDATA 1-8VALID0 ns MIN100 ns MAXEM, EL150 ns MIN300 ns MIN0 ns MINEL150 ns MIN0 ns MINDATA 1-8VALID100 ns MAXDATA 9-16VALID100 ns MAXFIGURE 7B. 8-BIT BUS DATA TRANSFER TIMINGFIGURE 8B. 16-BIT BUS DATA TRANSFER TIMING6

PROGRAMMABLE RESOLUTIONTURNS COUNTINGResolution is controlled by two logic inputs, A and B (see TABLE3). The resolution can be changed during converter operation sothe appropriate resolution and velocity dynamics can bechanged as needed. To insure that a race condition does notexist between counting and changing the resolution, inputs Aand B are transferred through the latch internally on the trailingedge of CB (see FIGURE 9).CBUSDC-19204/6MCC1UUP/DOWNCOUNTERTC0TABLE 3. RESOLUTION CONTROLB(PIN 8)0011A(PIN 7)0101RESOLUTION10 BIT12 BIT14 BIT16 BITNote: All unused digital output data bits are at logic 0.4 BITSNotes:(1) For the 4-bit up/down counter, use 74LS169B (TTL) or 4516 (CMOS).(2) U = up/down line, logic 1 counts up.(3) T = toggle line, counts on positive edge.FIGURE 10. TURNS COUNTING CONNECTIONDIAGRAMDIRECTION OUTPUT (U, PIN 31)CB0.1 µs MINA,BVALID;;; ;;FASTER SETTLING TIME USING BIT TO REDUCERESOLUTIONSince the SDC-19204/6 has higher precision in the higher resolutionmode and faster settling in the lower resolution modes, theBIT output can be used to program the SDC-19204/6 for lowerresolution, allowing the converter to settle faster for step inputs.High precision and fast settling can therefore be obtained simultaneouslyand automatically in one unit.When the resolution is changed, the VEL scaling is alsochanged. Since the VEL output is from an integrator with acapacitor feedback, the VEL voltage cannot change instantaneously.Therefore, when changing resolution while moving therewill be a transient with a magnitude proportional to the velocityand a duration determined by the converter bandwidth.MAJOR CARRY (MC, PIN 32)0 µs MINFIGURE 9. RESOLUTION CONTROL TIMINGMajor Carry is used with Direction Output (U) for multiturn applications.This signal is similar to a 4-bit up-down counter CO(Carry Out), that is, it is normally high and goes low for all 1’swhen counting up or all 0’s when counting down. See FIGURE10 for a typical interconnection.Direction Output (U) timing is shown in FIGURE 11. It is at logic1 to count up and logic 0 to count down. The logic level at (U) isvalid at least 0.5 µs before and at least 20 ns after the leadingedge of CB.CBMAJOR CARRYMCDIRECTION (U)SYSTEM SELF-TEST0.5 µs MIN20 ns MIN0.5 µs MINThe SDC-19204/6 provides two useful logic outputs for systemsself test: BIT and LOS.BUILT-IN-TEST (BIT, PIN 29)UP;COUNT;;;;;0.5 µs MINDON'T CARE;DOWNCOUNT0.5 µs MIN0.5 µs MINFIGURE 11. DIRECTION OUTPUT (U) TIMINGThe Built-ln-Test (BIT) output monitors the level of error (D) fromthe demodulator. D represents the difference in the input andoutput angles and ideally should be zero. If it exceeds approximately65 LSBs (of the selected resolution), the logic level at BITwill change from a logic 1 to logic 0. This condition will occur duringa large step and reset after the converter settles out. BIT willalso change to logic 0 for an over-velocity condition because the7

converter loop cannot maintain input-output sync, or if the convertermalfunctions where it cannot maintain the loop at a null.TABLE 4. DYNAMIC CHARACTERISTICSBANDWIDTHPARAMETER UNITSLOSS OF SIGNAL (LOS, PIN 28)HIGHLOWThe Loss of Signal (LOS) output is used for system safety. The RESOLUTION BITS 10 12 14 16 10 12 14 16LOS output changes from logic 0 to 1 if all three synchro inputs Input Frequency kHz .36-1 * * * .047-1 * *are disconnected. With disconnected synchro inputs, unpredictableTracking Rate RPS† 160 40 10 2.5 40 10 2.5converter performance occurs.Bandwidth, CL Hz 53 * * * 13 * *Ka1/sec 2 14.4k * * * 3.6k * *PROGRAMMABLE BANDWIDTH (BW, PIN 5)A1**1/sec 0.4 * * * 0.1 * *A2**1/sec 36k * * * 9k * *A**1/sec 120 * * * 30 * *Either low or high bandwidth can be selected by using the BWlogic input. A logic 0 applied to BW selects low bandwidth (13 Hznominal), while a logic 1 selects high bandwidth (53 Hz nominal).Bandwidth can be changed during converter operation.B**acc-1 LSB lagSettling timemax1/sec°/sec 2msec6017k110*4.2k110*1.1k200*260500151.1k550*260600*661100Bandwidth and the acceleration constant (K a ) can be determinedfrom the following formulas:†RPS minimum*Same as value to left**See FIGURE 15 for definitions of A1, A2, A, and B.Closed Loop Bandwidth (Hz) = 2 A / π*0.62******172400See Dynamic Characteristics TABLE 4 and FIGURES 15 to17 for values.CONTROL TRANSFORMER MODE (S, PIN 6)The converter will function as a Control Transformer (CT) byplacing S (pin 6) to logic 0. In the CT mode, the digital inputs aredouble buffered, EM is redefined as LM, EL is redefined as LLand INH becomes LA (see FIGURE 12). FIGURE 13 shows CTmode timing for a two-byte transfer.The CT mode is used when the AC error (e) is needed to drivean external control loop by the difference angle of the resolverinput and the digital input. It is also used for presetting the converterto a specific angle to reduce the step response time.LOS 28LOSS OFSIGNALDETECTORREFERENCECONDITIONER40 REFSYNCHROINPUT1-3SIGNALINPUTSIN θCOS θHIGHACCURACYCONTROLTRANSFORMERGAINeSIN(θ-φ)DEMODULATORDBITDETECT29 BIT+15 VLA(INH) 916 BIT CTTRANSPARENTLATCHDIGITALANGLE φDIFFGAINOF 239 eLM(EM) 1016 BITU-D COUNTER(SET MODE)12-19 20-271-8 9-1611 LL(EL)7A8BRESOLUTIONCONTROL+11 V+5.5 V-15 VPOWER SUPPLYCONDITIONER34 +15 VFIGURE 12. CONTROL TRANSFORMER BLOCK DIAGRAM8

(LA) INHS = 0tsuithuithe power supply level. The analog output VEL characteristicsare listed in TABLE 5. The VEL output has DC tachometer qualityspecs such that it can be used as the velocity feedback inservo applications.DATA IN(LM) EM(LL) ELtsu;; ;; ;Notes:(1) tw = 100 ns min (pulse width) 1 - data held in latch,th = 50 ns min (hold time)0 - latch is transparent,thui = 0 ns min (hold time inhibit)tsu = 0 ns min (setup time)(3) (LA) INH is latch controltsui = 300 ns min (setup inhibit)for CT latch:(2) When S is low: 1 - latch is transparent,(LM) EM is latch control for MSB byte, 0 - data held in latch.(LL) EL is latch control for LSB byte,ANALOG OUTPUTSThe analog outputs are AC error (e) and velocity (VEL). If theanalog outputs are not required, ground -15 V (pin 36).AC ERROR (e, PIN 39)AC Error Out (e) is used in CT mode. The AC error is proportionalto the difference between the resolver input angle θ andthe digital input angle φ, (θ − φ), with a scaling of:50 mVrms/LSB (10-bit mode)25 mVrms/LSB (12-bit mode)12.5 mVrms/LSB (14-bit mode)6.3 mVrms/LSB (16-bit mode)twthFIGURE 13. CT MODE TIMING - TWO-BYTETRANSFER, DOUBLE BUFFEREDThe error is positive if it is in phase with the reference and negativeif it is out of phase with the reference. The e output canswing ±10 V peak min with respect to ground when the voltagelevel of the ±15 V power supplies are 15 V. The output level rangechanges proportionally with the power supply level.tsutwthPARAMETERPolarityVoltage scalingScale FactorScale Factor TCReversal ErrorLinearityZero OffsetZero Offset TCLoadOutput VoltageVELOCITY PROGRAMMING (VEL PROG, PIN 37)The velocity output scale factor can be increased by connectingan external resistor (R) from VEL PROG (pin 37) to ground. Byscaling up the output, the noise and offset will increase proportionally.The value of R can be determined by the following formula:Where:TABLE 5. VELOCITY OUTPUT CHARACTERISTICSR =10 B/A1 - B/AR = external resistor in k OhmsA = specified voltage scaling (RPS/VOLT)B = desired voltage scaling (RPS/VOLT)RUNITRPS/V%PPM/°C%% outputmVµV/°Ck OhmsVVEL PROGTo determine A, refer to TABLE 6, Voltage Scaling.37TYPSDC-19204/6SDC-19204/6MAX(positive for increasing angle)See Voltage Scaling TABLE 6.10151002001211525-±13240503±10 minVELOCITY (VEL, PIN 38)The velocity output (VEL, pin 38) is a DC voltage proportional toangular velocity dθ/dt. The velocity is the input to the voltagecontrolledoscillator (VCO), as shown in FIGURE 1. Its linearityand accuracy is dependent solely on the linearity and accuracyof the VCO. The maximum VEL output can swing ±10 V min withrespect to ground when the voltage level of the ±15 V power suppliesare 15 V. The output level range changes proportionally withTABLE 6. VELOCITY OUTPUT VOLTAGE SCALING (RPS/VOLT)BW 10 BIT 12 BIT 14 BIT 16 BITHIGH 16 4 1 0.25LOW 4 1 0.25 0.0629

DYNAMIC PERFORMANCEA Type II servo loop (K v = ∞) and very high acceleration constantsgive the SDC-19204/6 superior dynamic performance aslisted in TABLE 4.VELOCITY RESPONSESYNCHROINPUTERROR PROCESSORVCOCTA S+ e 1 + 1A B 2SS S + 1-10BVELOCITYOUTDIGITALPOSITIONOUT (φ)A filter on the VEL output will, for a step input in velocity, eliminatethe velocity overshoot (normally critically damped) and filtercarrier frequency ripple. The VEL filter is shown in FIGURE 14.VELHIGH BWR=100kC = 0.082 µFVELFILTEREDτ = RC = 1/ACONVERTERTRANSFERFUNCTIONG =H = 1Note: See TABLE 4 for values of A1 A2, and BS A + 11 B2 S S + 110BWHERE:A 2 = A 1 A 2FIGURE 15. TRANSFER FUNCTION BLOCK DIAGRAMVELR=100kVELFILTEREDLOW BWTRANSFER FUNCTIONSC = 0.33 µFFIGURE 14. VEL OUTPUT FILTERτ = RC = 1/A-12 db/oct4BA2A-6 db/octω (rad/sec)10BThe dynamic performance of the converter can be determinedfrom its transfer function block diagram (FIGURE 15) and openand closed-loop Bode plots (FIGURES 16 and 17 and TABLE 4lists the parameters relating to the SDC-19204/6’s dynamic characteristicsfor different resolution and bandwidth modes.FIGURE 16. OPEN LOOP BODE PLOTACCURACY AND RESOLUTIONTABLE 7 lists the total accuracy including quantization for thevarious resolution and accuracy grades.SDC-1920X SERIESMODEL NO.TABLE 7. ACCURACY/RESOLUTIONACCURACY10BIT12BIT14BIT16BIT2A2 2 Aω (rad/sec)SDC-1920X-304SDC-1920X-303SDC-1920X-302SDC-1920X-3012’ + 1 LSB3’ + 1 LSB4’ + 1 LSB8’ + 1 LSB23.124.125.129.17.38.39.313.33.34.35.39.32.33.34.38.3CLOSED LOOP BW (Hz) =2 AπFIGURE 17. CLOSED LOOP BODE PLOT10

SDC-19204 APPLICATIONSUSING THE SDC-19204/6 IN THE CT MODEThe CT mode can be applied in servo systems, as shown in FIG-URE 18. In this application changes in position are commandedby the computer through signals fed to the CT. The CT then drivesthe motors through DC power amplifiers.INTERFACING THE SDC-19204/6WITH AN IBM PC/XT/AT®The SDC-19204/6 can be connected to an IBM PC/XT/ATthrough the IBM PC Bus located at address HEX 300 through303. This location is reserved by the PC for prototype cards.FIGURE 21 illustrates the connection to the IBM PC Bus; FIG-URE 20 illustrates the timing considerations for the interface.MULTITURN APPLICATIONS-USE OF MAJOR CARRY (MC,PIN 32)Refer to Major Carry paragraph for details.USING THE SDC-19204/6 AS AN S/D WITH VEL TOSTABILIZE POSITION LOOPFIGURE 19 illustrates a typical use of a SDC-19204/6 connectedas an S/D using the VEL output to stabilize the position loop.SDC-19204/6-To-IBM PC/XT/AT Theory of Operation1. The port address where the SDC-19204/6 is located is hardwired with jumpers into the 74LS688 address decoder. Thisaddress is HEX 300 through 303 and is reserved for prototypecards.2. Address line A1 selects the upper or lower 8 bits of theSDC-19204/6 to be placed on the Bus. When A1 is high, bits 1-8 are selected.3. Address line A0 sets and resets the SDC-19204/6 INHIBIT(INH) line. When A0 is low, the INHIBIT command is invoked.SYNCHROAMPDEMODULATORe SDC-19204/6 as a CTSµ COMPUTERFIGURE 18. CT MODE APPLICATIONREF4. To read the output of the SDC-19204/6 perform thefollowing:a. Send address HEX 302 to INHIBIT the SDC-19204/6(hold data stable) and place bits 1-8 on the Bus. Read andstore data on D0 to D7.b. Send address 300 HEX to keep the SDC-19204/6 in theINHIBIT mode and place bits 9-14 on the Bus. Read andstore data on D0 to D7.c. Read address 301 HEX or 303 HEX to release theSDC-19204/6 from the INHIBIT mode and prepare for thenext measurement. No valid data will be on the bus duringthis command.5. Since the output data is not valid until 0.5µs after the INHIBITcommand is invoked, the l/O READY line is held low for this periodof time. When l/O READY returns to the high level, the dataon the bus reads on the next negative clock edge.LATCH READ DATASYNCHROREFSOURCECLKOUTAMPALEOUTADDRVALID ADDRESSOUTD/ACOMPUTERS/DCON-VERTERI/OREADY500 nsec MIN PULSEINVELI/O ROUTFIGURE 19. S/D WITH VEL TO STABILIZE POSITION®IBM PC/XT/AT is a registered trademark of International Business MachinesCorporation.11FIGURE 20. PC APPLICATION - I/O READCYCLE TIMING

BIT 16(LSB)BIT 15BIT 14BIT 13BIT 12BIT 11D0D1D2D3D4D5D6D7Y1Y2Y3Y4Y5Y6Y7Y8BUS DRIVER74LS465GBIT 10BIT 9SDC-19204/6BIT 8BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2INHBIT 1 (MSB)EM EL74LS121QA274LS467Q CLKD500 nSEC MINPULSEIBMBUSI/O READALEGY1 Y2 Y3 Y474LS374A9A8GP0P1P=QQ0Q1A1 A2 A3 A43 STATEBUFFERA7A6A5P2Q2ADDRESSP3 DECODER Q374LS688P4Q4ADDRESSSELECTIONJUMPERSA4A3A2P5P6P7Q5Q6Q7A1A0I/O READYFIGURE 21. SDC-19204/6-TO-PC CONNECTION DIAGRAM12

TABLE 8. SDC-19204/6 PIN FUNCTIONSPIN NO. TITLE I/0 FUNCTION12345678910111213141516171819202122232425262728293031323334353637383940S1S2S3NCBWSABINHEMEL12345678910111213141516LOSBITCBUMC+5 V+15 VGND-15 VVEL PROGVELeREFIIIIIIIIIIIOOOOOOOOOOOOOOOOOOOOOII-IIOOISynchro Input.Synchro Input.Synchro Input.No connection.Bandwidth. Logic 1 for high BW (53 Hz); logic 0 for low BW (13 Hz).Control Transformer Set. Logic 1 for normal tracking logic 0 for CT operation. Used when AC error (e)is needed to drive external control loop by the difference angle of the resolver input and the digitalinput and for presetting the converter to a specific angle to reduce the step response time.Resolution Control A. Change Resolution to 10, 12, 14, or 16 bit depending on logic level (See TABLE 3).Resolution Control B. Change Resolution to 10, 12, 14, or 16 bit depending on logic level (See TABLE 3).Inhibit. Logic 0 prevents digital output bits from changing.Enable MSBs. Logic 0 enables digital output bits 1-8. Logic 1 disables these bits.Enable LSBs. Logic 0 enables digital output bits 9-16. Logic 1 disables these bits.Digital Output Bit 1 (MSB all modes).Digital Output Bit 2.Digital Output Bit 3.Digital Output Bit 4.Digital Output Bit 5.Digital Output Bit 6.Digital Output Bit 7.Digital Output Bit 8.Digital Output Bit 9.Digital Output Bit 10 (LSB-10 BIT MODE).Digital Output Bit 11.Digital Output Bit 12 (LSB-12 BIT MODE).Digital Output Bit 13.Digital Output Bit 14 (LSB-14 BIT MODE).Digital Output Bit 15.Digital Output Bit 16 (LSB-16 BIT MODE).Loss of signal. Used for system safety; the LOS output changes from logic 0 to 1 if all three synchroinputs are disconnected.Built-ln-Test. Monitors level of error (D) and will change to logic 0 if it exceeds approximately 65 bits .Also logic 0 for an over-velocity condition.Converter Busy. Indicates digital output update.Direction. Logic 1 to count up; logic 0 to count down.Major Carry. Used for turns counting applications; normally high goes low for all 1 ‘s whencounting up or all 0’s when counting down.Supply Voltage.Supply Voltage.Ground.Supply Voltage.Velocity Programming. Increase output scale factor with external resistor (R) from VEL PROG (pin 37)to ground.Velocity. DC voltage proportional to angular velocity.AC Error. Used in CT mode; e is proportional to the difference between the resolver input angle θ andthe digital output angle φ (θ - φ).AC Reference Input. Used to drive internal demodulator.13

REFERENCEOSCILLATORLOHISTATORR2R1S3S3REFCBVELS1S2S1S2SDC-19204/6PARALLELDATACAN INTERFACEWITH 8- OR 16-BITMICROPROCESSORROTORINHELEMFIGURE 22. SYNCHRO CONNECTIONSOURCES OF SOCKETS FOR THE SDC-19204/6The following companies are sources of sockets for use with theSDC-19204/6 Series. Consult them for more information.Aries Electronics, Inc.Single In-Line SocketP.O. Box 130Strip-Line SocketTrenton AvenueFrenchtown, NJ 08825-0130 Part No.20-05511 -11Tel: 1-908-996-6841http://www.arieselec.comCONNECTING THE SDC-19204/6The SDC-19204/6 can be attached to a PC board using handsolder or wave soldering techniques. Limit exposure to 300°C(572°F) max, for 10 seconds maximum.Do not use vapor phase soldering as this product containsSN60 or SN62 solder which melts at 180°C (356°F). Since theSDC-19204/6 Series converters contain a CMOS device,standard CMOS handling procedures should be followed.Circuit Assembly Corp.18 Thomas StreetIrvine, CA 92618-2777Tel: 714-855-7887http://www.ca-online.comPart No. CA-20-STL-XX XX-X14

1.14 MAX(28.96)1 400.050TYP(1.27)60/40 TINLEAD PLATEDPHOSPHORBRONZEPIN 1DENOTED BYORIENTATIONMARK0.018TYP(0.46)2.02 MAX(51.3)19 EQ. SP.@0.100=1.900TOL. NON CUMTYP(@2.54=48.26)PIN NUMBERSFOR REF. ONLY20 210.11TYP(2.79)0.010TYP(0.25)0.90TYP(22.86)0.23MAX(5.84)0.160±0.040(4.06 ±1.02)0.100TYP(2.54)0.50TYP(1.27)FIGURE 23. SDC-19204/6 MECHANICAL OUTLINEORDERING INFORMATIONSDC-1920X-30XAccuracy:1 = 8 min + 1 LSB(12 LSBs Differential Linearity)2 = 4 min +1 LSB(8 LSBs Differential Linearity)3 = 3 min +1 LSB(4 LSBs Differential Linearity)4 = 2 min +1 LSB(4 LSBs Differential Linearity)Configuration:4 = 11.8 V, 2% Linearity6 = 90 V, 2% LinearityNote: Differential Linearity is x LSB in the 16th bit.15

The information in this data sheet is believed to be accurate; however, no responsibility isassumed by Data Device Corporation for its use, and no license or rights aregranted by implication or otherwise in connection therewith.Specifications are subject to change without notice.105 Wilbur Place, Bohemia, New York 11716-2482For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413Headquarters - Tel: (631) 567-5600 ext. 7389 or 7413, Fax: (631) 567-7358Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689World Wide Web - http://www.ddc-web.comILC DATA DEVICE CORPORATIONREGISTERED TO ISO 9001FILE NO. A5976J-11/99-500PRINTED IN THE U.S.A.16