Switch - PLX Technology

PLX TechnologyPCI Express ProductsFebruary 2008© PLX Feb 20081

Corporate Overview‣ Public U.S. Company• Founded in 1986• IPO in 1999• NASDAQ: PLXT‣ Headquarters in Sunnyvale, CA• 160 Employees• Sales & Technical Support Worldwide• Fabless Semiconductor Business Model‣ Market Leader• 60%+ Marketshare in PCI Express Switches & bridges‣ Financially Solid• Zero Debt, Cash in Bank, Cash Flow Positive© PLX Feb 2008 2

The “Ideal” World?CPUSingleChipChip SetMemorySingleChipI/OIn the ideal world,you would not needany interconnectI/OI/O© PLX Feb 2008 3

Real World Needs InterconnectSwitchCPUChip SetMemoryTo Support MultipleI/O Standards& to Switch SerialPoint to PointPCI ExpressI/OSwitchBridgeLocalBusBridgeBridgeI/O© PLX Feb 2008 4

PLX Interconnect Products - Bridges‣ PLX is the World Leader in I/O Interconnect Products‣ Our broad product line of devices can bridge popular I/Ostandards including PCI Express®LocalBusBridgesConceptual Drawing, not every possible option available currently from PLX© PLX Feb 2008 5

Systems of Today Need SwitchingSwitchYesterday’s PCI BusToday’s PCI Express BusParallelSerialSharedPoint to PointNo Switching NeededSwitching Required© PLX Feb 2008 6

PLX Main Focus – PCI Express Switches‣ PLX Technology’s main focus today:• Supporting the quickly growing worldwide demand forPCI Express Switching• Fastest growing new basic building block for the systemsof today & tomorrow• Demand for switches are more than doubling each year‣ Since 2004 PLX has suppliedover 60% of the worldwidedemand for PCIe Switches‣ Best-in-Class Products• Performance, Power, Features• Quality & Cost© PLX Feb 2008 7

PCI Express® Focus = Leadership‣ Market Leader• Engaged with most leading server, storage, & communicationcompanies• Only public semiconductor company focused 100% on PCIExpress Switches & Bridges‣ Broadest Offering of PCI Express Bridges & Switches‣ Over $50M and 2M Units shipped‣ Objective:• Remain #1 Supplier ofPCI Express Switches& Bridges in the Industry© PLX Feb 2008 8

PLX PCIe History & Track Record‣ 2001:• Started investing in PCI Express technology‣ 2004:• Market’s 1st PCIe Switch (32 Lanes, 8 Ports)‣ 2005:• Company’s 1st PCIe Bridge‣ 2006:• 2 nd Generation Switch Architecture‣ 2007:• 3 rd Generation Switch Architecture• Industry’s 1st control plane PCIe switch• Sampled industry’s broadest Gen 2 Switch Offering• Shipped our Millionth PCI Express chip earlier this year• Crossed the $50M mark in PCI Express salesNOTE: All 17 PCI Express Products in Production today….went to production with 1 st Silicon (No exceptions)© PLX Feb 2008 9

PLX Dominant Supplier‣ PLX has continued to maintain60-70% marketshare forSwitches and Bridges• Time to Market• Superior Products• Product Line‣ Current success withNew Gen 2 Switches willextend this well into thefuture© PLX Feb 2008 10

PCI Express Momentum‣ PCI Express Started in the Computing & Storage Markets• But has spread to most major markets the past couple years• Networking and Communications• Instrumentation and EmbeddedMarkets& ApplicationsEmbeddedInstrumentationPrinters1000’s of OtherApplicationsPCI Express Based SystemShipments Growing RapidlyCommunicationsRouters/SwitchesG-Ethernet10G-EthernetBase StationsReplaceProprietaryStorageRAIDFibre Channel HBAFibre ChannelSwitchServers & WorkstationsRack ServersServers GraphicsWorkstations Blade ServersClustersPC & PC Peripherals/ConsumerDesktops Notebooks GraphicsPrintersTV TunersSet TopBoxesTVsTime© PLX Feb 2008 11

PLX Customer ApplicationsCommunicationsServerRouterSwitchWirelessGatewayBase StationPC Peripheral& ConsumerRack-mountTowerBladeSmartphoneVideo CamGraphics/VideoImaging/GraphicsIndustrialNASEmbeddedPrinterMedicalSANHBAStorage© PLX Feb 2008 12

PCI Express in ServersBridgeGECPUGESwitchChip SetMemoryAdapter & Riser CardsSwitchStand-alonealoneSwitchI/OI/ORack-mountBladeI/OBridgeI/OServerMotherboard© PLX Feb 2008 13

PCI Express in Storage SystemsCPUCPUStorageSANNASChip SetMemoryChip SetMemoryFCFCSwitchSwitchNTI/ONTSwitchI/OI/OI/OSASSASSwitchBridgeI/OBridgeI/OHigh Availability Storage System© PLX Feb 2008 14

PCI Express in Peripherals & ConsumerGPUBridgeGPUGPUSwitchGraphics - Reverse BridgeGraphics – More Monitorsor Higher ResolutionTVTunerBridgeMobileTVPCI Express TV TunerComputer Peripheraland Consumer ElectronicsPrinterWireless LANGraphics/Video© PLX Feb 2008 15

PCI Express in CommunicationsCo-Processor/Security/DSPDSLAMBase StationControllerWirelessLAN GatewayEnterprise StorageSwitchNTNPU/ASICVoIPGatewayRemote AccessConcentratorRouter/SwitchLocalProcessorFramerPHYLine Card 1CommunicationsLine Card nSwitchControlProcessorMemorySupervisory or Controller Card© PLX Feb 2008 16

PCI Express in EmbeddedFPGAFPGABridgeBridgeMemoryCPUImaging/GraphicsPrinterMedicalIndustrialEmbeddedSwitchFPGABridgeIndustrial Control &InstrumentationI/OI/OHostCPUBridgePCIeASICEmbedded Host System© PLX Feb 2008 17

Technology and Supply‣ Solid Relationships with State of the Art Foundries• TSMC @ .09u, .13u & .18u• Seiko Epson‣ Use Leading ASIC Vendors forSome Products• NEC• Fujitsu‣ Engineering & Marketing Expertise Enhancedvia Acquisitions• Sebring, HiNT, and NetChip© PLX Feb 2008 18

Executive Management TeamJacqueline DeelyExecutive AdministrativeMikeSalamehLarryChisvinPresident & CEOArtWhippleCOOCFODavidRaunMattReadyGeorgeApostolVP Marketing& BusinessDevelopmentVP SalesHectorBerardiCTOBadarBaqaiKenMurrayVP OperationsVP EngineeringVP of HR© PLX Feb 2008 19

Product OverviewBrief Overview of theProduct Families &ApplicationsSee Detailed Section formore Information© PLX Feb 200820

PLX Interconnect Families‣ PCI 9000 I/O Accelerator Series• Generic/Local Bus to PCI Bridges‣ PCI 6000 FastLane Series• PCI and PCI-X Bridges‣ NET 2000 NetChip Series• USB 2.0 to PCI & Generic/Local Bus Devices/Bridges‣ PEX 8000 ExpressLane Series …Introduced in 2004• PCI Express Bridges and Switches• PLX’s Largest & Fastest Growing Product Line© PLX Feb 2008 21

ExpressLane PCIe SwitchesPEX 8500PEX 8600Series‣ Broad Offering• Gen 1 (2.5 GT/s) & Gen 2 (5.0 GT/s)• 5 to 48 PCIe Lanes• 3 to 12 Flexible Ports• x1 to x16 Port Configurations‣ Additional Features• Industry’s Lowest Latency ~110ns& Highest Performance• Non-Transparent Portfor Dual Hosts/Failover• Read Pacing, Dual Cast, &Dynamic Buffer Allocation• True Peer-to-Peer& Fan-Out Capabilities• Up to 2 Virtual Channels• Unique Debug Capabilities• Industry’s Lowest Power& Smallest Packages© PLX Feb 2008 22

Server SystemsCPUChip SetMemoryEndPointSwitchEndPointBridge© PLX Feb 2008 23

‣ Possible I/Os• Ethernet• Fibre Channel• SCSI• InfiniBandStorage and CommunicationsI/OFPGALocal BusBridgeCPUI/OSwitchI/OI/OSwitchBridgeUsed on theBackplane© PLX Feb 2008 24

Dual Host Designs‣ PLX pioneering Non-Transparentbridging features to PCI Expresstechnology‣ Non-proprietary technology‣ Fully compatible with PCIExpress architecture andAdvanced Switching architectureI/OSecondaryHostCPUSecondary Host can takeover if Primary Host Failsusing NT Port on SwitchCPUI/OI/OI/OI/OSwitchNTNon-Transparent(NT) Port© PLX Feb 2008 25

Blade ServersNodeLogicNodeLogicNodeLogicNodeLogicNodeLogicNodeLogicNTNTSwitchNTSwitchNTSwitchNTSwitchNTSwitchNodeNodeNodeFabricNodeNodeNode© PLX Feb 2008 26

Switch-Based Add-In Cards‣ I/O Card• Switch used for Fan-In• All ports on the switchare transparentPCIeDevicePCIeDevice88PEX 853316‣ Intelligent Adapter• Switch used to isolatelocal memory from Hostprocessor using Non-Transparent Bridginginside the switchPCIeDevicePCIeDevice44MemoryCPUNT4PEX 86164© PLX Feb 2008 27

ExpressLane PCI Express Bridges‣ PCI to PCI Express• 32-Bit PCI (66 MHz)• x1 PCIe‣ PCI-X to PCI Express• 64-Bit PCI-X (133 MHz)• x4 PCIe‣ Additional Features• Forward & Reverse• Low Power• Small PackagesPCI or PCI-XPEX 8100Series‣ In Production!© PLX Feb 2008 28

PCIe Bridge ApplicationsPCIeEndpointI/O AdapterPCI ExpressBridgePCI ExpressCableHost AdapterPCI ExpressP-BridgeBridgeBridgeForwardBridgePCI or PCI-XI/O Expansion ChassisReverseBridgePCI or PCI-XHost System‣ Reverse Mode‣ PCI Express over Cable• Use the latest PCI• Use in Forward BridgeExpress native siliconmode at one end &devices in legacyReverse Bridge mode atapplicationsthe other end• Or create legacyPCI/PCI-X slots© PLX Feb 2008 29

PLX is All About Support‣ Documentation on Website• Specifications, White Papers,Reference Designs/Application Ideas‣ Development Tools• Best in Class, Complete Hardware& Software Development Platforms‣ Interoperability Lab• Shortens time to market by providing tested, reusable, deployablehardware and software components. Reports on Website.‣ Support Portal• Huge database of answers• Quick Response to Support Requests© PLX Feb 2008 30

Product Summary& Road MapsPLX PCIe Products© PLX Feb 200831

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LanesPLX Gen 2 Switch Road Map> 6448322416PEXPEX 8647864848 Lane, 3 Ports48 Lanes122KB, DC,Ports,RP, DBNT2KB, 3HPC, DC, RP, DBPEX 863232 Lanes, 12 Ports, NT2KB, 3HPC, DC, RP, DBPEX 862424 Lanes, 6 Ports, NT2KB, 3HPC, DC, RP, DBPEX 861616 Lanes, 4 Ports, NT2KB, 3HPC, DC, RP, DB1 st Gen 2 FamilyGeneral PurposeGraphics, ServerNetworking, StorageBackplanes, HBAs/NICsEmbeddedFuture Products:Additional Product Detailscan be sharedunder NDA12PEX 8612 PEX 861212 Lanes, 3 Ports, NT2KB, 3HPC, DC, RP, DB8Shipping NowIn Development

PLX PCIe NEW Gen 2 Switch FamilyFeature PEX 8648 PEX 8632 PEX 8624 PEX 8616 PEX 8612Lanes 48 32 24 16 12Ports 12 12 6 4 3Latency 140 ns (x16) 145ns (x8) 145ns (x8) 150ns (x4) 150ns (x4)Non-Transparency Yes Yes Yes Yes YesRead Pacing Yes Yes Yes Yes YesDual Cast Yes Yes Yes Yes YesHot-Plug Ports3 SHPC & 9Serial3 SHPC & 9Serial3 SHPC &3 Serial2 SHPC &2 Serial2 SHPC &1 SerialMaximumPayload Size 2KB 2 KB 2 KB 2 KB 2 KBFlip-ChipPackage (mm 2) 27 x 27 27 x 27 19 x 19 19 x 19 19 x 19Typical Power 4.0 W 2.8 W 3.0 W 2.2 W 2.0 WSamples Now Now Now Now NowProduction April 08 April 08 April 08 April 08 April 08Available today….more Gen 2 devices in development© PLX Feb 2008 34

Bridge Road Map - PCI, PCI-X, PCIePCI/PCI-XBus Speeds64 Bits133 MHz64 Bits66 MHzPCI 6254Non-TransparentAsynchronousPCI 6154Asynchronous31x31 mm 2 304 PBGAPCI 6466Non-TransparentAsynchronousPCI 6540PCI-X Non-TransparentAsynchronousPCI 6520PCI-X Asynchronous27x27 mm 2 380 PBGAPEX 811464-Bit 133MHz PCI-Xto x4 PCIe• Forward & Reverse Mode• Small 17x17mm Package• No Heat Sink Required32 Bits66MHz32 Bits33MHzPCI 6150High PerformanceAsynchronousPCI 6152Smallest Footprint15x15 mm 2 160 TBGAPCI 6140Lowest Power(200mW)Shipping NowIn DevelopmentPlanned/ConceptPEX 811132-Bit 66MHz PCIto x1 PCIe• Forward & Reverse Mode• Small 10x10 & 13x13mm Package• No Heat Sink RequiredPEX 8112Cost Reductions &Enhancements2003 & Before20042005 2007© PLX Feb 2008 35

PCI Express SwitchesKey Product FeaturesGen 1 & Gen 2© PLX Feb 200836

Key Advantages of PLX PCIe Switches‣ Unique PLX Features• Port Flexibility• Non-Transparency• Hot-Plug• Cut-Thru• Port Arbitration• Non-Blocking Architecture• True Peer to Peer• Limited ClockRequirements• SSC Support• Dual Host and Failover• Superior Software (SDK)‣ Unique Features (continued)• Read Pacing• Dual Cast• Dynamic Buffer Allocation• Debug Diagnostic Tools‣ Premium PLX Benefits• Lowest Power & Latency• Highest Performance• Smallest Packaging• Excellent Field Support• Superior Quality, Reliability• Availability of Product!© PLX Feb 2008 37

Port Flexibility – PLX Advantage‣ Flexible• Ports configurable as x1, x2, x4, x8, x16• Customize to meet your design’s needs• Auto-negotiation of port width supported• Will negotiate down to x8, x4, x2, or x1‣ Versatile• Any port can be upstream• Movable upstream port• Cross-link & NT capability• Dual-host supportx2 portsx4 portsx8 portx16 portPCIeSwitchcombine© PLX Feb 2008 38

Dual-Host & Failover Options‣ Two methods of implementing Failover Systems• Non-Transparent Port• Crosslink & Moveable Upstream Port PrimaryHostSecondaryHost‣ Crosslink & Moveable Upstream Port• Utilized when user has full control ofsystem software (OS)and enumeration processSwitch‣ Non-Transparent Port• Utilized when user has no or limited control of systemsoftware (OS) and/or enumeration process© PLX Feb 2008 39

Crosslink & Moveable Upstream PortPrimary HostCPUSecondary HostCPURootComplexRootComplexEndPointSwitchUpstreamDownstreamCrosslinkSwitchEndPointEndPointEndPointEndPointEndPoint‣ Crosslink allows 2 downstream ports to link up‣ Crosslink and moveable upstream functions can be used to providedual host or fail-over capability© PLX Feb 2008 40

Non-Transparent Port‣ One Port on Switch Designated as Non-Transparent Port‣ Isolates 2 Hosts from Endpoints• Endpoints mapping to differentmemory space on 2 hosts (CPUs)• Inter-processor communicationthrough mailbox & doorbell registers• Capable of configuring both Link-sideand Virtual-side registers‣ Applications• Dual-host/Multi-host• Host-Failover/Redundant Systems• ...and Intelligent I/O ModulesNon-TransparentPortIntelligent I/O AdaptorI/OI/ONTSwitchCPUPrimary HostCPURootComplexSwitch NTEndPointNon-TransparentPortSecondary HostCPUEndPoint© PLX Feb 2008 41

Configure Both Sides of NT Port‣ Two sides of NT Links:• Link-Side• Virtual-Side‣ Link-Side• The side linked to thehost/processor‣ Virtual-Side• The side beingisolated from thehost/processorPrimary HostCPURootComplexLink-SideSwitchNTVirtual-SideNTSecondary HostCPURootComplexLink-SideSwitch‣ PLX NT Switches capable of configuring both sides ofNT link in case of failover or back-to-back NT© PLX Feb 2008 42

Crosslink or Non-TransparencyPrimary HostCPUSecondary HostCPUPrimary HostCPUSecondary HostCPURootRootComplexComplexRootComplexEndPointSwitchUpstreamDownstreamCrosslinkSwitchEndPointNon-TransparentPortSwitch NTEndPointEndPointEndPointEndPointEndPointEndPointEndPointCrosslink is useful when user hasfull control of system software(OS) and enumeration processNT is needed when user has no orlimited control of system software(OS) and/or enumeration process© PLX Feb 2008 43

Lower Device Count – Failover/Dual-Host‣ PLX Integrated Non-Transparent (NT) Port in Switches• Move upstream port if primary host fails‣ Other solutions require external NT devices• Costs more and consumes valuable SPACE & POWER• Upstream traffic has no where to go if primary host failsPLXSwitchesPrimary HostCPUSecondary HostCPUSwitchwithoutNT PortPrimary HostCPUSecondary HostCPURootComplexRootComplexEndPointNTSwitchEndPointEndPointNon-TransparentPortEndPointSwitchEndPointEndPoint8NT2Non-TransparentBridging Device© PLX Feb 2008 44

PLX Leadership in NT‣ PLX created de facto standard for Non-Transparent Bridgingon PCIe Switches• Educated the market on 1 st NT implementation on PCIe‣ NT Switches in Production since 2005• Single-chip solutions with integrated NT Port• Hundreds of thousands NT units shipped to customers• Dozens of customers in full production with NT devices• 12 Products with Integrated NT…and more in development‣ PLX is the only vendor offering NT in Gen 2 switches• Shipping today!© PLX Feb 2008 45

Integrated Hot-Plug = PLX AdvantagePLX PCIeSwitchPCIe Hot-Plugcontrol registersPCIe Switchw/o Hot PlugControllerNo PCIe Hot-Plugcontrol registersVoltageCont.ClkVoltageCont.CPLD$$!ClkPowerHPPERSTClockPowerHPPERSTClock‣ PLX PCIe Switches‣ Other PCIe Switches• Internal Hot-Plug Controllers • Require External CPLD $$!• Provide PCIe Hot-Plug Registers• May not provide PCIe Hot-Plugand 9 Hot-Plug signalsRegisters Software burden!• Minimal External Circuitry Needed• Additional External Circuitry Needed• Available on 2 to 8 ports© PLX Feb 2008 46

Cut-Thru…for Reduced Latency‣ Cut-Thru Architecture – reduced latency• Moves packet to Egress port after reading packet header• Increased performance with bursty traffic‣ Store & Forward Architecture• Moves packet to Egress port after reading entire packet1001011000110110IngressPortCut-Thru PathEgressPort1001011000110110PayloadHeaderPCIe SwitchPayloadHeader1001011000110110PayloadHeaderIngressPortStore & Forward PathEgressPort1001011000110110PayloadHeader© PLX Feb 2008 47

True Peer-to-Peer SupportRootComplexRootComplexEndPointSwitchEndPointEndPointOther PCIeSwitchesEndPointEndEndPointPoint‣ PLX PCIe Switches• Simultaneous Transactions• No host involvement• Reduced latency• Enhanced CPU Performance• Optimized Peer-to-PeerBandwidth/PerformanceEndEndPointPoint‣ Other PCIe Switches• Claim Peer-to-Peer…but…• No Simultaneous Transactions• May require host-support• Added latency• Reduced CPU Performance• Bandwidth/Performance impactfor Peer-to-Peer traffic© PLX Feb 2008 48

Port Arbitration‣ Allows priority assignment to specific ports• Round Robin or Weighted Round Robin schemes can be usedEgress PortSwitch010101000011110101011010101000011110101011010101000011110101011010101000011110101011010101000011110101011010101000011110101011010101000011110101011010101000011110101011PacketQueueUser assigns priority or weightfor portsExample:Green port weight = 2Yellow and Gray weight = 1Port arbiter serves green porttwice the rate of other portsIngress Ports© PLX Feb 2008 49

Non-Blocking Internal Architecture‣ Allows traffic between ports at full line rates‣ Flexible buffer allocation‣ No head of line blocking• Bus Depot Analogy• One queue for all destinations Head of line blocking if a bus delayed• Separate queue for each destination No head of line blocking!Switch© PLX Feb 2008 50

Flexible Device Configuration‣ Register Configuration via:• I 2 C – Two wire protocoldefined by Philips• Out of band deviceconfiguration• EEPROM – Serial Load• Configures device prior toBIOS access• In Band – Memorymapped via PCIe link• In band deviceconfiguration by host‣ Hardware Strapping• Using Pull-up/Pull-downresistorsSignal StrappingSwitchI 2 CCSRsEEPROMPCIeUpstream LinkMultiple Ways to Configure PLX Switches© PLX Feb 2008 51

Spread Spectrum Clock Support‣ SSC Systems Supports Single Clock Domain• Reduces EMI‣ Supports two clock domains• SSC Domain• Modulated clock input• Constant clock domain• Constant clock inputHost 1SSC Domain 1Host 2SSC Domain 2‣ Advantages for having two clock domains• Removes requirement for single source clock• Important for modular systems© PLX Feb 2008 52

Spread Spectrum Clock SupportTHost 1SSC Domain 1OSCSSC ClockBufferCPUBridgeConstant ClockDomain (Non-SSC)CPUBridgeHost 2SSC Domain 2OSCSSC ClockBufferI/OI/OI/OSwitch NT SwitchTNTI/OI/OOSCOSCI/OConstant Clock Input© PLX Feb 2008 53

Power Management‣ Supports all required PCIe Link & Device Power Management States‣ Additional Power Management Support• WAKE#• Out of band mechanism used by endpoints to inform host of powerstate change• Beacon• In-band mechanism used by PCIe devices toinform host of power state change• VAUX• Auxiliary voltage supply for Beacon internal circuit‣ VAUX/WAKE#/Beacon support• WAKE# - Input Signal to Switch• Switch generates in-band Beacon sequenceto host when WAKE# is active© PLX Feb 2008 54

VAUX/WAKE#/BeaconWAKE#/Beacon Supportpresent in SwitchWAKE#/Beacon Supportnot present in SwitchCPUCPUChipsetChipsetWAKE#I/OBeaconI/OI/OSwitchSwitchVAUXSwitchI/OI/OI/OWAKE#© PLX Feb 2008 55

Reliability & Serviceability‣ Performance Monitoring• Allows users to monitor device and system performance ona per port basis:• TLP throughput & Queue depths• Blocking, stalling, over-subscription detection‣ Internal Testability Features• JTAG support• BIST for internal memories• Lane/Port status indicators‣ Debug Features• PRBS generator for bit error rate characterization• SerDes loopback mode (four levels)• Error Injection© PLX Feb 2008 56

Additional Key Features of PLX Gen 1‣ Quality of Service• Up to Two Virtual Channels‣ Lane and polarity reversal supported on all ports‣ Up to 32 General Purpose Output Pins‣ FATAL_ERR# and INTA# support‣ Error Handler• PCI Express Advanced error reporting• Poison-bit & end-to-end CRC‣ Industrial Temp Support‣ SerDes power control• Off, low, typical and high• Turn off unused SerDes blocks© PLX Feb 2008 57

New Features forPCIe Gen 2 SwitchesInnovation = PLX AdvantageAll Available TODAY!© PLX Feb 200858

Gen 2 Leveraged PLX Experience‣ PLX leveraged its experience and leadership to bringits new Gen 2 Product Line to Market• Higher Performance• Lower Power Consumption• Innovative New Features• Backward Compatible to Gen 1‣ Used a field-proven best in class3 rd Generation Architecture as base• Highest Performance/Lowest Power in Industry• Scaled up to Gen 2‣ Used Gen 2 SerDes IP from Market Leader (ARM)‣ PLX Gen 2 Switches are Shipping Worldwide© PLX Feb 2008 59

Best in Class Performance‣ PLX continues to raise the bar on performance‣ Staying ahead of the curve• Anticipating customer needs & pushing theenvelope• Innovative new features• Read Pacing• Dual Cast• Dynamic Buffer Allocation‣ Improved upon industry-leading Gen 1 architecture• Increased Max Payload Size to 2KB• Enhanced internal data paths‣ Gen 2 architecture achieves >99% of theoretical throughput!© PLX Feb 2008 60

PEX 8600 Performance‣ PLX setting the tone for Gen 2 Performance‣ Achieving >99% theoretical max throughputin Host-Centric and Peer-to-Peer environments‣ Proven in simulations & actual measurementsStay ahead of the pack with PLX!‣ Innovative new features• Read Pacing• Dual Cast• Dynamic Buffer Allocation© PLX Feb 2008 61

PLX Anticipating Customer Needs‣ Customers using a mix of constant & bursty traffic• Causing inefficient system performance PLX Solution: Read Pacing‣ Customer systems backing up data on secondaryendpoints and/or have two endpoints process same data• Dual Copying bogging down system bandwidth PLX Solution: Dual Cast‣ Unpredictable and asymmetric traffic patterns causinginefficient use of buffers• Lower performance due to inefficient buffer use PLX Solution: Dynamic Buffer Allocation© PLX Feb 2008 62

Exclusive Gen 2 Performance Features‣ Read Pacing• Optimize system performance by fairly allocating ReadRequest bandwidth to all endpoints• Performance increase of 10x to >100x versus other solutions!• Performance increase will vary based on system setup‣ Dual Cast• Double your Posted Write performance by copying data totwo destination (egress) ports• Remove burden from Root Complex‣ Dynamic Buffer Allocation• Customize buffers to optimize your system performance• Fully programmable buffers© PLX Feb 2008 63

Read Pacing*‣ Problem Reduced endpoint performance caused by:• Unbalanced upstream/downstream link-widths• Uneven number of Read Requests made by endpoints• Leads to one endpoint dominating Root Complex queue• Other endpoints get starved‣ Solution PLX Read Pacing*• Read Pacing Queues manage incoming Read Requests• Prevents one endpoint from dominating Root Complex queue• Ensures no endpoint is starved• Allows for optimized performance of endpoints* Patents pending© PLX Feb 2008 64

Dual Cast Feature Relieves CPUSwitch‣ Exclusive feature from PLX‣ Allows forwarding of one ingress packet to two egress ports• Posted transactions only (Memory Writes)• Forward ingress packet to any 2 user selectable ports• ACKs have to be received for both copies• 8 BARs available‣ Useful for different applications• Storage Systems (Redundancy)• Dual Host (High Availability) Systems• Traffic monitoring‣ Increases CPU performance!• Relieves CPU from dual writes of same data© PLX Feb 2008 65

Dual Host Usage Model‣ Dual Host (High Availability) Systems• Dual Cast used to copy data from System A to System B (and vice versa)• Dual Cast can be used in conjunction with an NT portSystem ASystem BProcessor(Primary)Processor(Backup)Root ComplexRoot ComplexPEX 8632NTNTPEX 8632x4 & x8x4 & x8© PLX Feb 2008 66

Dual Cast - Fibre Channel HBA‣ Redundant Storage Array• Switch uses Dual Cast to store data on two RAIDs• Same card can be used for non-redundant applicationsFCFC Cont.PHYASICx4FCFC Cont.PHYASICx4PEX 8612x4Fibre Channel HBA© PLX Feb 2008 67

PLX PEX 8600 Buffer Allocation‣ Shared memory pool per 16 lanesPLX Buffer Allocationx4‣ User assigns buffers as per port-width• Set minimum buffers per ports• Also creates a common pool‣ Ports dynamically grab buffers as needed• Grab when assigned buffers are full• Return empty buffers to the poolAssignedBuffersCommonBufferPoolAssignedBuffersx4x2x2© PLX Feb 2008 68

Best in Class Gen 2 SerDes‣ Best in class SerDes from ARM‣ Programmable• Transition amplitude and Non-transitional amplitude• Pre-emphasis, De-emphasis and drive strength granularity to 50mV• Receiver Detect and Electrical Idle bits‣ SerDes BIST and AC JTAG‣ Automatic impedance calibrationNon-Transitional EyeTransitional Eye© PLX Feb 2008 69

Gen 2 Switch in Gen 1 System‣ PLX Gen 2 Switches can be used in any Gen 1 System• Switch automatically operates in Gen 1 modeif placed in a Gen 1 System• PLX encourages move to Gen 2 Switch‣ Applications can take advantageof the great new features andperformance in a Gen 1 System• Read Pacing• Dual Cast• Smaller Package Size• Enhanced Power Management• Lower PowerG1G1 Gen 2SwitchGen 2 Switchoperates as Gen 1Switch if used isGen 1 systemG1‣ Lower Cost SolutionG1G1© PLX Feb 2008 70

Gen 2 Switch in Mixed Gen 1 & 2 System‣ PLX Gen 2 Switches can be used in anyMixed Gen 1 & Gen 2 System• Switch ports automatically adjust to Gen 1 or Gen 2depending on attached device to particular port‣ Switch will “bridge”:• from Gen 2 to Gen 1• from Gen 1 to Gen 2G1G2G2SwitchG2G1 Gen 2SwitchGen 1 to “Bridge” to Gen 2G2G2G1© PLX Feb 2008 71

Gen 2 Switch in Mixed Gen 1 & 2 SystemCPUCPUChip Set(Gen2)MemoryChip Set(Gen1)Memoryx16x8x16x16Gen 2Gen 2x4 & x8 Gen 1 slotsx4 & x8 Gen 1/2 slotsGraphics SlotGraphics SlotEndPointEndPointGen 2 to Gen 1 Gen 1 to Gen 2© PLX Feb 2008 72

PCI Express SwitchesDevice InformationFor Products AVAILABLE TODAYPCIe Gen 1 (2.5GT/s) & Gen 2 (5.0GT/s)© PLX Feb 200873

‣ PEX 854848 Lane Switches• Industry’s lowest latency switch• Servers, ATCA Blades, Fan-out, Peer-to-Peer Communication, Graphics‣ PEX 8648• Highest Lane & Port Count Gen 2 Switch in Market• Adds Non-Transparent Port, Dual Cast, Read Pacing and Debug FeaturesFeature PEX 8548 PEX 8648Lanes 48 48Ports 9 12PCIe speed Gen 1 (2.5GT/s) Gen 2 (5GT/s)Latency 110ns (x16 to x16) 140ns (x16 to x16)Non-Transparency No YesRead Pacing No YesDual Cast No YesHot-Plug Ports 3 3 with HPC Signals, 9 through I 2 CMaximum Payload Size 1 KB 2KBAvailability In Production NowPackage 37.5 x 37.5 mm 2 27 x 27 mm 2 flip-chipTypical Power 4.9 W 4.0 W© PLX Feb 2008 74

48 Lane Port Configurations – Gen 2x4sx4x4sx16PEX 8648x4sx16x8x8x16x8PEX 8648PEX 8648PEX 8648PEX 8648x4sx8sx4sx4sx8x8x8x8x8x8x8x8x4sx8x4sx4sPEX 8648PEX 8648PEX 8648PEX 8648x8x8x8x4sx4sx4s‣ Many other configurations possible‣ Ports will auto-negotiate down© PLX Feb 2008 75

48 Lane Port Configurations – Gen 1x8x8PEX 8548x8x8x16PEX 8548PEX 8548x8x4x8PEX 8548x8x4x8x16PEX 8548x16x4 x4 x4 x4x16x16x4 x4 x4 x4x4x4x8x8PEX 8548x8x8x8PEX 8548x8x8x8x16PEX 8548x8x8x16PEX 8548x8x8x8x8x4x4 x8x4 x4 x4 x4x4x8x4‣ Many other configurations possible‣ Ports will auto-negotiate down© PLX Feb 2008 76

Bladed Switch FabricCPU Blade2 I/O BladesCPUCPU14 CPU BladesRootComplexPEX 8508NTPEX 8548PEX 8548© PLX Feb 2008 77

ATCA & MicroTCA Backplanes10-20 AMC or 10 AMC Carrier Modules FabricToBackplanePEX 8648CPUNTPEX 8648To otherFabric© PLX Feb 2008 78

48 Lane Dual-Graphics Switches‣ Application Specific Switches• Dual Graphics• Dual x16 Slot Creation on MotherboardFeature PEX 8547Lanes 48Ports 3PCIe speedGen 1 (2.5GT/s)Latency 110ns (x16 to x16)Dual CastNoHot-Plug Ports 0Max. Payload Size 1 KBAvailabilityIn ProductionPackage 37.5 x 37.5 mm 2Typical Power4.9 WPEX 8547x16x16x16© PLX Feb 2008 79

PEX 8547 Dual Graphics UsageCPUCPURootComplexRootComplexx16x16PEX 8547PEX 8547x16x16x16x16GPU1GPU2GPU1GPU2© PLX Feb 2008 80

32 Lane Switches‣ PEX 8533• Performance optimized switch with industry’s lowest latency - 115ns• Servers, Storage, Graphics, Fan-Out, Peer-to-Peer Communication‣ PEX 8632• Adds new Gen 2 Features and Non-Transparency• Smaller package, increases to 12 ports, Lower PowerFeature PEX 8533 PEX 8632Lanes 32 32Ports 6 12PCIe speed Gen 1 (2.5GT/s) Gen 2 (5GT/s)Latency 115ns (x8 to x8) 145ns (x8 to x8)Non-Transparency No YesRead Pacing No YesDual Cast No YesHot-Plug Ports 3 3 with HPC Signals, 9 through I 2 CMax. Payload Size 1 KB 2 KBAvailability In Production NowPackage 35 x 35 mm 2 27 x 27 mm 2 flip-chipTypical Power 3.3 W 2.8 W© PLX Feb 2008 81

32 Lane Port Configurations – Gen 212 port mode 8 port modex4sx4PEX 8632x2sx4x4PEX 8632x4x16PEX 8632x16PEX 8632x2sx4sx8sx4sx4sx8x2sx8x8x8x8x8x8PEX 8632PEX 8632PEX 8632PEX 8632x2sx4sx4sx4s‣ Industries only 32-lane device with 12 ports• x2 ports can not be combined to wider ports in 12 port mode‣ Other configurations possible, ports will auto-negotiate down© PLX Feb 2008 82

32 Lane Port Configurations – Gen 1PEX 8532PEX 8533x4x4PEX 8532x4 x4 x4 x4x4x4x8x16PEX 8532x8x8x8PEX 8533x4x4x4x4x8x16PEX 8533x8x8x8x8x8x8PEX 8532x8x8PEX 8532PEX 8533PEX 8533x4x4x4 x4 x4 x4x8x8x8x4x4x8x8‣ Many other configurations possible‣ Ports will auto-negotiate down© PLX Feb 2008 83

Adding a Gen 2 Slots to Gen 1 SystemCPUChip Set(Gen1)Memoryx8Gen 1 from Legacy Chip Setor DevicePEX 8632EndPointCan CreateGen 2 SlotsAll Gen 2 ports work automatically in Gen 1 mode© PLX Feb 2008 84

24 Lane Switches‣ PEX 8525• Performance optimized switch with industry’s lowest latency - 115ns• Servers, Storage, Graphics, Peer-to-Peer Communication‣ PEX 8624• Gen 2 Features, 6 ports, & Non-Transparent Port• Smallest 24 Lane Package at 19x19mmFeature PEX 8525 PEX 8624Lanes 24 24Ports 5 6PCIe speed Gen 1 (2.5GT/s) Gen 2 (5GT/s)Latency 115ns (x8 to x8) 145ns (x8 to x8)Non-Transparency No YesRead Pacing No YesDual Cast No YesHot-Plug Ports 3 3 with HPC Signals, 3 through I 2 CMaximum Payload Size 1 KB 2 KBAvailability In Production NowPackage 31 x 31 mm 2 19 x 19 mm 2 flip-chipTypical Power 2.6 W 3.0 W© PLX Feb 2008 85

24 Lane Port Configurations – Gen 2x4PEX 8624x8x4x4PEX 8624PEX 8624x4x4x4x8x8x8x8x4x4PEX 8624PEX 8624x4x4x4x4x8‣ Many other configurations possible‣ Ports will auto-negotiate down© PLX Feb 2008 86

24 Lane Port Configurations – Gen 1x8PEX 8525x8PEX 8525PEX 8525x4x4x4x4x8x8x8x4PEX 8525PEX 8525x8x4x4x4x4x4x4‣ Many other configurations possible‣ Ports will auto-negotiate down© PLX Feb 2008 87

Fail-Over System with Dual CastProcessor AProcessor BProcessorProcessor(Primary)(Backup)Root Complexx8Root Complexx8PEX 8624*SwitchNTx4PEX 8624*NT Switchx4x4 x4x4 x4 x4*8632 and 8648 may also be utilized© PLX Feb 2008 88

Create Gen 2 Cards from Gen 1 Silicon‣ Leverage Investmentin Gen 1 throughBridging• Build Gen 2 NICs withGen1 ASIC/ASSPs10 GE10 GEMAC/PHYMAC/PHYGen 1 x8Gen 1 x8Gen 2 x8PEX 8624• Build Gen 2 HBAs withGen1 ASIC/ASSPs forFCFC Cont.Gen 1 x8FCFC Cont.Gen 1 x8PEX 8624Gen 2 x8© PLX Feb 2008 89

16 Lane Switches‣ PEX 8518• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon• Redundant Systems, Fan-Out, Servers, HBAs, NICs, Mezzanine cards‣ PEX 8616• Adds Gen 2 Features & Smaller Package• Lower Power & Larger PayloadFeature PEX 8518 PEX 8616Lanes 16 16Ports 5 4PCIe speed Gen 1 (2.5GT/s) Gen 2 (5.0GT/s)Latency 150ns (x4 to x4) 150ns (x4 to x4)Non-Transparency Yes YesRead Pacing No YesDual Cast No YesHot-Plug Ports 5 2 with HPC Signals, 2 through I 2 CMaximum Payload Size 256 B 2 KBAvailability In Production NowPackage 23 x 23 mm 2 19 x 19 mm 2 flip-chipTypical Power 2.6 W 2.2 W© PLX Feb 2008 90

16 Lane Port ConfigurationsPEX 8518PEX 8616x4x8x4x8PEX 8518PEX 8518PEX 8616PEX 8616x4x4 x4x4x2x2x4x4x4x4x4x4x8x4x4PEX 8518PEX 8518PEX 8616PEX 8616x4 x4 x2 x2x2 x2 x2 x2x4x2x2x4x4x2‣ Many other configurations possible‣ Higher lane-width port will auto-negotiate down© PLX Feb 2008 91

Multi-Function Printers (MFP)CPUMPC7449MemoryChipsetMV64560x4HDDx4PEX 8518x4ASICx4Image Processing – 2OptionalASICImage Processing - 1© PLX Feb 2008 92

Server NIC‣ 10 Gig Ethernet NIC• Two to Four 10 GEports aggregated• All ports on the switchare transparent• Can be duplicated inAMC form factor10 GE10 GE10 GEMAC/PHYMAC/PHYMAC/PHY444PEX 8616*410 GEMAC/PHY410 GEMAC/PHY4PEX 86168* PEX 8624 can be used for wider up-stream port© PLX Feb 2008 93

12 Lane Switch‣ PEX 8512• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon• HBAs, NICs, AMC/XMC plug-in cards, Redundant Systems, Host Isolation‣ PEX 8612• Adds Gen 2 Features• Smaller Package & Lower PowerFeature PEX 8512 PEX 8612Lanes 12 12Ports 5 3PCIe speed Gen 1 (2.5GT/s) Gen 2 (5.0GT/s)Latency 150ns (x4 to x4) 150ns (x4 to x4)Non-Transparency Yes YesRead Pacing No YesDual Cast No YesHot-Plug Ports 3 2 with HPC Signals, 1 through I 2 CMaximum Payload Size 256 B 2 KBAvailability In Production NowPackage 23 x23 mm 2 19 x 19 mm 2 flip-chipTypical Power 2.2 W 2.0 W© PLX Feb 2008 94

12 Lane Port ConfigurationsPEX 8512PEX 8612x4x4x4PEX 8512PEX 8512PEX 8612x4x4x2 x2 x2 x2x4x4‣ Higher lane-width port will auto-negotiate down© PLX Feb 2008 95

I/O ExpansionCPURootComplexx4x4PEX 8512PEX 8512x2x2x2x2x4x4Dual GEDual GEDual GEDual GEPCI ExpressSlotFC© PLX Feb 2008 96

Intelligent Adapter UsageIntelligentI/O AdaptorI/OCPUNon-TransparentPortNTPEX 8612PrimaryHostCPUBladeSecondaryHostCPUBladeI/OI/OI/ONTPEX 8632© PLX Feb 2008 97

8 Lane Switches‣ PEX 8508• Non-Transparent switch with SSC and Vaux/WAKE#/Beacon• Redundant Systems, Host Isolation, AMC/XMC plug-in cards‣ PEX 8509• Industry’s only 8 lanes & 8 ports PCIe switch• Control Planes, Docking Stations, NICs, High-end PrintersFeature PEX 8508 PEX 8509Lanes 8 8Ports 5 8Latency 150ns 118ns (in x4 to x1 configuration)Non-Transparency Yes NoHot-Plug Ports 5 3Maximum Payload Size 256 B 1 KBAvailability In Production In ProductionPackage 19 x 19 mm 2 15 x 15 mm 2Typical Power 1.6 W 1.2 W© PLX Feb 2008 98

8 Lane Port ConfigurationsPEX 8508PEX 8509x4x4x4x2PEX 8508PEX 8508PEX 8509x2PEX 8509x1 x1 x1 x1x2x2x1x1x1x1x1x1x1x1x4x2x2x1PEX 8508PEX 8508x1PEX 8509x1x1PEX 8509x1x1x2x1x1x2 x2 x2x1x1x1x1x1x1x1x1‣ Many other configurations possible‣ Higher lane-width port will auto-negotiate down© PLX Feb 2008 99

Notebook Docking StationMother BoardCPUGraphicsNorthBridgeMemoryUSB/SATA/GESouthBridge• Low Cost and Power• PCI Expressaggregator• Single lane PCI Expressslots/cardsNetworkEnd PointDocking Station1114PEX 85091EndPoint© PLX Feb 2008 100

Control Planes For Large Systems7 portsTo Line Cards6 portsPEX 8509x1PEX 8509x1ControlProcessorMemoryController CardControl Processor has only one PCIe port© PLX Feb 2008 101

Control Planes For Large Systems7 portsTo Line Cards7 portsPEX 8509PEX 8509x1ControlProcessorMemoryController Cardx1Control Processor has dual PCIe ports (ex: MPC8641D from Freescale)Now there is no bottleneck between the two PEX 8509 devices© PLX Feb 2008 102

PEX 8509 RDK‣ PCI Express Add-in CardForm Factor‣ Four x1 PCI Express SlotsPEX 8509‣ PCI Express Connector: x4© PLX Feb 2008 103

PEX 8509 RDK - Expansion Kitx1x1 PCI Express Cablex1x1Resetx1x1 PCIe Cable Adapter – x1 PCIePassive Host CardClockPowerRDK Port Expander: 4 PCI Expressx1 Slots with external power supply© PLX Feb 2008 104

PEX 8509 RDK and Expansion Kitx1x1x1To PCIe Slot onHost ComputerPEX 8509ResetClockPower‣ Eight x1 PCI Express Slots• Four on PEX 8509 RDK• Four on expansion board© PLX Feb 2008 105

5 Lane Switch‣ PEX 8505• 5 lanes & 5 ports PCIe switch• Control Planes, Docking Stations, I/O expansion in PCs, High-endPrinters, Consumer Electronic SystemsFeature PEX 8505Lanes 5Ports 5Latency138ns (in x2 to x1 configuration)Non-TransparencyNoHot-Plug Ports 3Maximum Payload Size1 KBAvailabilityIn ProductionPackage 15 x 15 mm 2Typical Power0.8 W© PLX Feb 2008 106

5 Lane Port Configurationsx1PEX 8505x2x2PEX 8505PEX 8505PEX 8505x1 x1 x1 x1x1x1x1x2x1x1x2x1PEX 8505PEX 8505PEX 8505x1x1x1x1x1x1x1‣ Higher lane-width port will auto-negotiate down© PLX Feb 2008 107

On-Board Control PlaneASICFPGAFPGAPEX 8505ControlProcessorMemoryASIC© PLX Feb 2008 108

I/O Expansion in PCsSouthBridgeEnd PointPEX 8505StereoCODECVIA17242PCIe Sound CardPCIBusPEX 8112PCIe TV Tuner CardPhilipsHybridTunerCVBS2IFConexantCX23882PCIBusIFConexantDemodCX22702TSPEX 8112© PLX Feb 2008 109

PEX 8505 RDKx1x1x1To PCIe Slot onHost ComputerPEX 8505ResetClockPower‣ Five x1 PCI Express Slots• One on PEX 8505 RDK• Four on expansion board© PLX Feb 2008 110

Gen 1 vs. Gen 2 ElectricalCategory48 Lanes32 Lanes24 Lanes16 Lanes12 LanesDevicePackage Size*(mm 2 )Typical PowerConsumption(Gen 1 Mode)Max. PowerConsumption(Gen 1 Mode)SmallerPackageLowerPowerPEX 8648 27 x 27 mm 2 3.3 W** 6.2 W** PEX 8548 37.5 x 37.5 mm 2 4.9 W 7.1 WPEX 8632 27 x 27 mm 2 2.3 W** 4.2 W** PEX 8533 35 x 35 mm 2 3.3 W 4.8 WPEX 8624 19 x 19 mm 2 2.6 W** 4.4 W** PEX 8525 31 x 31 mm 2 2.6 W 3.8 W PEX 8616 19 x 19 mm 2 2.0 W** 3.2 W** PEX 8518 23 x 23 mm 2 2.6 W 3.6 WPEX 8612 19 x 19 mm 2 1.8 W** 2.9 W** PEX 8512 23 x 23 mm 2 2.2 W 3.1 W* All Flip-Chip, 1.0mm Pitch** Preliminary EstimatesTypical: 35% lane utilization, typical voltages 25C° ambient. L0s modeMaximum: 85% lane utilization, L0 mode, max operating voltagesPLX encourages new designs to use Gen 2 parts even if only Gen 1 needed.© PLX Feb 2008 111

PLX Provides Complete Solutions‣ Silicon (switch and bridge products)‣ Rapid Development Kit (RDK)• Software Development Kit (SDK)• Hardware Module‣ Package Spice Models‣ Other tools• Design guide, design check-list, HW design guide• BSDL files, OrCAD Symbols• Package thermal models‣ Excellent customer support through regional FAEs© PLX Feb 2008 112

PCIe Gen 2 SwitchUsage Models© PLX Feb 2008 113

Server Fan-outCPUChip SetMemoryx4x8EndPointPEX 8624x4sEndPoint© PLX Feb 2008 114

Server Fan-outCPUGen 1Chip SetMemoryEndPointx4x16PEX 8648EndPointx4sx4sGen 2 SlotsGen 2 EndpointsEndPoint© PLX Feb 2008 115

Server Fan-outCPUGen 2Chip SetMemoryEndPointx4x8PEX 8648EndPointx8sx4sGen 2 SlotsGen 1 EndpointsEndPoint© PLX Feb 2008 116

Workstation Fan-outCPUCPUCPUCPUChip SetMemoryx4x16PEX 8616*EndPoint*May use 12 to 32 lane switches© PLX Feb 2008 117

Imaging Workstation Fan-outCPUCPUCPUCPUChip SetMemoryx4x16PEX 8616*GPUEndPoint*May use 12 to 32 lane switchesPEX 8547PEX 8547GPUGPUGPU© PLX Feb 2008 118

Compute Cluster/SupercomputerCPU CPUMemChip SetNICUPMemCPU CPUChip SetNICUPUPNTPEX 8616NTPEX 8616DSDSNTPEX 8632CPU CPUPass thru EthernetMemChip SetNICCPU CPUMemChip SetNIC© PLX Feb 2008 119

Servers Fan-out – RISC BasedRISCProcessorMemoryx8PEX 8648or PEX 8632x8 & x4EndPoint© PLX Feb 2008 120

Router UsageControlModulePowerPCMemoryEndPointEndPointx8 or x4PEX 8648or PEX 8632EndPointEndPointLine CardEndPointEndPoint© PLX Feb 2008 121

Redundant Blade System Fan-outCPUCPUCPUCPUCPU CPUCPU CPUChip SetMemoryChip SetMemoryx8x8PEX 8624PEX 8624all x4sall x4sNTNTNTNTPEX 8612PEX 8612PEX 8612PEX 8612EndPointEndPointEndPointRedundant LinksEndPoint© PLX Feb 2008 122

Host Bus Adapters (HBAs)‣ 16-Lane aggregation• Switch used as an aggregator10G FC ControllersFCFC ContFibre Channel HBAx4‣ Multi-Port Fibre Channel CardFCFC Contx4PEX 8612x4FCFCFC ContFC ContFibre Channel HBAx4x4PEX 8616*x4FCFCFCFC ContFC ContFC ContFibre Channel HBAx4x4x4 PEX 8616*x4© PLX Feb 2008 123

Backplane or Fabric UsageI/O BladesFabricPEX 8648 PEX 8648Redundant Fabric Cards© PLX Feb 2008 124

Gen 2 - In Summary...‣ Broad selection of PLX PCIe switches and bridges• Shipping 13 Gen 1 switches, four Gen 1 bridges• Shipped over $50M and 2 million chips in PCI Express switches andbridges• Shipping to industry leaders in all segments‣ PLX offering a complete solution with silicon, RDKs, development tools,documentation and excellent customer support‣ PLX leveraging success into Gen 2 products• Introduced five new Gen 2 switches• Ranging from 12 to 48 lanes and up to 12 ports• Devices shipping to customers worldwide• Using robust and field-tested architecture• Exclusive features and leading performance‣ PLX remains 100% focused on PCIe and will continue to dominate thePCIe market© PLX Feb 2008 125

PLX PCI Express BridgesDetailed Product Section© PLX Feb 2008126

What is a PCIe Bridge?‣ A PCIe Bridge connects a PCIe device to a different I/O type• Provides spec-compliant connection between devices withdifferent I/O standards‣ PLX PCIe Bridges provide the Proven Connection• Rigorous Interoperability Testing on each device• 100’s of chipset, motherboard, BIOS and cards tested in PLX labs• PCI SIG Certified for Spec Compliance on SIG Integrator’s ListLocalBusBridge© PLX Feb 2008 127

Why Use a PCIe Bridge?PCIDeviceCreate PCIe Add-in Cardsusing PCI-nativeTargets or MastersCreate PCI Add-in Cardsusing PCIe-native endpointsBridgePCIeEndpointBridgeSRAMEEPROMFPGA4 New PCI SlotsLocalCPULocalBusBridgeHostCPUBridgeRootComplexMigrate legacy local bus devices overto next generation PCIeCreate PCI Slots on PCIe System Board© PLX Feb 2008 128

Key Bridge Features‣ PCIe Side• Interoperates withany PCIe device• PCIe compliant• Fully IntegratedSERDES• 2.5 GHz PHY• Large FIFO andCredit Control• Integrated Hot-Plug Controller‣ PCI Side• Interoperates withany PCI deviceBridge• PCI compliant• 5V tolerant I/O• 32/64 bit‣ Local Bus Side• 33-133 MHz• Interoperates with• Built in PCI arbiterany Local Bus device• 8/16/32 bit• Up to 66 MHz• 2 DMA channelsLocalBus© PLX Feb 2008 129

Defining “Forward” and “Reverse” ModesPCIe HostorRoot ComplexPrimaryPCIHostPrimary BusBridgeSecondary BusBridgeSecondaryForward BridgingReverse Bridging© PLX Feb 2008 130

PLX Bridges – The Proven Connection‣ Why Interoperability Is Important:• in·ter·op·er·a·bil·i·ty [in-ter-op-er-uh-bil -i -ty] , noun• The ability of software and hardware on multiple machinesfrom multiple vendors to communicate.The Free On-line Dictionary of Computing, © 1993-2007 Denis Howe• No surprises in the field• Access to broader market‣ PLX is the Interoperability Leader in PCIe Bridges• Tested with over 25 motherboards and add-in cards• All PLX PCIe Bridges on PCI SIG Integrator’s List• Designed-in with over 100 customers since 2005© PLX Feb 2008 131

PLX Bridge UsersRS232 CardSCSI CardUSB CardVideo EditorGraphics CardAMCDVR / TVWorkstation System BoardBase StationRiser CardServer System BoardATCA ChassisAudio CardTV Tuner© PLX Feb 2008 132

PLX Bridges – Interop Testing‣ Phase 1: Motherboards + System BIOS Testing‣ Phase 2: Endpoints Testing‣ Phase 3: Chip-to-chip Interoperability and WHQLCertification‣ Phase 4: Microsoft / Linux Operating Systems© PLX Feb 2008 133

PLX Interop Phase 1 – Motherboard/BIOS‣ 26 different motherboard/chipsets:• MSI, Intel, Nvidia, Supermicro, ABIT, ULI,WinFAST, Dell, AMD, ASUS, Gigabyte, HP‣ 25 different BIOS loads• Phoenix, Award, AMI, Dell, Intel© PLX Feb 2008 134

PLX Interop Phase 2 - Endpoints‣ 16 different graphics cards• ATI, Nvidia, Matrox, 3d, Kaser, Mad Dog, …‣ 6 different Ethernet cards• HP, Broadcom, Sysconnect, D-Link, Intel, …‣ 6 different storage controllers• QLogic, Emulex, LSI Logic, SIIG, …‣ 3 different TV tuners• Hauppauge, Lifeview, …PCI Express EndpointRS232 Card© PLX Feb 2008 135

PLX Interop Phase 3‣ Chip-to-chip Interoperability• Tests multiple bridges and switches‣ WHQL Certification• Microsoft WHQL certification on selected graphics cards© PLX Feb 2008 136

PLX Interop Phase 4 – Microsoft OS‣ Microsoft Operating Systems:• Windows XP Professional• Windows Server 2003• Windows Server x64 for 2003• Windows Vista© PLX Feb 2008 137

PLX Interop Phase 4 – Linux OS‣ Linux Support© PLX Feb 2008 138

Compliance‣ Benefits of Specification Compliance• Insures interoperability• PCI-SIG• PICMG• Listed on the Integrator’s List• Access to broader market© PLX Feb 2008 139

Fully Integrated SerDes‣ Less board space‣ Lower cost‣ Lower power dissipation‣ Enhanced signal integrity‣ Easier to designFPGASerDesBridge© PLX Feb 2008 140

Large FIFO and Credit Control‣ Improved data throughput‣ Traffic prioritization and optimization• Ability to control specific credit allocation between postedand non-posted transaction‣ Prefetching capability to lower the overhead and burstdata‣ Multiple transaction parallel processing© PLX Feb 2008 141

Integrated Hot-Plug Controller‣ Less board space‣ Lower costCPUChip SetMemoryMRL#CPUATTNLED#PWRLED#BridgePWREN#PowerControllerChip SetMemoryPWRFLT#BUTTON#REFCLKEN#CLK GENI2C or FGPA SignalsBridgePRSNT# PERST# REFCLKp REFCLKnPOWERBUTTON#FPGA/PLD orIO ExpanderPWREN#PWRFLT#MRL#PowerControllerPWRLEDPCI Express ConnectorAttentionButtonManualRetentionLatchATTNLED#PWRLED#PRSNT#REFCLKEN#PERST#REFCLKpCLK GENREFCLKnPOWER‣ Lower power dissipation‣ Easier to designPCI Express ConnectorAttentionButton© PLX Feb 2008 142

PCIe Bridge Summary‣ PLX Bridges Feature Proven Connectivity• Ensured by design of flexible I/O interfaces• Ensured by Interoperability Testing• Demonstrated in PCI-SIG Compliance• …and in hundreds of systems worldwide‣ Smallest Packages‣ PLX is First-to-Market with Reverse Bridging‣ Lower Power Dissipation• No heat sink required• Reduces cost of power supplies• Reduces amount of heat generated© PLX Feb 2008 143

PCIe BridgeDetailed Product Section© PLX Feb 2008144

Bridge Road Map - PCI, PCI-X, PCIePCI/PCI-XBus Speeds64 Bits133 MHz64 Bits66 MHzPCI 6254Non-TransparentAsynchronousPCI 6154Asynchronous31x31 mm 2 304 PBGAPCI 6466Non-TransparentAsynchronousPCI 6540PCI-X Non-TransparentAsynchronousPCI 6520PCI-X Asynchronous27x27 mm 2 380 PBGAPEX 811464-Bit 133MHz PCI-Xto x4 PCIe• Forward & Reverse Mode• Small 17x17mm Package• No Heat Sink Required32 Bits66MHz32 Bits33MHzPCI 6150High PerformanceAsynchronousPCI 6152Smallest Footprint15x15 mm 2 160 TBGAPCI 6140Lowest Power(200mW)Shipping NowIn DevelopmentPlanned/ConceptPEX 811132-Bit 66MHz PCIto x1 PCIe• Forward & Reverse Mode• Small 10x10 & 13x13mm Package• No Heat Sink RequiredPEX 8112Cost Reductions &Enhancements2003 & Before20042005 2007© PLX Feb 2008 145

ExpressLane PCI Express Bridges‣ PEX 8111 / PEX 8112 PCI to PCI Express• 32-Bit PCI (up to 66 MHz)• x1 PCIe‣ PEX 8114 - PCI-X to PCI Express• 64-Bit PCI-X (up to 133 MHz)• x4 PCIe‣ PEX 8311 - Generic Local to PCI Express• 32-Bit Local (up to 66 MHz)• x1 PCIe‣ In Production TODAY!© PLX Feb 2008 146

PEX 8112 Overview‣ Proven Interoperability• Exhaustive Testing at PLX InteropLabs• Proven interface for broad range ofdevices and endpoints• PCI 32-Bit 33MHz to 66 MHz‣ Forward or Reverse Bridging‣ In Production NOWPEX 8112PCI 32-bit, 66 MHz© PLX Feb 2008 147

PEX 8111 / PEX 8112 Part NumbersOrdering NumbersPackagePEX 8111-BB66BCPEX 8111-BB66BC FPEX 8111-BB66FBC FPEX 8112-AA66BIPEX 8112-AA66BI FPEX 8112-AA66FBI FOrdering NumbersPEX 8112RDK-FPEX 8112RDK-RStandard PitchBGA 13 x 13 mm 2Lead-Free, Standard PitchBGA 13 x 13 mm 2Lead-Free, Fine PitchBGA 10 x 10 mm 2Standard PitchBGA 13 x 13 mm 2Lead-Free, Standard PitchBGA 13 x 13 mm 2Lead-Free, Fine PitchBGA 10 x 10 mm 2DescriptionPEX 8112 Forward BridgeRapid Development KitPEX 8112 Reverse BridgeRapid Development Kit© PLX Feb 2008 148

PEX 8114 Overview‣ Proven Interoperability• Exhaustive Testing at PLX Interop Labs• Designed for broad range of I/O types• Configurable to x4, x2, or x1• PCI or PCI-X Bus – 32/64-Bit up to 133 MHz‣ Supports Forward or Reverse BridgingPEX 8114‣ In Production Since 2005© PLX Feb 2008 149

PEX 8114 Part NumbersOrdering NumbersPackagePEX 8114-BC13BIPEX 8114-BC13BI GPEX 8114-BD13BIPEX 8114-BD13BI GStandard PitchBGA 17 x 17 mm 2Green, Standard PitchBGA 17 x 17 mm 2Standard PitchBGA 17 x 17 mm 2Green, Standard PitchBGA 17 x 17 mm 2Ordering NumbersPEX 8114RDK-FPEX 8114RDK-RDescriptionPEX 8114 Forward BridgeRapid Development KitPEX 8114 Reverse BridgeRapid Development Kit© PLX Feb 2008 150

PEX 8311 Overview‣ Generic Local Bus to PCI Express Bridge‣ Generic Local Bus• 32-Bit, Up to 66 MHz• Non-Multiplexed (C-Mode) & Multiplex (J-Mode) address/data• Big Endian (M-mode)• 2 DMA Channels• Register Backward compatible withPLX PCI 9056, 9656 & 9054• Local Bus protocol backward compatible withPLX PCI 9056 & 9656 up to 66 MHz‣ PCI Express• x1 Lane PCIe• Integrated SerDes‣ In Production Since March 2006!PEX 831132-bit / 66 MHzLocal Bus© PLX Feb 2008 151

PEX 8311 Part NumbersOrdering NumbersPackagePEX 8311-AA66BC FStandard PitchBGA 21 x 21 mm 2Ordering NumbersPEX 8311RDKDescriptionPEX 8311Rapid Development Kit© PLX Feb 2008 152

End of PresentationThank Youwww.plxtech.com© PLX Feb 2008153