CISC Processor Design - SERC - Indian Institute of Science

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InstructiontiADD R1, D2(B2)‘5A’ R1 B2 D20 8 12 16 31The second operand is added in the firstThe sum is placed in the first operand locationThe operand and the sum are treated as 16-bit signed binary integersThe first operand is in the register specified by the R1 fieldThe second operand is in the memory – address is calculated by addingthe displacement specified by the D2 field to the content of the baseregister specified by the B2 fieldAdvance Computer Architecture 10ComputerDesignLaboratory&Tes
Execution StepsSteps for ADD instruction Execution1. Fetch the first half word2. Find ADD control word sequence3. Fetch the remaining instruction word4. Calculate the operand address5. Fetch the operand6. Add7. Store the resultAdvance Computer Architecture 11ComputerDesignLaboratory&Tes
Page 1 and 2: CISC Processor DesignVirendra Singh
Page 3 and 4: Processor ArchitecturePIControllerC
Page 5: Instruction ti SetInstruction Forma
Page 12 and 13: Execution Steps1. Fetch the remaini
Page 14 and 15: Execution Steps1. Update the progra
Page 16: Thank YouAdvance Computer Architect

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