CISC Processor Design - SERC - Indian Institute of Science

CISC Processor DesignVirendra SinghIndian Institute of ScienceBangalorevirendra@computer.orgComputerDesignLaboratory&TestAdvance Computer Architecture1

Processor ArchitecturetProcessor Architecture• CISC• RISCAdvance Computer Architecture 2ComputerDesignLaboratory&Tes

Processor ArchitecturePIControllerControl SignalsFrommemoryDatapathStatus SignalsPOTo memoryAdvance Computer Architecture 3ComputerDesignLaboratory&Tes

Instruction ti SetInstruction Set Should be complete‣ One should be able to construct t a machine level l program toevaluate any function Should be efficient‣ Frequently required functions can be completed quickly usingrelatively few instructions Should be regular‣ Should contain expected opcodes and addressing modes Compatible with existing i machinesAdvance Computer Architecture 4ComputerDesignLaboratory&Tes

Instruction ti SetInstruction FormatOp-codeOperandsAddressing• Register Specification• Effective Address• Implicit ReferenceAdvance Computer Architecture 5ComputerDesignLaboratory&Tes

Random LogicImplementationClock-Phase GeneratorBus ControllerRandom LogicControllerProgramCounterRegistersR0 R1 Rn Shifter ALUDatapathAdvance Computer Architecture 8ComputerDesignLaboratory&Tes

InstructiontiADD R1, D2(B2)‘5A’ R1 B2 D20 8 12 16 31The second operand is added in the firstThe sum is placed in the first operand locationThe operand and the sum are treated as 16-bit signed binary integersThe first operand is in the register specified by the R1 fieldThe second operand is in the memory – address is calculated by addingthe displacement specified by the D2 field to the content of the baseregister specified by the B2 fieldAdvance Computer Architecture 10ComputerDesignLaboratory&Tes

Execution StepsSteps for ADD instruction Execution1. Fetch the first half word2. Find ADD control word sequence3. Fetch the remaining instruction word4. Calculate the operand address5. Fetch the operand6. Add7. Store the resultAdvance Computer Architecture 11ComputerDesignLaboratory&Tes

Execution Steps1. Fetch the remaining i instruction ti word2. Calculate the operand address3. Fetch the operand4. Add5. Store the result6. Update the program counter7. Fetch the first half word for the next instruction8. Find the address of the next instructions control wordsequence9. Branch to the next instruction’s control wordAdvance Computer Architecture 12ComputerDesignLaboratory&Tes

Execution Steps1. Fetch the remaining instruction word‣ One state to second half of the ADD instruction2. Calculate the operand address‣ One state to add D2 displacement and the content of the B2 register3. Fetch the operand‣ One state to fetch the data half word (put the address on the pads and waitfor the operand half-word)4. Add‣ One state to add the operands5. Store the result‣ One state to store the result in Register R1Advance Computer Architecture 13ComputerDesignLaboratory&Tes

Execution Steps1. Update the program counter‣ One state to increament PC‣ One state to save the incremented value2. Fetch the first half word for the next instruction‣ One state to put the PC value on the pads and wait for the first half of thenext instruction3. Find the address of the next instructions control wordsequence‣ One state to put the next instruction into the instruction decoder4. Branch to the next instruction’s control word‣ Zero state – this step is accomplished as a part of the previous stepAdvance Computer Architecture 14ComputerDesignLaboratory&Tes

Processor - Block DiagramClock-Phase Reset & Power-On LogicGeneratorBus ControllerInterrupt LogicControlStoreNext StateControlBranch ControlunitIRDecoderEncoded Control Word FieldsControl Word DecoderDecoded d Datapath ControlInstructionPrefetchRegisterAddressOut Reg.PC R0 R1Internal A BusRn Shifter ALUInternal B BusDatapathDataReg.Advance Computer Architecture 15ComputerDesignLaboratory&Tes

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