Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST

4. PIN SELECTIONOur recommendation is the following: A deployed SJ BISTapplication should use at least four groups of cores: onegroup of two I/O pins near each corner of the FPGA dieshadow or at each corner of the FPGA package (the pinkshadedpins in Figure 15). Research indicates the solderballs nearest the corner of the package or the FPGA die aremost likely to fail first. The stress diagram in Figure 16indicates that of the two areas, the corners nearest the FPGAdie are likely to fail first. High stress caused by physicalmounting coupled with thermal-mechanical stresses is themost likely cause of the observed failure distribution ofsolder balls in BGA packages. Further evidence of thevalidity of these observations is the reserving of the four I/Opins at each corner for ground and all of the pins under thedie for power and ground (the orange-shaded pins).5. TEST ACTIVITIESExtensive experiments, including HALTs, have beenplanned and are presently being conducted. The primaryobjectives are the following: (1) perform final sensitivity,resolution and clock frequency measurements to verifyFigure 14; (2) collect, evaluate and publish statistical datarelated to test I/O port location, first failure and probabilityof failure distribution. The pink- and light-blue-shaded pinsin Figure 15 are the sixty-four pins we selected for HALTtesting: 32 groups of two-pin SJ BIST cores.HALT Test BoardFigure 16: FG1156 Strain Diagram.Figure 17 is a block diagram of the HALT test board wedesigned. The SJ BIST test program is loaded into aPROM, which then loads the program into each FPGA whenthe board is powered on. Each FPGA generates 640 bits ofdata (64 x (2 faults signals + 8 bits of count)); each boardgenerates 2560 bits of data. We wrote a LabVIEW®program to control the collection of data, and we wrote aMATLAB® program to process the data.Figure 18 shows a manufactured, populated and solderedHALT test board. There are three connectors: (1) XILINXprogrammer connection, (2) power input and (3) experimentcontrol connections.Figure 15: FG1156 I/O Pin Footprint [22].Figure 17: HALT Test Board Block Diagram.6

Figure 18: HALT Experiment Board with Four XILINXFG1156 FPGAs.At the Center for Advanced Vehicle Electronics at AuburnUniversity, Alabama, test boards are placed in a thermaloven (Figure 19) and cycled from -55 o C to 125 o C in 30minute ramps and 15 minute dwells. The boards aresubjected random cyclic shock with variable frequencysuperimposed with random vibrations (Figure 20). A droptest is performed and the test board is placed in the oven for5 days. Data is collected at the beginning of the test andthen twice a day. At the end of 5 days, another drop test isperformed with data collected before and after the drop test.This procedure is repeated for each test board until theboards are damaged.Figure 20: HALT Test Board Mounted on Vibrator.Figure 21 shows the HALT test block diagram: a NationalInstrument (NI) 6541 digital generator is connected to testboard and a CB 2162 connector board to collect the digitaldata. The power board provides 1.2 V, 1.8 V, 2.5 V and 3.0V power to the FPGA test board. Data from the test board isextracted using a platform cable USB.Figure 21: HALT Test Block Diagram.Figure 19: Thermal Oven for Solder Joint HALTTesting – CAVE, Auburn University, Alabama.Independent Test ResultFigure 22 shows a test result from Sindelfingen, Germany,using a known fault of 300 Ω, a 50 MHz clock and a 47 pFcapacitor. The result is actually better than that predicted byFigure 14, which shows for a 10 MHz clock, a 500 pFcapacitor, the fault sensitivity is 300 Ω, and by extrapolationa 100 MHz clock and a 50 pF capacitor should result in afault sensitivity of 300 Ω. The total capacitance is the sumof the external, the parasitic capacitance of the port plus thecapacitance of everything connected to the port, includingthe oscilloscope. Note the display of the digital oscilloscopeindicates a detected frequency of 24.9 MHz, indicating theoscilloscope the lower voltage signals were not included.7

Figure 22: 50 MHz CLK, 47 pF, 300 Ω Fault Test.6. DEMONSTRATION BOXFigure 23 is a picture of one of the SJ BIST demonstrationboxes being tested for delivery to Raytheon MissileSystems. The front panel shows a fault count of 7, apreviously detected fault in an upper-right pin, and both anactive (the fault inject button is depressed) and a previouslydetected fault in a lower-right pin. The purpose of the box isto allow for portable demonstrations, and to allow non-Ridgetop personnel to independently demonstrate andevaluate SJ BIST.Figure 24: SJ BIST Demonstration Box, XILINXSpartan-3 XC3S200FT256 Board.Figure 25 is a picture of the display control board for the SJBIST demonstration board. The board provides theinterface and control between the box front panel and theFPGA. Not shown is a small board upon which the 7-segment LED is mounted. We have since designed,fabricated and assembled a printed wire board to replace thewire-wrapped bread board.Figure 25: SJ BIST Demonstration Box, Display Board.7. SUMMARY AND CONCLUSIONFigure 23: SJ BIST Demonstration Box.An inside view of the demonstration box is shown in Figure24. The FPGA is programmed to test 8 pins; two of the pinsare configured to enable injection of a 100 Ω fault. Asfaults occur, they are summed and displayed. The controlboard supports an ENABLE switch and a RESET switch.In this paper we provided updated information on SJ BIST.A brief overview of the mechanics-of-failure was included:the primary contributor to fatigue damage is thermomechanicalstresses related to coefficient of temperatureexpansion (CTE) mismatches, shock and vibration, andpower on-off sequencing. Solder-joint fatigue damage canresult in fractures that cause intermittent instances of highresistancespikes that are hard-to-diagnose. In reliability8

testing, OPENS (faults) are often characterized by spikes ofa 100Ω or more lasting for less than 100 ns to 1 µs orlonger.Prior to SJ BIST, there were no known methods fordetecting high-resistance faults in solder-joint networksbelonging to the I/O ports of operational, fully-programmedFPGAs.An in-situ SJ BIST to test or monitor selected I/O pins isuseful because stress magnitudes are hard to derive, whichleads to inaccurate life expectancy predictions; and eventhough a particular damaged solder-joint port might notresult in immediate FPGA operational failure, the damageindicates the FPGA is no longer reliable. SJ BIST can alsobe used in newly designed manufacturing reliability tests toinvestigate failure modes related to the PWB-FPGAassembly.8. ACKNOWLEDGEMENTThe foundation work presented in this paper was supportedby Small Business Innovation Research contract awardsfrom the Department of Defense, Naval Air, Joint StrikeFighter program. Final patent applications have been filed:one for SJ BIST technology; one for a related SJ Monitortechnology. U.S. Patent 7,196,294, Mar. 27, 2007, has beenissued for a third related technology.9. REFERENCES[1]. J.P. Hofmeister, P. Lall, D. Goodman, E.O. Ortiz,M.G.P. Adams, and T.A. Tracy, “Intermittency Detectionand Mitigation in Ball Grid Array (BGA) Packages,” paperaccepted for publishing in the proceedings of IEEEAUTOTESTCON 2007, Baltimore, MD, Sep.17-21, 2007.[2]. J.P. Hofmeister, P. Lall and R. Graves, “In-Situ, Real-Time Detector for Faults In Solder Joint NetworksBelonging to Operational, Fully Programmed FieldProgrammable Gate Arrays (FPGAs), IEEE Instrumentationand Measurement Magazine, Aug., 2007, pp. 32-37.[3]. J.P. Hofmeister, P. Lall and Russ Graves, “In-Situ,Real-Time Detector for Faults in Solder Joints Belonging toOperational, Fully Programmed FPGAs,” Proceedings,IEEE AUTOTESTCON 2006, Anaheim, CA, Sep. 18-21,2006, pp-237-243.[4]. Pradeep Lall, Prakriti Choudhary, Sameep Gupte, JeffSuhling, James Hofmeister, Justin Judkins, DouglasGoodman, “Statistical Pattern Recognition and Built-inReliability Test for Feature Extraction and HealthMonitoring of Electronics Under Shock Loads,” 57 th IEEEElectronic Components and Technology Conference, June1, 2007.[5]. James P. Hofmeister, Pradeep Lall, Edgar Ortiz, JeremyRalston-Good, and Douglas Goodman, “Prognostic SolderJoint Sensors for Programmed FPGAs,” CMSE Conference2007, Components Technology Institute, Inc., Los Angeles,CA., Mar. 12-15, 2007, pp. 159-68.[6]. James P. Hofmeister, Pradeep Lall, Edgar Ortiz, DougGoodman and Justin Judkins, “Real-Time Detection ofSolder-Joint Faults in Operational Field Programmable GateArrays,” IEEE Aerospace Conference 2007, Big Sky, MT,Mar. 4-9, 2007, Track 11-0908, pp. 1-9.[7]. Accelerated Reliability Task IPC-SM-785, SMT ForceGroup Standard, Product Reliability Committee of the IPC,Published by Analysis Tech., Inc., 2005,www.analysistech.com/event-tech-IPC-SM-785.[8]. P. Lall, M.N. Islam, N. Singh, J.C. Suhling and R.Darveaux, “Model for BGA and CSP Reliability inAutomotive Underhood Applications,” IEEE Trans. Comp.and Pack. Tech.,Vol. 27, No. 3, Sep. 2004, pp. 585-593.[9]. R. Gannamani, V. Valluri, Sidharth and M-L Zhang,“Reliability evaluation of chip scale packages,” AdvancedMicro Devices, Sunnyvale, CA, in Daisy Chain Samples,Application Note, Spansion, July 2003, pp. 4-9.[10]. Sony Semiconductor Quality and ReliabilityHandbook, Revised May 2001,http://www.sony.net/products/SC-HP/tec/catalog, Vol. 2, pp.66-67, Vol. 4, pp. 120-129.[11]. Use Condition Based Reliability Evaluation: AnExample Applied to Ball Grid Array (BGA) Packages,SEMATECH Technology Transfer #99083813A-XFR,International SEMATECH, 1999, pg. 6.[12]. Comparison of Ball Grid Array (BGA) Componentand Assembly Level Qualification Tests and Failure Modes,SEMATECH Technology Transfer #00053957A-XFR,International SEMATECH, May 31, 2000, pp. 1-4.[13]. R. Roergren, P-E. Teghall and P. Carlsson,“Reliability of BGA Packages in an AutomotiveEnvironment,” IVF-The Swedish Institute of ProductionEngineering Research, Argongatan 30, SE-431 53 Moelndal,Sweden, http://www.ivf.se, accessed Dec. 25, 2005.[14]. D.E. Hodges Popp, A. Mawer and G. Presas, “Flipchip PBGA solder joint reliability: power cycling versusthermal cycling,” Motorola Semiconductor Products Sector,Austin, TX, Dec. 19, 2005.[15]. The Reliability Report, XILINX, xgoogle.xilinx.com,Sep. 1, 2003, pp. 225-229.[16]. J-P. Clech, D.M. Noctor, J.C. Manock, G.W. Lynottand F.E. Bader, “Surface mount assembly failure statisticsand failure-free times,” in Proceedings, 44 th ECTC,Washington, D.C., May 1-4, 1994, pp. 487-497.[17]. P. Lall, P. Choudhary and S. Gupte, “HealthMonitoring for Damage Initiation & Progression duringMechanical Shock in Electronic Assemblies,” Proceedings9