ISSN: 2250-3005 - ijcer

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International Journal Of Computational Engineering Research (ijceronline.com) Vol. 2 Issue. 8The input interface has the following features:Avalon-ST data sinkReady signal latency of one cycleDoes not apply back pressure since data is continuous from RF cardThe output interface has the following features:Avalon-ST data sourceReady signal latency of one cycleDoes not accept back pressure from downstream sinkDynamically changeable cyclic prefixFFT MegaCore FunctionThe FFT MegaCore function is capable of performing both the forward and inverse transform. Thehardware architecture is chosen to minimize the resource usage and has the following parameters:Burst modeSingle output engineSingle instance of engine16-bit internal and data input/output precision widthsIn addition, design implements two clock domains so that it is possible to exploit time sharing andminimize resource utilization in the FFT MegaCore function by running Clock 1 faster than Clock 2. The FFTMegaCore function generates block floating point output data and the output dynamic range is maximized for thegiven input and output data widths.Clock RequirementsThe clocking requirements are as follows:The two clock domains must be synchronousThe minimum Clock 2 frequency is the data sampling frequency given in Table 1. This would lead to aconstant output from the FFT MegaCore functionFFT Points Bandwidth (MHz) Clock 2 (MHz)128 1.25 1.429256 2.5 2.857512 5 5.7141,024 10 11.4292,048 20 22.857Table 1. Minimum Clock 2 Rate The Clock 2 frequency may equal or exceed the Clock 1 frequency The Clock 1 requirements are dictated by the FFT MegaCore function and are summarized in Table 2FFT PointsRequired data rate(MHz)FFT throughput(Cycles/ N block)Clock 1 minimumSpeed (MHz)128 1.429 858 9.579256 2.857 1,626 18.146512 5.714 3,693 41.2141,024 11.429 7,277 81.2202,048 22.857 16,512 184.285Table 2. Clock 1 RequirementsIssn 2250-3005(online) December| 2012 Page 79
International Journal Of Computational Engineering Research (ijceronline.com) Vol. 2 Issue. 8Table 2 ignores the cyclic prefix effect, which reduces the Clock 1 speed requirement slightlyThe Clock 1 minimum speed = throughput/N × data rate6. ConclusionThis application note has outlined the advantages of using Altera FPGAs for implementing OFDM systemssuch as an IEEE 802.16e deployment. A flexible, high-throughput DSP platform needs an FPGA-basedimplementation platform. In addition, this reference design demonstrates the implementation of a key function thatmay be exploited to facilitate rapid system deployment.7. ResultsSymbol generator simulation output of an OFDM kernel for WiMAX as obtained in Model Sim®Issn 2250-3005(online) December| 2012 Page 80
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ISSN: 2250-3005 - ijcer

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