ISSN: 2250-3005 - ijcer

International Journal Of Computational Engineering Research (ijceronline.com) Vol. 2 Issue. 8The input interface has the following features:Avalon-ST data sink and status sourceReady signal latency of one cycle—the earliest time valid data may be presented to the block after ready hasbeen signaled is one clock cycleThe output interface has the following features:Avalon-ST data sourceReady signal latency of four cycles—the block responds to new data or stops delivering data four cycles afteran event on the ready signalSupport for back pressure and Dynamically changeable cyclic prefixUplink ReceiveThe uplink OFDM kernel module performs an FFT of the time domain input data and removes the cyclicprefix. The Avalon-ST start of packet pulse should specify the start of the cyclic prefix. The remove cyclic prefixblock ignores the data during the cyclic prefix and writes the remaining samples to the FFT input buffer.EmbeddedmemoryAvalon – STData SinkInterfaceIFFT MegaCore FunctionAdd CyclicPrefixAvalon – STdata sourceInterfaceClock 1Clock 2Figure5. Uplink OFDM Kernel Block DiagramBecause the channel characteristics can change, it is possible that the start of the packet pulse is not alwaysafter the start of the cyclic prefix time. The hardware has been designed to deal with this scenario but with theconstraints that the variation of the pulse must be within the cyclic prefix time and that the start pulse will not bebefore the preceding symbol has been fully clocked in.Uplink Interface SpecificationsThe block has two clock domains. In addition, there are two reset ports; one for each clock domain. Thereset ports are active low.cp_widthdin_readydin_validdin_realdin_imagdin_start_blockConfiguration InterfaceAvalon –ST SinkInterfaceAvalon –ST SourceInterfaceFigure6. Uplink OFDM Kernel Interfacesdout_readycp_widthdout_validcp_widthdout_rcp_widthdout_idout_expdout_start_blockdout_end_blockIssn 2250-3005(online) December| 2012 Page 78