ISSN: 2250-3005 - ijcer

International Journal Of Computational Engineering Research (ijceronline.com) Vol. 2 Issue. 86. COMPARISION RESULTSThe device used to take Comparison results is Spartan XC3S400-5 PQ208.Tab 1: Comparison results of Sigmoid function proposed system and previous system.7. CONCLUSIONIt is seen from the comparison table in section VI that previous system [15] used more number of Slices, LUT’s andIOB’s for sigmoid function. So our sigmoid function system used less number of resources as mentioned above. So we haveeffectively reduced the area utilization of these neural network systems. This has increased compactness & reliability of oursystem. In future our system permits us to achieve maximum level of optimization.Therefore one should aim at giving ahardware platform for ANN like FPGA because of the re-configurability of FPGA, we can develop the prototypes ofhardware based ANNs very easily. Mapping FPGA into Field programmable Neural Network Arrays can fin d vastapplications in real time analysis.REFERENCES[1] I. A. Basheer and M. Hajmeer, ―Artificial neural networks: Fundamentals, computing, design, and application,‖ J. Microbio.Methods, vol. 43, pp. 3–31, Dec. 2000.[2] M. Paliwal and U. A. Kumar, ―Neural networks and statistical techniques: A review of applications,‖ Expert Systems WithApplications, vol. 36, pp. 2–17, 2009.[3] B. Widrow, D. E. Rumelhart, and M. A. Lehr, ―Neural networks: Applications in industry, business and science,‖ Commun. ACM,vol. 37, no. 3, pp. 93–105, 1994.[4] A. Ukil, Intelligent Systems and Signal Processing in Power Engineering, 1st ed. New York: Springer, 2007[5] B. Schrauwen, M. D’Haene, D. Verstraeten, and J. V. Campenhout, ―Compact hardware liquid state machines on FPGA for realtimespeech recognition,‖ Neural Networks, vol. 21, no. 2–3, pp. 511–523, 2008.[6] C. Mead and M. Mahowald, ―A silicon model of early visual processing,‖ Neural Networks, vol. 1, pp. 91–97, 1988.[7] J. B. Theeten, M. Duranton, N. Mauduit, and J. A. Sirat, ―The LNeuro chip: A digital VLSI with on-chip learning mechanism,‖ inProc. Int. Conf. Neural Networks, 1990, vol. 1, pp. 593–596.[8] J. Liu and D. Liang, ―A survey of FPGA-based hardware implementation of ANNs,‖ in Proc. Int. Conf. Neural Networks Brain,2005, vol. 2, pp. 915–918.[9] P. Ienne, T. Cornu, and G. Kuhn, ―Special-purpose digital hardware for neural networks: An architectural survey,‖ J. VLSI SignalProcess., vol. 13, no. 1, pp. 5–25, 1996.[10] A. R. Ormondi and J. Rajapakse, ―Neural networks in FPGAs,‖ in Proc. Int. Conf. Neural Inform. Process., 2002, vol. 2, pp. 954–959.[11] B. J. A. Kroese and P. van der Smagt, An Introduction to Neural Networks, 4th ed. Amsterdam, the Netherlands: The University ofAmsterdam, Sep. 1991.[12] J. Zhu and P. Sutton, ―FPGA implementations of neural networks—A survey of a decade of progress,‖ Lecture Notes in ComputerScience, vol. 2778/2003, pp. 1062–1066, 2003.[13] “MATLAB Neural Network Toolbox User Guide,” ver. 5.1, The MathWorks Inc., Natick, MA, 2006.[14] A. Rosado-Munoz, E. Soria-Olivas, L. Gomez-Chova, and J. V. Frances, ―An IP core and GUI for implementing multilayerperceptron with a fuzzy activation function on configurable logic devices,‖ J. Universal Comput. Sci., vol. 14, no. 10, pp. 1678–1694, 2008.[15] Rafid Ahmed Khali,l Hardware Implementation of Backpropagation Neural Networks on Field programmable Gate Array (FPGA)Issn 2250-3005(online) December| 2012 Page 27