Commodore 1541 Troubleshooting & Repair Guide (PDF)

Commodore 1541Troubleshooting& Repair GuideMichael G. PeltierHoward W. Saini & Co.A Division of Noxmillan, Inc.43lXl West62nd Street, Indianapolis, IN 46268 USA

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ContentsAcknowledgments ..IntroductionCHAPTER 1 Description 01 the VlC·1541. 11.1 WHAT IS A VIC-l541?. 11.2 ANATOMY OF A FLOPPY DISK. 31.3 INSIDE THE VIC-I541 .. 41.3.1 Disassembly and Identtflca1lon of Subassemblies . 41.3.2 Chonging Detnce Numbers. 41.3.3 Reassembly. 9CHAPTER 2 Theory of Operation. 152.1 OVERALL THEORY OF OPERATION, ALL MODELS. 152.1 1 Ouetsimpn/1ed Theory of Operation. 152.1.2 Simplified Theorv ofOperation. . 162,2 MECHANICAL THEORY, MODELS 1540 AND 1541. 162.2.1 Loading and Unloading. . " , 182.2.2 Track Selection. . 182.2.3 DrJue System. 192.2.4 Write Protect System. 192.3 MECHANICAL THEORY,MODEL 1542, ... , .... 192.3.1 Loading and Unloading. ..202.3.2 Track SeJectlon. . . 2D2.3.3 Drive System, 212.3.4 WritePtotectSJl$!ern ,212.4 ELECTRONIC THEORY, ALL MODELS 212.4.1 PowerSupp/y. . 222.4.2 Computer Circuit. . 222.4.3 TImingOrcutt. 22iii

Content,2.4.42.4.52.4.62.4.72.4.82.4.9Track Select Circuit .. , .. .... 24DriveMotor Servo Circuit, Models 1540(lnd 1541 . . 24DriveMotor Servo Circuit, Model 1542 24Read Circuit . . . . . . .. 25Encoder/Decoder Circuit. .. 26Write Circuit. . . . . . .. 27CHAPTER 3 Alignment, .3.1 EXERCISING THE DRIVE UNIT.3.2 CAUBRATING DISK RPM.3.3 READ/WRITE HEAD ALIGNMENT .3.3.1 Shop-Quality Ahgnment .3.3.2 Emergency or Make'lhift Ahgnment3.4 TRACK NO.1 STOP ADJUSTMENT .2929. 30.33...33.38. 40CHAPTER 4 Preventive Maintenance. 434.1 EXTENDING THE LIFE OF THE VIC-I541. .. 434.2 EXTENDING THE LIFE OF THE FLOPPY DISK 444.3 CLEANING THE READ/WRITE HEAD. . 454.3.1 Using Head Cleaning Disks. . 454.3.2 Manual Head CleanIng. , 45CHAPTER 5 Basic Troubleshooting and Repair. 475.1 INTRODUCTION TO TROUBlESHOOTING .5.2 IDENTIFYING A PROBLEM..5.3 BASIC TROUBLESHOOTING FLOWCHART..47...48........ 50CHAPTER 6 Advanced Troubleshooting and Repair. 676.1 INTRODUCTION TO ADVANCEDTROUBLESHOOTING. .......•. . .. 676.2 ADVANCED TROUBLESHOOTING FLOWCHARTS .. 686.2.1 FaultyGreen LED . 686.2.2 FaultyRed LED. . 696.2.3 FaultyPower Supply . . 716.2.4 Faulty DriveMotor. . 756.2.5 FaultyStepping Motor. . 796.2.6 Faulty Computer Circuit .. 966.2.7 FaultyRead/Write CircuIt. 1256.2.8 Blown Fcses • 144

ContontsCHAPTER7 Advanced Theory of Operation.7.1 ADVANCEDTHEORY, MODEL 1540.7.1.1 Frame Electrical Theory ..7.1.2 Power Supply Electrical Theory .7.1,3 TImingElectrical Theory .7.1.4 Computer ElectrU.:al Theory.7.1.5 Track SelectElectrical Theory ....7.1.6 Driue Motor System Electrical Theory.7.1.7 WrIte Clrcu~ Electrical Theory.7.1.8 Read Circuit Electrical Theory.7.1.9 Encoder/Decader Electrical Theory .7.1.10 Optics ClrcLlit Electrical Theory .7.2 ADVANCEDTHEORY, MODEL 1541.7.2.1 Frame Electrical Theory.7,2.2 Power Supply Electrical Theory .7.2.3 Timing Electrical Theory .7.2.4 Computer Electrical Theory,7.2.5 Track Select ElectrU.:al Theory.7.2.6 DrlueMotor System Electrical Theory.7.2.7 Write Circuit ElectricCl! Theory.7.2.8 Read Circuit Electrical Theory.7,2.9 Encoder/Decoder Eloctrlcal Theory.7,2.10 Optics Circuit Electrical Theory .7.3 ADVANCEDTHEORY, MODEL15427.3,1 Computer Circuit.7.3.2 DriveMotor Seroo Circuit.APPENDIX A Technical Data.Al INDEXTO TECHNICAL DATA .A2 ViC-1541 INTERCONNECT DIAGRAMS .A.3 VIC-I541 SCHEMATICS.A.4 VIC-I541 PARTS lAYOUTSA.S MODEL 1540 PARTS LIST.A.5.1 Disk ControllerPC Beard.,A.5,2 DriveMotor Servo CircUit.A6 MODEL 1541 PARTS LIST ...A.6.1 DIsk ControllerPC Boord .A.6.2 DrIveMotor Servo Circuit.A.7 MODEL 1542 PARTS LIST.A.7.1 DIsk ControllerPC Board .A. 7.2 Driue Motor Seruc Circuit.145145145145147148.. 156. 157159159162165165165166167169. .... 175177179.., .. 180182182183183185187187190. .... 192207. .... 215215.. ... 216217217...218..... 219., .. 219.. ... 220

ContentsAPPENDIX B Fabrication of Video Detector. 221APPENDIX CMOS Handling Precautions. 224APPENDIX D Standard ICPin Numbers. 225APPENDIXE Description of Disk Controller IC . 227

Acknowledgments1wish to thank the following for contribUllng to the preparallon of this manual:Ed Roseru;teinPaula MayfieldLeiItJ PeillerQuality Compul

To my children, Joshua, Matthew, and Rachel"'

IntroductionThiS book provides troubleshooting and repairinstructions for the VIC-1541 serles diskdrives, Models 1540, 1541, and 1542.When the text Is referring to all three models, thenomenclature VIC-1541 wlll be used. If tn., textrefers to a disk drive by model number, the infor_mation applieS only to that model.Chapter 1, "Description of the VIC-1541,"explains briefly what a VIC-1541 is and examine.the analomy of a floppy disk. If you would like toget your hands on the insides of your V1C-1541,read Section 1.3, "Inside the VIC-l541." This sectionprovides instructions lor disassembling theVIC-l54l. The text /amillarizes you wllh each ofthe subassemblies as they are removed. It also givesInstructions lor changing the device number andreassembling the parts.Chapter 2, "Theory of Operation," is designedto help you understand "how it works." Three levelsof the theory of operation are provided, eachbased on a block diagram, The first level of theoryis general and oversimplified, The second levelgoes a little deeper, but although functions of majorcircuits are dlscussed, level 2 15 still simplified. Thethird level analyzes the major circuits discussed Inlevel 2, using a detailed block diagram for eachcircuit.A fourth level of theory of operation 15 pre-vided in Chapter 7, "Advanced Theory of Operation,"This theory is discussed on a componentlevel, using the circuit schematic instead of a blockdiagram.Chapter 3, "Alignment," provides Instructionsfor proper adjustment of your disk rpm's, track No,r stop, and read/write head alignment. in Section3.3, "Read/Write Head Alignment," two methodsof alignment are presented, One procedure is ashop-quality alignment, For those who do not haveaccess to a reference disk or dual-trace oscilloscope,a second alignment procedure is provided.This procedure only requires a screwdriver, vohmeter.and the homemade video detector that 15described in Appendix B. Although not shop-quaH·ty because of a lack of accuraie reference, thisemergency procedure will get your drive working,Guidance In selectmg a reference is also providedChapler 3 also introduces a utility program whichcan exercise the mechanical functions of the drivefor test purposes,Chapter 4. "Preventive Maintenance," providessuggestions to promote long disk drive anddisk life. Also covered Is periodic maintenance,Section 4.3, "Cleaning the Read/Write Head," hastwo head-cleaning procedures. One procedure requiresa head-cleaning disk, The other procedurecovers manual cleaning of the read/write head,

Introdl1cllonChapter 5, "Basic Troubleshooting and Repair,"explains how to troubleshoot the VIC-1541,solving some problems wh~e focusing other solutionson a group of parts using a flow

CHAPIERIDescription of theVIC-1541If you are Interesb.!d In repairing or maintainingyour VlC-1541 disk drive, you probably alreadyknow hasteally what a disk drive Is andwhat II III llS'!d for. For the benefit of the novicewho may have a few quesllons about the basses, IwlU de=ibe the VIC-1541l1l1d lis uses here.1.1 WHATISAVIC-1S41?The VIC-1541 disk drive is II mass storageperipheral which Clll1 store or recall Informationfrom a removable floppy disk. When connected tothe Commodore 64 or VIC 20, the VIC-I541 givesthe computer the capability to "file" Information onthe floppy disk. Without this file capability, yourcomputer Clll1not perform such useful work a. wordprocessing or database management. Also, programstorage and retrieval Is much faster and easierwhen using the disk drive In lieu of the DlIlllsetlerecorder.Three versions of the VIC-I541 have !leenproduced by Commodore; they can be seen InFigs. 1-1 through 1-3. Although these disk drivesclosely resemble each other, their Internal differencesare subs!llntlaL All three ver.lons 01 theVlC-I541 have the seme controls, indicators, con"nectars, and command sets. Table 1-1 describesthe controls, Indicators, and connectors., .Ftll.l_t. Fronlvlow of Modoll540.Note: AIlthree versions of the VIC-I541Iu1ve"1541" printed on their fronts. Model 1540 has"VlC-I54l" and "stngle drive floppy disk." Models1541llnd 1542 both have "1541" on their fronts.Model 1542, however, has II tw!st-lype disk latchon the left-hand side of the disk slot, lIS cen be seenin Fig. 1-3. BeclIUS8 some versions of Model 1540use the same housing as Models 1541 and 1542, itIs necessary to refer to the parts layout drawings inAppendlJr A to determine exactly which model youhave.

2 Cl541 TROUBLESHOOTING & REPAIR GUIDEFig. l_2. Frontviowol Model 1541.aVIC-I541 Is being accessed. Never remov~ thefloppy disk when this LED is continuously mum!­nate

D.",,~prt"" of theV1C·1541 3WARNING• Neve, attempt to change the fuse with theac llnecom Installed.• Always Install fuse of COrTeet sizE and raUng;failure to do SO may re.ult in fireand/or per­$Onalinjury.The two serial bus connectors (Items 8 and 9)are used to connect the V1C-154110 the compulerand other serial bus peripherals. Both connectorsare electrically IdenllcaL They are wired In parallel,1.2 ANATOMY OF AFLOPPY DISKA floppy disk Is illustrated in Rg. 1-5 and itsparts are enumerated in Table 1·2,Table1_2. Anatomy of" FIopp~ Dlsk~. FIGURE DESCRIPllONW J·5B ~u J·5B ".~ra 'M I"do. Culoutia J·5B I"do. Hole'M Rood/Writ. SJoiis " 'M Wnt«ProIo

.. Cl541 TROUBLESHOOTING s, REPAIR GUIDEered with opaque !ape, writingis di...bled. Note theproper way to insert the disk (see Fig. 1·5A).1.3 INSIDE THE VIC-1541This section describes the insides of theVIC-I541 and basic maintenance consisting ofdisassembly, changing device numbers, and reas·sembly.1.3.1 Disassembly andldendflcation of SubassembliesWARNINGBefore lIttempting to disassemble this dJskdrive. remOVe the ac Une cord and any serialbus cables, Failureto do so could resuh Indamageto the disk drive or personal, possibly fatalInjury.The subassemblies that make up the 1540,1541, and 1542 may be seen in Figs. 1·6, 1·7, and1-8, respectively. Table 1-3 identifies these sub·essembues and parts. Refer to the table and theapp1lcable illustration for the model you are disas·sembling. Below is a procedure to dismantle thedisk drive completely. In practice, disassemble thedisk drive only as far as is necessary to accomplishthe maintenance you wish to perform,To remove the top cover (Item 16) from thebottom cover (Item 17), tum the disk drive upsidedown and remove four screws (!tern 18) using aPhlUlps screwdriver_Then gently lift the disk driveout of the top cover.To remove the RR shield (Item 19), removetwo screws (Item 20) and two lockwashers (Item21). (Note: In some unlls, the screws (Items 20,30, and 32) and lockwashers (Items 21, 31. and33) are aUone plece.]Lift the left-hand side of the RFI shield sUghtlyto allow the dimples on the right-hand side to cleartheir mating holes, Before liftingthe RFI shield clearof the disk drive, check to see If the wiring Isthreaded through the square hole on the right-handside of the RR shield; If so, disconnect the connector(Item 22) and ltft the RFI shield clear of the diskdrive.Table1-3. Sub.....mbll.' oIth. V1C·1541FIGURE1-6, 1-7, 1-8I-{;, 1-7, 1-8I-{;, 1_7, 1_81_6, 1_7. 1_81·6, 1·7, 1·81·6, 1·7, 1·81·6,1-7.1-8H,I-7.HI1-{;.1-7. 1-81_6.1_7.1-81·6.1·7.1_81-6.1·7.1·81·6.1-7.1·81-{;,1-7, 1-81-{;. 1_7. 1-81-{;. 1_7. 1-81-{;. 1·7, 1-81-{;. 1·7, 1-81-{;,1-7, 1-8H, 1-7, 1-81-6, 1-7, 1-8DESCRlPTlDNTQpCove,_om 0,..,~~RFI "h,"ld~.~Ld

"Fig. 1-6. Exploded .iew of Modoll540.

• Cl541 TROUBLE5H(X}TING & REPAIR GUIDEFig. 1_7. Exploded view of Mod.1 1541.

Fig, ,. _. E>

• cteu TROUBLESHOOTING & REPAIR GUIDEis configured for device #8 and VIC·I541(B) isconfigur",d for device #9. This configuration iscalled "daisy chaining." The data goes into a peripheralon one serial bus connector, then out theother serial bus connector to the next peripheral,and So on. The peripheral that is being addressedacts upon the' data. Peripherals that are not eddressedsimply pass the data on to the next peripheraLoTHER SER1AleUS OEVICESFig. I·'). Multlpl. disk dnve conflguratlan.To lUuslrate the difference In commands reoqutred for two or more disk drives, assume thatVIC-I541(Al and VIC"I541(B) each contatn ablank floppy disk that Is to be formatte

Deocriptkm0/ the V1C-1541 itTabl.I·4.Selectlng Dovi"" NumberPROGRAMMING PADSDEVlCENO. LOW ORDER HIGH ORDER(ITEM S7){ITEM:l81e t'lo,Cu, Not Cu'• ,,,Not Cu'W No,Cu, ,,,H'"',,,perlonned, Reier to Fig. 1-16 to reassemble the1540, Fig. 1-17 to reassemble the 1541, andFig. 1-18 to reassemble the 1542. Refer to Table1-5 for definitions of item numbers_Fig. 1·13. Location 01prograrnmingpad•. Mod.l 1541,. "Ag. 1_14. Locatkm 01progrommlng""d" Mod.l 1542,WIRE c:::::;""~~Fig. 1·15. Ropalling cutprogrommlng pads_1.3.3 ReassemblyThe lollowing procedure to reassemble theV1C·I541 assumes that the disk drive is completelydisassembled down to the subassembly level. Re",,'semble as is necessary lor the maintenance youT"bl.t·5. R......mbly ofth. VIC·tM1~. fiGURE DESCRIPTION.. 1_16.1_17. i.ia Top Cov",1·16. 1·17. i.ia Bottom Cove,"re 1·16.1·17. i-re 5=... 14)is 1-16,1-17, l-IB RFl Shiokieo 1-16,1-17, 1-IB 5=... (2)1_16.1_17, t-IB l""'....ben" ea 1_16,1_17, i-ra Conn«tw Il

10 elMI TROUBLESHOOTING & REPAIR GUIDEFig:. 1_16. Ru••.,mblyol Model 154Q.

Fig. 1_11. R........rnblyof Model 1541.Deoertption ollhe VlC-lf>41 11

12 Cl541lROUBLESH00l1NG & REPAIR GUIDEFIg. 1·18. Re.....,mbly of Model1542.

Descrlp/lO!1o/th.. VIC-1541ISunit and the frame, Secure the drive unit using twoscrews (Item 36) on the right-hand side of the driveunit, and two screws (Item 36) on the left-hand sideof the drive unitTo inslall the disk controller PC board (Item24), proceed as follows: Drape the cable bearingthe connector (Item 29l into rectangular slot "A" sothat the connector is outside of the frame Drapethe wire bundle be.arlng the connector (ltem 25)over the comer of the frame marked "B" so that theconnector is outside of the frame. Drape the remainingwires bearing thr~ connectors (Items 27,28, and 29) into the slot marked "C" so that theconnectors are outside of the frame.Note: Be SUre to follow the order describedhere for securing the screws. To lighten In thereverse order might damage the PC board. Also,do not overtighten the screws.Position the PC board as shown In the appropriatefigure; secure it with two screws (Item 32)and two Iockwashers (Item 33) through the holes inthe right-hand side of the frame. Be careful toavoid pinching the wires between the frame (Item34) and the heat sink on the PC board. Secure thePC board with five screws (Item 30) and five lockwasherslitem 31). Be careful to avoid pinching thewires between the frame and the PC board.Connect the five female connectors [Items 25through 29) to their maling male connectors (Items39 through 43, respectively) On Models 1540 and1542, these connectors are oriented so that theslotted side should face the center of the PC board.On Model 1541 only, the slots of one connector(Item 29) face away from the PC board (seeFig, 1-19)To install the bottom colier (Item 17l. placethe frame lltem 34) Into the bottom colier (Item17); secure it with six screws (Item 23). Do notovertighten the screws, or the holes in the bottomcaller may become stripped, Use care to ensurethat the wires are not pinched between the frameand the bottom Caller.Fig. 1_19. Slotted ,id.. of conneclorSLOTSTo inslllllthe RFI shield (Item 19l, first connectthe female connector (Item 22) to lis mallng maleconnector (Item 44l.Note: On Model 1540, thread the connector(Item 22) through the square hole in the leh-handside of the RFI shield (Item 19)Position the dimples in the RFI shield into lhelrmating holes on the right-hand side 01 the frame(Item 34); position the holes on the left-hand sideof the RF[ shield ever the threaded holes in theleft-hand slele of the frame, and secure with twoscrews (Item 20) and two lockwashers (Item 21).Take care that no wires are pinched between theRFI shield and the frame.To Install the top cover (Item 16), position thetop cover over the disk drive and the bottom cover(Item 17). Tum the disk drive and the lop coverupside down and secure with four screws (Item1B). Be careful to avoid pinching the wires betw~nthe top cover and the bottom cover,

CHAPTER 2Theory of OperationIn this chapter, we will look at the theory ofoperation of the VIC-1541 on three difflm!ntlevels. As with peeling successive layers froman onion, each level of theory reveals more informationabout the VIC-1541 than the level before it.2.1 OVERALL THEORY OFOPERATION, ALL MODELSWe start our discussion w!th Section 2.1.1,''Oversimplified Theory of Operation." This sectionIs the most ac

16 Cl541 lll.OUBLESHOOTING & REPAIR GUIDEfloppy disk's directory and block availability map(BAM).The drive unit is predominantly a mechenlealassembly that rotates the floppy disk andperforms the actual recording and reading of thenoppy disk. The drive unit is 10 a floppy disk as atape deck Isto a cassette tape.2.1.2 Simplified Theoryof OperationReier to Fig. 2-2 for a block diagram llIuminatlngthe following discussion. The power supplyconsists of a section of rectifiers that convert the acHne voltage to +9 volts de and +16 volts dc. Theoutputs of the rectifiers are applied to the voltageregulators. The voltage regulators, in tum, produceoutpul voltages of +5 volts and +12 volts. Thevoltage regulators also produce a switched outputof +11 volts, which is turned off during power upand power down operations in order 10 preventInadvertent writing on the diSk.The disk controller can be subdivtded Intoeight functional ctrcutts-cccmputer, timing, optles,track select, drive motor servo circuil, encoder/de·coder, read, and write. The computer circuit managesthe rest of the disk drive, using a program inflnnware refelTed to as the disk operaling system(DOS). The DOS program contains routines tocontrol the drive unit and the serial bus, as well asroutines 10 per/orm the housekeeping for the floppydisk. The serial bus circuits contain line drivers, linereceivers, and other logic thai interfaces the computerdrcult with the serial bus. The serlai bus cir·cults also generate the reset signal lor the computercircuit.The liming circuit produces the microprocessorclock and the encoder/decoder clock. The microprocessorclock is a fixed I-MHz square wave,which is the time standard for the computer. Theencoder/decoder clock is a variable Irequencyclock that determines the data transfer rate betweenthe disk controller and the drive unit. The frequency01the encoder/decoder clock is selected bythe computer circuit.The optics circuit drives the access/error LEDand a photoemilter in the drive unit. The photo·emitter passes light through the write protect notchin the floppy disk onto a photodetector. A signalfrom the photodetector Is applied to the optics circuliin the disk controller. The optics circuit convertsthis signal to a level that is compatible with thecomputer circuit.The track select circuit decodes position Inlormatlonfrom the computer circuit and buffers thisinformation before applying it to the four-phasehead positioning motor. Additionally, an outputfrom the track select circuit is applied to the drivemotor servo circuit. This digital signal Is used totum the drive motor on or off.The dnve motor servo circuit regulates the rctationalspeed of the floppy disk. The drive motorhas a built-intachometer which provides a feedbacksignal to the drive motor servo circuit. The drivemotor servo circuit uses this signa.! to measure thespeed of the disk and, in tum, adjusts the motorcurrent accordingly until the feedback indicates tbatthe disk is operating at the cOlTect speed.The encoder/decoder circuit is used for bothread and write operations. In the write mode, theencoder/decoder converts an 8-blt.byte from thecomputer circuit Into a senel stream of preciselyspaced transitions. The spacing between transitionsdetelTnines whether the bit is a "1" or a "0." Theencoder/decoder only ceres about the transitionSplicing, not the direction of the transltlons. Inthe read mode, the encoder/decoder converts thestream of transitions Into an 8-blt byte and appliesthis byte to the computer. The parallel data which istransferred to and from the computer circuit is fur·ther encoded. The DOS musl perform additionalencoding and decoding to generate or recover theactual data being stored.The transitions out of Ihe encoder/decoderare applied to the write circujj which provides thenecessary drive current for the recording process.This cwrent Is applied to the read/write head in thedrive unit. In tum, the read/write head recordsthese transitions on the floppy disk.In the read mode, the read/WIite head sensesthe transitions On the surface of the floppy disk andapplies these transitions to the read circuit. Theread circuit amplifies these low·level cUlTents to alevel suitable for the encoder/decoder circuit. Theoutput of the read circullis applied to Ihe encoder/decoder circuit and subsequently to the computercircuit.2.2 MECHANICAL THEORY.MODELS 1540 AND 1541This mechanical theory covers the theory ofoperation for the Alps drive unit which is used in

.8 Cl541 TROUBLESHOOTING & REPAIR GUIDEthe 1540 and 1541. If you have a 1542, whsch 15equipped with a Newtronks drive unit, see Section2.3, "Mechanical Theory, Model 1542."2.2.1 Loading and UnloadingRefer to Table 2-1 and Flg. 2-3 for an iUustratlonof the Alps drive unit. Every time a floppy diskIs inserted into the Alps drive unlt, four thingshappen:1. The disk ejector 15 locked,2. Read/write pressure 15 applied.3, Disktension is set.4, The floppy disk is held fltmly against the drivehub.Fig. 2_3. Alp. drtve un~. lo.ding .nd unloading.Table 2-1.Alp. Drive UM, Loading and Unloadingm. FIGURE DESCRIPTIONa,~"~,~ Disk Ejectm Am.,~ Ei""!O' fum Pln,~ 101" Hub Moon',~ D>ok T.n~Ofl Poda.a Unlo6dln

Th."'Y of Operation 19• •"FIg. 2·•. Alps drive untl. top view.2.2.3 Drive SystemRefer to Table 2-3 and figs. 24 and 2-5 forIllustration of the following discussion. The mechanlcaldrive syslem rotates the drive hub (Item53) and, therefore, the floppy disk itself,The drive motor/tachometer (Item 62) contarnsa motor and a tachometer On a COrnmanshaft. The tachometer section is used to generatespeed information for feedback purposes. The molorsection drives the tachometer and the drive pulley(Item 63), which turns the flywheel (Item 64)via the drive belt (llem 65). The flywheel smoothsout the motion of the drive hub (Item 53). Theflywheel may also contain a timing disk for the pur·pose of disk speed calibration. Disk speed Is regu.lated by the drive motor servo circuit (Item 66)Table 2-3. Alp. Drive Uo~. Drive System~ FIGURE DESCRlI'TIONsa ,.. onv, Hubsa ,.. on"" Mo_iTam"""""sa 2_5 011". PuU,yM a.s FI~wh••1ss a.s on""BoIt00 a.s on"" MoOOf 50"'0 Ore""FIg. 2·5. Alps drive unil, bootiomview,Table 2-2.Alp< Drive Untl. Track SeI.cUo,;~ FIGURE DESCRIPTIONM Reod/Writ. H••d Moun'ss ,.. Ho.d Mount Slid. R"i~~ T,.,k Select Bond;; H St'",,"'g Motor 011". Wh.,1M T""k f'osItjon Idler Fulley;0 ,. $p>jog_eu ,; S",,,,,109Moto,er ,. T,.ck No, 1 Stop2.2.4 Write Protect SystemRefer to Table 2-4 and Fig, 2·4 for illustrationof the following discussion. The write protect systemconsists of an LED (Item (7) and II phototransistor(Item 681. When a floppy dtsk is insertedwith the write protect notch, uncovered. the LEDtransmits light to the phototranslstor, activating thephototranslstor, The phototranslslor then informsthe disk controller that writing to the floppy disk ispermitted. If, however, the write protect notch iscovered. the light beam Is Interrupted and the diskcontroller will not pennlt writing to the floppy disk.Table 2·4.Alps Drive Unit, Writ< ProtectSystemH,.FIGURE2.3 MECHANICAL THEORY.MODEL 1542DESCRIPTIONThis mechaniClll theory covers the theory ofoperation for the Newtronics drive unit, which Is

aoCl&41 TROUBLESHOOTING & REPAIR GUIDEused in the 1542. If you have a 1540 or a 1541,which is equipped with an Alps drive unll, see Sectlon2.2, "Mechanical ThWfY, Models 1540 and1541."2.3.1 loacUng and UnloacUngRefer to Table 2-5 and Fig. 2-6 for lllusltatlonof the following discussion. Every lime a floppy diskis inserted Into the Newlronlcs drive unll, thr"""things happen:1. Read/write pressure is appUed.2. Disk tension Is set.3. The floppy disk Is held firmly against the drivehub.aFig. 2·6. N"wIrot1!dlng and vnlo.dlng.Table 2.5.N"wtron~ DrIve Un". loading and Unloading~ FIGURE DESCRlPDONa ,. ~'"Idiot Hub Moun'~ a.e Dhk T.nsk>n Pod"so ,. Preoo"",PodM""ntsa a-e Idle, Hub",. llrloEHub'",. Loarl'n" Actuola

Tho"'Yof OperationatThe drive motor/tachometer (Item 62) COntainsa motor and a tachometer On a COmmonshaft. The tachometer SllCtlOn is used to generatespeed lnformatlon for feedback purposes. The motorsection drives the tachometer and the drive pulley(Item 63), which turns the flywheel (Item 64)via the drive belt (Item 65). The flywheel smoothsOllt the motion of the drive hub (hem 53). Theflywheel may also contain a timing disk for the purposeof dlsk speed caBbratlon. Disk speed is regulatedby the drive motor servo circuit (Item66).Table 2_7.Newlrcnlcs Driv. Unit, Drive Sy«emFIg. 2-7.Newtronics

211 CI541 TROUBLESHOOTING & REPAIR GUIDE2.4.1 Power SupplyRefer to Fig. 2·9 for illustration pertaining tothe folloWing discussion. The power supply con·verts the ac ~ne voltage to regulated dc vo~ages 01+5 volts and +12 volls. The power supply alsoprovides a swltched supply which drives the readand write circuits,The ac Hne current enters the power switch atthe rear of the frame assembly. The output 01 thepower switch Is applied to the fuse, which providesoverload protection, then to the transformer. Thetransformer provides two lower at voltages of 9volts and 16 volts ac, The 9 volts ac from the trans·former Is applied 10 the +S·volt rectifier, whichIs a fuJl-wllve rectifier. The dc voltage out of the+5·volt rectifier Is filtered by the +S-volt Iilter,Ihen appHed to the +5-volt regulator. The +S-voltregulator regulates the voltage to +5 volts ±0.25volt.The 16 volts ec /rom the trllnsformer passesthtough the + 12-volt rectifier, + 12-volt filter, and+ 12-volt regulator, which operates similarly to the+S-volt leg of the power supply. Outputs of boththe + 5-volt lind +12-volt regulators are appHed tothe reHlIblHty switch. The rellabiHty switch fillers Ihe+ 12-volt supply, lind It turns this filtered supply onor off depending on the status of the +S-volt line.If the +S-volt Hne is less than +4 volts dc, then theoutput of the reliability switch (+Vsw) is turned off,If the +S-volt line is greater than +4 volts, the out·put of the rellllbilily switch is turned on. Since theoutput of the reltabillty switch drives the read andwrite circuits, this feature prevents accidental writ­Ing or erasure of data at power-up, powe.-downor, whenever the +S-volt logic supply is unreHable.2.4.2 Computer CircuitRefer to Fig. 2·10 for illustration pertaining tothe following discussion. The computer circuit consistsof a 6502 central processing unit (CPU), 2K," -,bytes of random-access memory (RAM), 16K bytesof read-only memory (ROM), senel bus Interlace,disk contrOller versatile Interlace adapter NIAl,write logic, and address decoder. The address decoderenllbles communications between the CPUand the deVice or memory whose address eppeerson the address bus. (See Table 2-9 lor device ad·dresses,1 The 16K ROM contains the DOS firm·ware, which Is actually a list 01instructions that theCPU executes in a logical otder, The 2K of RAM isused by the CPU to store temporary data such asread or write data, commands, stack information.and so on The write logic places the RAM Into thewrite mode when instructed to do so by the CPU.DEVICE",MSo""1 B",VIADIokCoo"ol1

Theory of Oper~'lon 235E~AL":~~~.r_:- "ICLocaSOIAl .U.nATA",TE"'AC'".!I"0>iFig. 2.10. Block dj.gr~m of tho computer clrcuil.ates a I-MHz clock for the CPU and a variable (1.0MHz to 1.2307 MHz) clock for the encoder/decodercircuit. The heart of the timing circuit is theI6-MHz oscillator. The I6-MHz square-wave outputof the 16-MHz oscillator Is applied to the + 16frequency divider and the +n frequency divider.The + 16 frequency divider divides the I6_MHzsquare wave by 16, yielding 1 MHz which is applledto the CPU, The +n frequency divider,Or programmable frequency dlvlder, provides theclock for the encoder/de

24 Cl541 TROUBLESHOOTING & REPAIR GUIDE2.4.4 Track Select CircuitReier to Fig. 2-12 for illustration pertaining tothe loUowing discussion. The desired track Is physicallyselected by positioning the read/write headusing the four-phase stepping motor, which rotates1.8 c per step. To move the read/write head onetrack, the stepping motor must rotate 3.6 c , or twosteps. ln order to step the read/write head Inward,each of the four q,[N) lines must be energii':ed inascending order (I.e., q,1, \1>2, \1>3, q,4, q,1, 2.etc.I. To step the read/write head outward, each ofthe four q,(N) lines must be energized in descendingorder (l.e., q,4, q,3, q,2, \1>1, q,4, 3. . etc.). Thephase decoder of Fig. 2·12 is a two· to four·linedecoder which decodes the binary phase numberfrom the computer circuit that is present on linesPHASE SEl A and PHASE SEl B. The decodedoutput is applied to the appropriate buffer (I.e., q,1buffer, 2 buffer, 3 buffer, or q,4 buffer) The2·bit binary numbers on the phase select lines areincremented to step the head in and decrementedto step the head out."'"......~....".Ftg.2-12. Blcck dlogrorn cf I... track ..I.ctcfrcult.Notice that the on/off signal from the computercircuit Is Inverted before being applied to theactive·low enable input of rhe phase decoder. Toenable the phase decoder and subsequently thestepping motor, the on/off line from the computercircuit must be high, If this line is low, then the steppingmotor is aUowed to rotate freely. The outputof the inverter is applied to a buffer and, in tum,the output 01 the buller is applied to the drtvemotor speed circuit. Only one line from the computercircuit controls the on or off status of both thestepping motor and the drive motor. Both motorsare turned on or all at the same lime; they may notoperate tndependently.2.4.5 Drive Motor Servo Circuit,Models 1540 and 1541Refer to Fig. 2-13 for illustration pertaining tothe folloWingdlscussicn. The drive motor servo clr·cuit for the Alps drive controls the rotational speedof the floppy disk. The ofl!on signal from the trackselect circuit is applied to gate the motor driver inthe drive motor servo circuit. When this line is low,the motor driver buffers the signal from the speedcontroller and applies this buffered signal to thedrive motor/tachometer, When the off/on line ishigh, the motor is turned ofl.As the motor turns, so does the tachometer,which is housed on the back 01the motor case, Thetachometer behaves like an alternator, providing anac signal whose output frequency and voltage areproportional to the rotlltional speed of the motor/tachometer, The output of the tachometer is appliedto the signal rectifier in the drive motor servocircuit. The output 01 the signal rectifier is a fullweverectified signal that i5 applied to the speedcontroller IC. This Ie monitors the output 01 thesignal rectifier and ""justs the motor current asneeded to maintain proper disk rpm. Becausesome floppy disks exhibit more drag than others.this circuit ensures proper disk speed from one diskto another.2.4.6 Drive Motor Servo Circuit,Model 1542Refer to Fig. 2-14 for illustration pertaining tothe following discussion. The drive motor servo circuitfor the Newtronics drive unit regulates the rotationalspeed of the floppy disk, The oil/on linefrom the track select circuit is applied to the gover·nor IC. When this line is high, the governor turnsoff the drive motor, When this line is low, the governorapplies current to the drive motor/tachometervia the motor driver.As the motor turns, so does the tachometer,which is housed On the back of the motor case, Thetachometer behaves like an alternator, proViding anac signal whose output frequency and voltage areproportional to the rotational speed of the motor/tachometer. The output of the tachometer is ep-

Theory cI I)porafion 25OFFIONr------------------------------,----,, ,,, ,SIGNALSPEl"DRECTIFIERCONTROLLl"R,MOTOR II DRIVl"R IIL ~DRIVE MOTOR Sl"RVO CIRCUIT Ir-----------------,: MOTORITACHOMETER III II I , II ~L ~J IFig.2-13. Bleck dlagrom c1th~ dnvemotor ""rvo cJrcu~. Mod~lo 1540and 1541.,MOTO~ ID~'VE~ I, ,1... ..J,-..O'ro~ii'AcHa...ETE~- - - -:i ,,I I I iLL_-..=-.=-::::IFig.2-14. Block di"!/I.m c1thednve motOr""""' clrcutt,Model 1542,plied to Ihe governor in the drive motor servo drcuil.The governor monitors the signal /rom thelachometer and adjusts the motor current as neededto maintain proper disk rpm. Because somefloppy disks exhibit mOre drag Ihan others, this drcuitensures proper disk speed from One disk toanother.2.4.7 Read CircuitRefer 10 Fig. 2-15 for illustration pertaining tothe following discussion. The read clIcuit sensesand screens data before it is applied to the encoder/decoder.The data on the surface 01 thefloppy disk is sensed by the read/write head andapplied to the first video amplifier via a diodeswitch. The state of the diode switch is determinedby the write circuit. When the write circuit is disabled.the diode swUch gates data from the read/write head to the flIst video amplifier. When thewrite mode is enabled, the diode switch allows datato pass from the write drcult to the read/write headwithout affecting the read circuits, The data fromthe read/write head is approximately a scant 7 millivolts.After amplification by the first video amplilier,this signal is Increased to 350 millivolts. The350-mlUivolt signal out of the first videoamplifie. isapplied to the second video amplifier, which has avoltage gain 01approximately 10. The 35-volt dif-

26 Cl541 TROUBLESHOOTING & REPAIR GUIDEferential signal out of the second video amplifier isapplied to a comparator, which converts the receiveddata to a transIstor-transistor logic (lTL) signal.Thls lTL signal is applied to the valid pulsedetector. The valid pulse detector Is disabled In thewrite mode. The valid pulse detector onll' passespulses that are at least 2,5 microseconds in duration.AnI' pulses less than 2.5 microseconds aresuppressed; this effectively rejects anI' noise above400 kHz, The output of the valid pulse detector isapplied to the edge detector. In turn, the edgedetector produces a narrow pulse on low-to-highand high-to-low transitions of the received data.These narrow pulses marking the transitions of thedata on the disk are applied both to the timing circuitas bit sync in order to Sl'ncmonize the encoder/decoderclock with the transitions, and tothe encoder/decoder as dalll for decoding.2_4.8Encoder/Decoder CircuitReier to Fig. 2-16 for Illustration pertaining tothe following discussion. The encoder/decoder circuitconverts the serial stream 01 transitions intoeight parallel bits of data for the computer circuitand vice versa, First we will discuss the decodingoperation. Assume Ihat the read/write line fromthe computer circuit ls high (read mode) The decoderconverts the serial stream of transitions intoa serial data stream as well as generating a shift!lock. Each bit cell out 01 the decoder is four encoder/decoderdock pulses long, If a transition (orinput pulse on Ihe dalll line from the read circuil)occurs at the beginning of a bil cell, then that bit cellis a loglc 1. II no rransilion (or input pulse on thedata line from the read circuit) occurs, then that bitcell is, a logic O. Both the serial data and shilt clockoul of the decoder are applied to a 10-bit serlal-toparallelconverter (or "shift register"). Addltlonalil',the shift dock is applied to the bit counter, Whenenabled by the computer circuit, Ihe bit counter sig'nals the computer circuit Ihat eight bits have beenshifted and the data In the serlal-to-parallel converteris readl' to be transferred to the computer circuit.The first eight btts of the 10-bit serlal-to-paralleIconverter are gated by the S-bit buffer to port Aon the disk controller VIA, All 10 bits out of the1O-bit serial-to-parallel converter are applied to thesync detector. At least 10 "ones" In succession arerecognized as a block 5l'nc. The block sync resetsor, "synchronizes," the bit counter and also informsthe computer that the start of a header or datablock has been detected. .This scheme has certain limitations to it. Onesuch limitation i5that in order to reduce dalll bandwidth,not more than two "zeros" may occur in succession.As stated earlier, a zero is a bit cell with notransition at the start of it. To read 256 consecutlvebytes of $00 would require 2048 bit cells In whichno data occurred. Another limitation is the fact thatdata such as I$FF followed by $CO would be detectedas a sync mark. To cverccme these limita·tions, group code recovery (GCR) Is used, WithGCR, five bits 01 recorded data are reqUired tomake one 4-bit nibble of Intelligence tsee Table 2·11) Using GCR coding, there will never be morathan two zeros In succession. Notice that $FF is1ST 2,.0VIDEO ~~p VIDEO ~"'P CO~P"'R"'TORM"81T SYNCF1EA,OJWR,TEHEADFig. 2_15. Block diagram 01tho 'oad clrcu~.

Theory of Operation 27............'" -1~--;===t-~r-lFig. 2_16. Blook dlogromof the encoder/decoder drcuR.written as 1010110101, and $CO Is written as0110101010; this does not conflict wllh a syncmark of 10 "ones" in succesetcn. Encoding anddecoding GCR Is performed in the computer circuit'sRAM, not by the encoder/decoder. The encoder/decoderperforms the encoding and decodingof the transitions to GCR-coded data, and viceversa.T.bIe 2-11.GCR CodingOffi~.""o 01010, 0101110010a 10011, 011100 01111s 10110t 10111a 01001, 1100111010"• lionc 01101C 1110111110, 10101Now we wtll discuss the encodlng operation.For encoding, the read/write ~ne from the computercircuit 15 low (write mode). With the read/write Itne low, the read circuit Is disabled, 50 thereare no pulses (or data) from the read circuit to thedecoder. However, the decoder does produce ashift clock at one-fourth the encoder/decoder clockrate.Additionally, with the read/write line low,both the sync detector and S-blt buffer are disabled.Data to be written is applied from port A of the diskcontroller VIA to the a-bit parallel-to-serial converter(shift register'. The shift clock 15 appliedto the a-bit parallel-to-serial converter and the bitcounter. After eight serial bits are shifted out of theparallel-to-serial converter, the bit counter loads thenext eight parallel bits Into the parallel-to-serlalconverter using the S/L line. Additionally, the bitcounter informs the computer circuit to gel the nextbyte ready lor the follOwing cycle. Both the shiftclock and the serial data out 01 the serial-to-parallelconverter are applied to the encoder. The encodergenerates a transillon when a serilll "one" is coincidentwith a shift clock. No transltlon is generatedfor a serlal "one." The data from the encoder Isapplted to the WIttecircuit.2.4.9 Write CircuitRefer to Fig. 2·17 for illustration pertaining tothe followmq discussion. The write circuit supplies

28 Cl541 TROUBlESHOOTING & REPAIRGUIDEthe read/write head with proper bias currents torecord data onto the floppy disk. Assume that theread/write line Is low (write model· The read/writeline from the computer circuit and the write protectsignal from the photodetector in the drive unit areapplied to the write loglc. If the floppy disk Is notwrite protected and the read/write line is low, thenthe write protect output to the computer circuit willindicate that writing to the floppy disk Is permitted.Additionally, the write logle will turn on the biasswitches which provide bias to the read/write headlind also billses the diode switch into the writemode via the read/write head.The write logic also turns on the amp enableswitch. In turn, the amp enable switch suppliespower to the differential write amp. Data from theencoder/decoder is applied to the differential writeamp, which generates the recording current. Theoutput of the differential write amp Is applied to theread/write head via the diode switch. These recordingcurrents magneticlilly polarize the coatingon the surface of the floppy disk. This recordingprocess Clln be thought of liS providing tiny mag-".,T1OPOOT1OCT"",....H."WRITE •••Fig. 2·11. BlockdiilS'.m ofth. _t1rouk.,05.,"nels on the surface of the disk; these tiny magnelsare later detected during the read or playbackprocess.

CHAPTER 3AlignmentThis chapter contains alignment procedureswhich apply to all models of the VIC-1541.Section 3.1 introduces a utlBty program thatmay be used to exercise the electromechanicalfunctions of the drive unit. This program may beused for troubleshootlng or for alignment setup.Section 3.2 Is devoted to disk speed caBbration.Section 3.3 contains two read/write head alignmentprocedures. The first procedure is a shopqualityalignment using an o>dlloscope and a cat'seye alignment disk. The second procedure is not ashop-quality alignment, but, in a pinch, will getyour disk drive working with a minimum of testequipment or it will enable you to recover datafrom a floppy disk which has been written duringan out-of-alignment condition. Section 3.4 Is theprocedure to adjust the track No.1 stop.3.1 EXERCISING THEDRIVE UNITThe program shown in Fig. 3-1 is a utmtyprogram that allows you to exercise the electromechanicalfunctions of the disk drive. By user command,this program wlll step the head in, step thehead out, tum the drive motor' on, tum the drivemotor off, and perform a bump (step out to trackNo.1 stop). Store this program on cassette tapeand/or disk. If your system has a cassette tape,store the program on tape because your disk drivemay not be working when you need the program.If you do not have a second disk drive or cassettetape, you may have to reenter the program manuallyinorder to troubleshoot your disk drive.A lew things should be noted about this programbefore atlemptlng to enter It. A commonmistake made by the novice is to use the invalidabbreviation 11 in lieu of PRINTI. This conditiongenerates a syntax error that is not easy tolocate. The proper abbreviation for PRINTI is P R. The Instruction PRINT 115 isabbreviated P < SHIFT> HIS. Another source01 confusion is the graphics characters In lines 60through 110 and line 8000. In line 60, the graphicscharacter after the first quote is obtained by press­Ing the f1 fundion key. This graphics characterappears again in line 60 in the remark instruction.The remark instruction need not be typed In; it Isthere only for your benefit. Each of the lmes thathave graphics charaders also have a remark ;nsrrucncnthat defines the graphics characters. Inline60, the remark instrudion indicates to press thefl key to get the graphics character. [n line 70,press 13 to get the graphics character; in line 80,press 15; and in line 90, press f7. To get the graphkscharacter in line 100, press 12 (f2 is < SHIFT>zs

so Cl541 TROUBLESHOOTING & REPAIR GUIDE11), and to get the graphics character in line 110.press f4 (f4Is 131.Line 8000 has two consecutive graphics characters.To get the firstcharacter, press CLR ICLRis CLR/HOME). To get the next graphicscharacter, press the cursor down key.Refer to Table 3-1 for a descripllon 01 theexerdser commands. This program may be usedwith fonnatted disks, alignment disks, Or blankdisks. Because it does not need the headers, theprogram will even work with no disk at alL Theexerciser program keeps a record of the track numberby adding or subtracting one-halt track for eachstep-in or step-out command. It Is Important tonole that il an adjustmenl Is made or if the read!write head Is physically moved by some meansother than the stepping motor, the track displayedon the screen may not agree with the actual headposition. To avoid any discrepancy, perfonn abump (12), which will bring the read!write headback to the track No.1 stop and set the screen displayto track No.1. This program may be used foraligntng, cleaning, testing, and troubleshooting thedrive unit.3.2 CALIBRATINGDISK RPMThen perform the adjustment Inthe lightof theTV or monitor screen. There are a substantial num-bar of Model 1542s, equipped with a N

Alignment 11drive. that do not have timing disks (see Fig. 3-3,Item 64). Two procedures will remedy this. Oneoption is to photocopy or trace Fig. 3·4, cut out thecopy. and adhere the illustration to the flywheel,using rubber cement or two-sided tape oniy. Do notallow either the adhesive or the tape to interierewith the drive belt. The other option is to use a frequencycounter as a relerence. To do this, connectthe frequency counter to pin 2 of the governor IC(see Fig. 3-3, Item 70). The disk is rotating at itsproper speed when the frequency counter displays367 Hz.4. Prepare the reference as described earlier inthe text.5. Connect the serial bus cable between the diskdrive and the Commodore 64/VIC 20.6. Connect the ec line cord between the diskdrive and an ec outlet.WARNINGUse extreme Care to avoid contact withframe components. High ac voltage potenlillisare present during this procedure These voltagesmaycause falallnJury.7. Tum on the disk drive, the monitor, and anyother peripherals. .8. Tum on fhe computer.9. H you are using a VIC 20, enter the lollowingcommand:OPEN 15,8,15, "U:":CLOSE 15 I"I•~•.,10. Load, or enter and then run the exerciserprogram of Section 3.1. Execute the drivemotor on command by pressing function keyf5. Alternatively. the drive motor may beturned on with the lollowing command:OPEN 15,8,15,PRINU15, "M-E" +CHR$(13Ol+CHRS

52 Cl5411ll0UBLESHOOTlNG & REPAIR GUIDEFig. 3-3. Di>kspero adjuS1ment.Mod.11542

A~5!'1m.nlaaFig. 3·4. Timing dl,k (ac!uol " ..)3.3 READ/WRITE HEADALIGNMENTWe now discuss two read/write head alignmentprocedures. The first ISection 3.3.1) is astep-by-step procedure, shop-quality alignment andis preferred over the second procedure, which is anemergency or makeshift alignment (Section 3.3.2).The shop-quality alignment requires a dualtraceoscilloscope and an alignm"nt referenc« disk(Dysan Analog Alignment Diskette 224!2A). ITthisequipment is nol available, follow th" second align·ment procedure using a voltmeter, video detector(see Appendix B), and a formatted disk you knowto be in proper alignment. This procedure Is alsouseful for recovering data from a diskette that wasrecorded on a disk drive that wlIS out of alignment.The VIC·1541 disk drive frequently goes outof alignment because of the track select mechanism.The stepping motor drive wheel (FIg. 3·3,Item 57) is aluminum and Is press-lit onto a stainlesssteel shaft. As the VIC-1541 heats up, thealuminum pulley expands fester than the shall,causing the pulley to loosen slightly. When the pulleyis loose and hits the track No.1 slop (Item 61),It slips on the shaft. The result Is a misaligned read/write head. At first glance, the track No.1 stop appearsto have moved because the gap between thepulley and slop Increases, but this Is seldom thecase. Out of over 80 malfuncllonlng VIC·1541 diskdrives I have repaired, fewer than 10 were due toproblems other than the pulley slipping on theshaft.3.3.1 Shop-Quality AlignmentThis procedure requires a dual-trace csctlloscope,Dysan Analog Alignment Diskette 224/2Aor equivalent, and a Phillips screwdriver.1. Remove all cables from the VIC-1541,especially the ac line cord.2. Disassemble the V1C·154l1n accordance withSecllon 1.3.1.3. Conned five female connedors (Items 25through 29) to their mating connectors (Items39 through 43, respectively) (See Fig. 3-5 forthe 1540, Fig. 3·6 for the 1541, and Fig. 3-7for the 1542.) See Section 1.3.3 for properconnedor orientation. Place thesesubassemblies In such a fashion as to allowaccess to the bottom of the drive unit whilenot allowing the PC board components tocontact any metal parts4. Connect the serial bus cable between the serialbus connector (Item 8) and the Commodore64jVIC 20.5. Connect the ac line cord between the ec linecord connector litem 6) and an ac outlet.WARNINGUse extreme care to avoid conlacl w~hframe componenis. High ac voltage potentialsare present during this procedure. These voltage.may cause hllalinjury.6. Conned channel A of the dual-traceoscilloscope to pIn 7 of the second video amp,and conned channel B to pin 8 of the secondvideo amp. (See Fig. 3-8 for Model 1540 OrFIg. 3-9 for Models 1541 and 1542.) Connectchannel A at 73 and channel B at 74. Invertchannel B and place the scope Into A + Bmode. Set the verllcal sensitivity to 2V/cmand swe"p time to 20 ms.7. Turn on the disk drive, any peripherals, andthe osdlloscope.8. Turn on the Commodore 64/VIC 20.9. Load, Orenter and then run the exerciserprogram of Section 3. L10. Inserl the alignment disk (Dysan AnalogAhgnment Diskette 224/2A or equivalent)into the drive un~.11. Depress function key fl as many times asnecessary until the display Indicates trackNo. 17.

34 Cl541 TROUBLESHOOTING & REPAIR GUIDE"'--""•"FlO. 3-5. Alignment setup. Mode11540.

Fig. 3·6. AlIgnment ..tup, Model 1541.A~gmn.nt 35

3fiCl541 TROUBLESHOOTING & REPAIR GUIDE"FIg. 3-7. A!ignmenl setup. Mod.1 1542,

A~gTl"",ntS7"fig. 3-8. Locotlon 0/ ..cond vtdeo """,llfI.r output ping.Model 1540""Fig. 3-10. He.d .Iignment. Mode~ 1540 illld 1541.Flg.3.9. LOC

38 C1M1 TROUBLESHOOTING & REPAIR GUIDEdisk you choose is off, the alignment will be too.While most factory prerecorded disks are amazinglyaccurate, some can be off significantly. It is best touse a disk that has never been written to since thefactory recording. Even ilthe disk you choose Is offslightly. It will stillallow you to "flx" a disk drive thatis not working because of misalignment.FIg. 3-12. COl" eY" pOllern.lobes on the oscilloscope display are within90% of ea H). Then depress function key f1until the screen displays track No. 17. Verifythat the lobes on the oscilloscope display arewithin 90% of each other.16. Exit the program by depressing function key f4«SHIFT> f3).17. Adjust track No. 1510p by performing theprocedure In Section 3.4, "Track No.1 StopAdjustment," starting with step 1.3.3.2 Emergency or MakeshiftAlignmentThe procedure described here allows you toalign the read/write head using only a voltmeter.video detector (see Appendix B), Phillips SCT

AI~nmenlS9"Fig. 3-13. Loc~Uon of second video ~mplilier output pm,_Model 1540Flg.3.15. Heed ollgnmenl, Models 1540 ond 1541."fig. 3·14. LocMjon ot ..oond video amptllier Qulputplm,Mode" 1541 ~nd 154210. Insert the formatted disk that Is to be used as areference.11. Dep~ss lunction key f1 as many times asnecessary until the display Indicates trackNo.6.12. Loosen but do not remove the two screws thatsecure the stepping motor (Item 72). (SeeFig. 3-15 fo. Models 1540 and 1541 orFig. 3-1610' Model 1542.)13. Slowly rotate the stepping motorcounterclockwise (as vIewed from the bottom,or drive !>eM, sIde of the drive unit) whileFig. 3-16. Hud alignment. Model 1542.observing the voltmeter. You willnotice thatthe voltage Increases, peaks, then decreases.The correct setting for the stepping motor Isatthe peak. Tighten the two screws that securethe stepping motor housing

40 el541 TROUBLESHOOTING & REPAIR GUIDE14, Depress function key f2 «SH[FT> fl) tobring the head to track No, 1 stop.15. Depress function key fl once and the screenshould display track No. 1.5. Inspect trackNo.1 stop. [fthe stepping motor drive pulleyis not touching the track No.1 stop, omitsteps 16 through 18 and proceed dIrectlytostep 19.16. Depress function key fl as many times asnecessary untilthe screen displays trackNo. 16.17. Loosen but do not remove the two screws thatseCure the stepping motor (Item 72).18. Slowly rotate the stepping motor clockwisewhile observing the voltmeter. The voltmeterdisplay willdecrease, then Increase. peek,then decrease again, The correct selling forthe stepping motor Isat the peak. This muslnot be the same peak you observed in step13. Tighten the two screws that secure thestepping motor housing,19. Depress function key /2 « SHIFT> f1) tobring the read/write head to track No.1 stop.20. Note the voltmeter display at track No.1, thendepress function key fl Once and verily thatthe voltmeter display at track No.1 ,5 Is nogreater than 30% of that noted for trackNo. L21. Repeat the step 20 check lor tracks 2 through35.22, Depress function key f2 «SH[FT> 11) tobring the read/write head back to track No. 1.23. Adjust the track No.1 stop by per/onning theprocedure In Section 3.4, "Track No.1 StopAdjustment," starting with step 4,3." TRACK NO.1 STOPADJUSTMENTNever perform this procedure without first performingone of the procedures from Section 3.3.The following procedure does not include setupinformation, Setup is performed in procedure 3,3.1or 3.3.2. The above procedures also indicate whichstep to begin with below.1. Loosen the track No, 1 stop screw(sl(Fig. 3-17, Item 75). Loosen the track No.1stop so that It moves freely under the screw(s),~ODELS 1S40 I\. '~IMODEL '542Fig.3_17. Trad< No, t stop adju.tment.2. Verify that the oscilloscope dlsp[ays the125-Hz waveform shown In Fig, 3-18. Thiswaveform is at track No. I. If thle waveform Isnot present, depress function key fl or f3 asnecessary until the osclnosco~ displays the125-Hz waveform.3, Omil steps 4 through 6 and proceed dIrectlyto step 7.4. D.lpress function key f4 to eKlt the eKerciserprogram.5. Loosen the track No, 1 stop screw(s)(Fig. 3-17, Item 75). Loosen the track No.1stop so that it moves freely under the screw(s),6. Enter the follOWing command to seek trackNo.1'"Flg.3_18. T'.okNo.1portem,AI'PROX"-l

A~gnment 41OPEN 15.8,15,"I":OPEN 8,8.8,"N":PRINU15."U1:"8;O;1;17. Slide a O.006-inch feeler gauge Into the gap(Fig.3·17, Item 76). gently push track No.1stop against the feeler gauge, and tlghten thescrew(s).8. Verify the gap by sliding the feeler gauge Intothe gap. The feeler gauge should not bind,nor be loose.9. Tum off the Commodore 64IVIC 20.10. Tum off the disk drive and peripherals.11. Disconnect all test equipment from theVIC-154112. Disconnect all cables from the VIC·1541.13. Reassemble the V1C-1541 in accordance withSection 1.3.3.

----------

CHAPTER 4Preventive MaintenanceThis chapter provides instructions for day·to·day do's and don'ts for prolonging the lifeand Integrity of the VIC-1541 disk drive and5'i,·lnch floppy disks. Also Included Is Informationpertaining to cleaning the head and rllmoving dust.4.1 EXTENDING THE LIFEOF THE VIC-1541The VIC-1541 disk drive does not requll"

•• el54l TROUBLESHOOTING & REPAIR GUIDEflow more freely into the bottom cooUngventsof the VIC·I541.4. When practical, do not operate the VIC-1541in an environment above 25°C (78°F).5. Tum off the VIC-1541 when the Commodore64 or VIC 20 Is not In use.The VIC-1541 must also be kept free of Can·laminants. Dust and dirt can cause overheallngand unnecessary wear. Contaminants on the read/write head. or on the floppy disk can cause permanenthead damage or scratch the floppy disk, If thefloppy disk gets scratched, then data may be lost.The OXide coating at the edges of the scratch can bechipped off by the read/wrlle head and causeoXidedeposits on the read/write head,Dust In the drive unit can cause wear 01 movingparts. Also, dust On electronic parts can promoteoverheating by insulating the componentsand inhibitingtheir abilityto dissipate heat.Once every 12 months, you should removedust from the inside of the VIC-154L To do this,disllSSemble the VIC-1541 using the instructions inSection 1.3,1, "Disassembly and Identification ofSubassembUes." Use a soft brush to brush the dustfrom the internal parts, If you have compressed airaVailable, use nO more than 15 pSIof pressure toblow the dust off.Observe the follOWing precautions when removingdust from the VIC-1541:1. Do not bend component leads. Bending acomponent lead weakens it and causes it tobecome more brittle. Ifbent a few times In theSame place, the lead will break,2. Be careful when handling the drive unit. Thedrive unit Is vulnerable when removed fromthe protecllon of the VIC-1541's case. Beespecially carelul to avoid wrinkling the thinmetal track select band.3, Do not touch the read/write head. Oil fromyour finger gets Onthe head and collects dirt.4. Do not use strong solvents; if a solvent isnecessary, use denatured alcohol.Inspect the drive belt on the drive unit for signsof wear, Also, inspect all the disk drive's internalsubassemblies for signs 01 corrosion. If corrosion Ispresent, use denatured alcohol to clean off the corrosion.Also clean the read/write head folloWingthe Instructions In Section 4.3, "Cleaning theRead/Write Head." Reassemble the VIC-1541according to the instruCtions In Section 1.3.3,"Reassembly,"4.2 EXTENDING THE LIFEOf THE FWPPY DISKUse special Care when handling floppy disks inorder to prevent loss of data or even damage to theread/write head, When a floppy disk Ihat has dustor dirt On Ills inserted into the VIC_1541, Ihe contaminantscan be deposited On the read/writehead. Once these deposits are on the read/writehead they can scratch any floppy disk inserted intothe drive, even a clean one. Oocaglonally inspectyour disks for dirt, scratches, or warp, Don't forgetIhe bottom surface of the disk. This is the side onwhich the dala is written.Follow these guidelines lor prolonging Ihe lifeof a floppy disk:1. Always keep the floppy disk in Itspaperenvelope whenever it Is not in the disk drive.The envelope offers protection for theexposed areas of the media and also helpskeep the disk clean.2. Store disks In the vertical position, If disks arestacked honwntally the disk media cansometimes stick lnslde the jackel. When storedvertically, dirt may fall off the diSk.3. Do not .tore floppy disks In direct sunlight.Direct sunllght can warp the disk and crack Iheoxide CO

PI.ventlve Mointona""" 459, When labeling floppy disks, always write onthe label before applying it to the disk. Do notwrite on the disk jacket because pencils andpens indent the disk surface, therebydegrading disk performance.4.3 CLEANING THEREAD/WRITE HEADIt is important to keep the read/write headclean because deposits on the head can cause diskdamage and read/write errors. There are twomethods you may use to remove deposlls from theread/write head. One method requires a cleaningdisk (see Section 4.3.1). The second method is todisassemble the disk drive and clean the read/Writehead with a lint-free cloth and solvent (see Secllon4.3.2). Each method has its advantages and dlsad·vantages.The advantage of using a cleaning disk Is thatIt Is easy to use. On a cleaning disk, the media isreplaced by a cloth or chamois disk wet with sol·vent. Insert this disk In the disk drlve and rotate lorapproximately 30 seconds. The rotating disk mbsagainst the head and removes the deposits, Thedisadvantage 0/ thls method Is that the cleaningdIsk can pick up abraSive deposits from the head,which then pass over the read/write head approxi·mately 300 limes a minute. These deposits couldhave an adverse effect on the read/wrlte head.The above effect does not occur 1I you disassemblethe disk drive and clean the head manuaUy.Addllionally, this method allows you to see if all thedeposlls have been removed or If more cleaning isneeded. Unfortunately, manually cleaning the headInvolves a lot mare work than uslng a cleaning disk.A combination 01 these methods Is best. Typically,a cleaning disk should be used every monthwith a thorough manual head cleaning performedevery six months. [f your disk drive gels very beavyuse, clean the head more often. Perform the manualcleaning if the deposits on the head are causingscratching or data loss problems. A cleaning diskshould only be used for periodic cleaning. II a dirtyhead is causing problems, use the manual headcleaning method,4.3.1 Using Head Cleaning DisksTo dean the read/write head with a cleaningdisk, follow this procedure:1. Connect the VIC·I541 to the Commodore 64or VIC 20 serial bus.2. Connect the ec line cord between Itsconnector and an ec outlet.3. Tum on the V1C·I54I.4, Tum on the Commodore 64 or VIC 20,5, Load or enter the u!llily program 01Fig. 3·1into the Commodore 64 or VIC 20,6. Prepare the cleaning disk In accordance withthe manufacturer's instructions.7. Insert the cleaning disk into the disk drive.8. Run the utility program you entered In step 5.9. Depress function key 15 to start rotatingthe disk.10. Repeatedly depress lunctlon key 11at theapproximate rale 0/ two keystrokes persecond, ThiS keeps moving the read/writehead to a fresh surface of the cleaning disk,reducing the chance of abrasion from dirtalready removed from the disk.11. Alter approximately 30 seconds, stop thecleaning disk by depressing function key f7.12. Remove the cleaning disk.13. Exit the utility program by depressing functionkey f4 «SHIFT> 13).14. Allow plenty of time for solvents to evaporatebelore Inserting a floppy disk into theVIC-l54l.4.3.2 ManlLlllHeed CleaningTo clean the read/w,ite head manually youwill need the following mate,lals: lint·f'ee cloth orpiece of loam rubber, cleaning solvent such asdenatured alcohol or trichloroethylene, a PhllUpsscrewdriver, Proceed as follows:1, Remove the lie Unecord from the VIC-1541.2. Follow the instructions In Section 1.3.1 toremove the top cover, RFI shield, and diskcontroller PC board from the disk drive.3. To access the read/write head, gently liltup the pressure pad mount as Illustrated InFig. 4-1.4. Wet the lint-free cloth or foam rubber withsolvent.5. Gently rub the read/write head and pressurepad until deposits are no longer visible.

.6 elMI TROUBLESHOOTING & REPAIR GUIDE6, Allow all of the solvent to evaporate beforeproceeding.7. Release the pressure pad mount.S. Reassemble the VIC-1541 using theInstructions in Section 1.3.3, "Reassembly,"FIg. 4·1. Ac

CHAPTERSBasic Troubleshootingand RepairThis chapter covers most of the COmmon failuresof the VlC-1541 on a symptomaticbasis. This means we will start troubleshootingby identt/ylng a specific problem. Then we willlook for malfunctlons which can cause those specificproblems. Some malfunctions can be as ob­\lious as burned parts, a shorted conductor, orbroken wires. Other malfunCtions are mvtslble tothe naked eye, such as a faulty integrated circuit(IC) or a bad transistor. [n any e\/flnt, you must firstIdentify the problem In order to restore the diskdrive to operlltlon. Troubleshooting Is this processof finding the problem.5.1 INTRODUCTION TOTROUBLESHOOTINGWhen troubleshooting, there are some relativelysafe assumptions that you can make. Theseassumptions are proven to be fact In approXimately95% of the malfunctions that occur In theV[C-l541. These assumptions are:1. Assume only one problem exists. An exampfeof this is the symptom of the drive motor andthe stepping motor not turning. If you assumeonly one problem exists, then you know itmust be a ctrcuit of common use by both. Youalso know that it is not the drive motor andthe stepping motor. It Is not hkefy that bothmotors would fail at the same time. The onlye>

... Cl541 TROUBLESHOOTING & REPAIR GUIDEdrive's reectlcn during a lest and aft.... any ,..,pairactlon is attempted. Compa,.., these obseJVationswith the data that you recorded earlier. If the diskdrive exhibits any change In behavior, It could been Important clue to finding the bad part.Troubleshooting can be a long and tediousprocess. The purpose Isto find the bad parts. In thisquest It Is sometimes ellSY to overlook the goodparts. IIthe part Isgood, then this is not the part wea,.., looking for. II you cannot find the bad plll1,then look for the good parts. Usually when a persontroubleshoots a piece of electronic equipment,he or she starts out with two mental lists of parts.One Hst comprises "parts that could be bad." Theother list comprises "parts that are good." Unlessgiven a clue by the nature of the malfunCllons,most troubleshooting starts wHh all the parts In the"parts that could be bad" list. Gradually, the troubleshooterfinds circuits that work or determinesthat parts are good. These parts in the circuit aremoved from the "parts that could be bad" llst andplaced on the "parts that are good" list. When the"parts that could be bad" listhas one part left on it,that Is the bad part. Usually, when the "parts thatcould be bad" listgets down to a few items, the badpart Is obvious. Even IIyou have not yet found thebad part, lIS long as you are identifying good parts,you are making progress.Except for read/write head alignment, ourtroubleshooting In Chapter 5 wlll narrow the problemdown to a group of parts without the use of testequipment. This chapter assumes that you knowhow to solder, identify parts, and replace parts. Ifthis Is a new experience for you and you would likemore information concerning these skills, ,..,ad thefollowingbook:ElectronicPrototllpe Construcilon, bllStephenD. Kasten. Howard W. Sams& Co., 1983.(Cat. No. 21895)The troubleshooting Instructions in Section5.3, "Basic Troubleshooting Flowchart," will eithe,correct the malfunction or narrow down the list of"parts that might be bad." In addition to a parts list,Section 5.3 gives you s!!Veral options on how tofind the bad part. One of the options given is to followspecified instructions in Chapter 6, "AdvancedTroubleshooting and Repair." Although Section5.3 directs you to a specific section in Chapter 6,please ,..,ad Section 6.1, "Introduction to AdvancedTroubleshooting," before proceeding withthe flowchart In Section 6.2.5.2 IDENTIFYING APROBLEMThls troubleshooting procedure can be used tolocate and repair most common VIC-1541 mal·functions. For rare problems that requlre in-depthtesting, see Chapter 6, "Advanced Troubleshootingand Repair."Before you start the troubleshooting process,perform the following troubleshooting setup procedure:1. Tum off VIC-1541 and Commodore 640rVIC 20.2. Remove ac line cord from the VIC-154L3. Remove any serial bus cables from theVIC·154L4. Remove top cover and RFI shield folloWingthe instructions In Section 1.3,1.5. Connect the serial bus cable(s), which wereremoved In step 3, back to their respective""ceptacles.6. Install ac line cord between Itsconnector andan ac outlet.After this selup has been performed, followtheflowchlll1 In Section 5.3 to localize or Isolate aproblem. 11 the problem Is not Isolated, the flowchartwilllocalizethe malfunction to a particular circuitor group of circuits. The VIC-1541 may berepaired b!l ,eplaclng these parts. It may not benecessary to replace all of these parts. [f !Ioureplace only one plll1at a time, then check 10see ifthe problem Is solved after each replacement; youmight get lucky and replace the bad part on the firstattempt. Of COUrSe there Is always the possibilityofreplacing the bad part on the very last attempt. Inany event, you are no worse off than replactng allthe parts In question.It is eastest to ,..,place socketed [Cs first. If youhave spare ICs (6502, 6522, 6116, etc.I, now Isthe time to make good use of them. [f you knowthat these spares are in working order, you cansubstitute each of the spares for their socketedcounterparts. Check to see If the malfunction stillexists. 11 the problem has gone away, the last IC

BMic Trouble.hOOllng .nd Repol, 4'you changed was the faulty one. If you wish totroubleshoot the problem further, see the applicablesection in Chapter 6. The flowchart in Section 5.3indicates the specific section to see. Each group ofcircuits is identified in a table and/or a figure specifiedin the flowchart. Tables have three columnslabeled 1540, 1541, and 1542; the parts in questionare listed under the applicable column for themodel you are troubleshooting. Figures specified inthe flowchart ate three-part figures. Part A is lor the1540. part B is for the 1541, and part C is lor the1542. Faulty PC board parts are indicated on thesefigures. Use the part of the figure which Is applica·ble to the model you are troubleshooting. Beforeattempting troubleshooting, inspect the read/writehead for deposits and clean the head if necessary.See Section 4.3, "Cleaning the Read/WriteHead."

-_.----,--­,50 Cl541 mOUBLESHOOTlNG & REPAIR GUIDE5.3 BASIC TROUBLESHOOTINGFLOWCHART('''0TIPlaooVIC-'''' _ ....'toll I Table 5·l. F~ulty G",.n LED'0 on ,,"iI. o"o""n" thorOO aM .roon LEO,.FAULTYPART'S ONE OF mE FOllOWING:..t.. ,~'M'"UF:PI Fu.. Hold.,. >:PIT..n~ormor. T1 TransfrmOI. T1 T,,"sforme,. TlConno_,JI Coon.eI"', JI Conn,elot, JI1Pia"" v,c-..., powOr .""Oh., Bridga, CR3 13

B.s1CTroubleshooting ""d Ropalr 51(A) 1540,(B) 154]Fig. 5.1. Faully power supply

52 Cl541 TROUBLESHOOTING & REPAIR GUIDEie11542,Fig. 5-1.Faulty power ,upply (cont.l,rAI1540,Fig. 5-2. Fau~y red LED,

Baslc Troubleshooting and R~p.lrSS(B) 154le» 1542.Fig. 5-2. Faultyrod LEDkont.1.

54 Cl541 mOUBLESHOOTlNG & REPAIR GUIDE5.3 BASIC TROUBLESHOOTINGFLOWCHART (eont.)A Frm Page ~m~~" "".1oy d.",,,.,.., LEO,loy 00,Se' Tobl. ox;.M Fig. ~J,~>"''----J~ F.ully Compui" C'"olt.Aloo... S.ct'on ".'.5,F.ully Comp"., C"'ult.:000. rodlED ...PIi"~ioglo"" '_O,m.o," To.t' P"'1l"'" I,omVIC·O.mo 0'.. wn"" ,.'uoo"od w;'h'hO .,,"". Tn;, .,,,,,rom i, .1'0 "....In tho .ooondi. of iM ".,., moo"",aio'uPP"oO wllh t~o dl,k ""'0BToPag'07FAULTYPART IS ONE Of 11l:EFOlLOWING:,~'M',~IC, Uf2 IC.UOl ic um!C, UCD4 IC, UC2 IC. lJC2R_or, R36 Re~_R45 Roo"'", R45Rod LED Redl.ED Rod LWConn."'o,,1'6 Conno_,P6 Coonocto,. P6Conn."'or, J6 Con"_,J6 Coonocto,. J6

~c T,oubl..hooling and RepaIr 55rAJ 1540.rBJ 1541.Fig. 5·3. Fau~y compulo, drcu~.

56 Cl541 TROUBLESHOOTING & REPAIR GUIDEle/l542,Ftg. 5-3. Faulty computer circu~ (cont.).Table ~5.mE Pll.OIl1£M IS IN ONE Ofnrs FOU.OWlNG.,~'"',~MPu,UCD5 ~.= MPU. UC4VIA, UABl vn.txa VIA, UC3VIA. UCD4 ~.= VIA, UC2ROM. UAB5 ROM, UB4 ROM, UB4ROM. UAM ROM. U83 ROM, U83RAM, U83 RAM.UB2 RAM,lJB2RAM, UA3 IC.UC7 IC, UCBRAM, UB2 IC. UC6 IC, UC?RAM, UA2 IC. UC5 IC, UC5jc.uea IC. UAI IC, UAIIC.UB5 IC, UBI IC, UBlIC, UB? IC, UD3 IC, UD3IC. UCl IC, UD5 IC, UD5IC. UDl 00c111ot",. VI Oo

&83< T,oubleohooli"!j and Repair 575.3 BASIC TROUBLESHOOTINGFLOWCHART (coaL)B From P.go 54Soo ntllo 5...M FlO.5_"_lWr". Frotll.m. AI"" ...S",,"oo 5.2.3, F.,It, _NlrltoClreu".ClIO!< drive I, ",,'co••"."" pro"'om ...,t._Se. Tobl. 5-10010 Fig. 5_" 0,,,.Motcr P",bl.m. Al,o>eo Sectlcn••2.4, F""It, On,o MOI"'_l.OOIl or ontor """'y p'g",m1,.,0

58 CI541lROUBLESHOOl1NG & REPAIRGUIDE(A) 154()1811541.FIg. s.4. D~"" molOT problom.

&ole Troubleshooting and Rop

60 CI541 TROUBLESHOOTING & REPAIR GUIDETable S-7.Drlve Motde, CR14 Diodd.,CRlS Diod

Bosic Troubleshooting and Repair 61(/I) 154),(C)J542FIg. 5-5. Stepping motor problem {eont,).

62 Cl541 TROUBLESHOOTING & REPAIR GUIDE5.3 BASIC TROUBLESHOOTINGFLOWCHART (coat.)C F",m POllO 51Pe~",m p"","""", In &o

Bosio TfOlibl.sh""~ng ~nd R.polt 63IAJ 1540fBi 154J,Fig, 5·6. Rood/Wlile problem.

&4 Cl541 TROUBLESHOOTING & REPAIR GUIDEIC) l542.Fig. 5-6. Reod/write problem (oon•.).Table 5-9.DIE PROBLEM15 IN ONE OF TIlE FOllOWING:,~'M',~~,~ VIA, UC2 VIA, UC2IC.UE7 IC, UE6 IC. UE6IC.UE5 IC, UCI IC, OClIC,UF4 IC, U02 IC,002IC.UE3 IC, UF3 ic. UF3IC.UF3 !C, UF4 IC,UF4IC,UC! IC,UE4 lC,UE4IC,002 IC. UD3 IC, UD3IC, UC2 IC. UD4 IC,UMIC, UC3 IC.UAl IC, UJ\IIC, UDS T..".I

OO~~~~~~~~~~~~f~~~~~tt~~!!!ii~~i~i~ii~ii8"if·~·~·":'·"·"·"·":':':' :'.".".".".":' I~n~~~~g~~~~~~~~~~~~~~~ _ ~ ~ ~~~~~o~i~~i~J[rJ,f~~ooooooooo~~~~~~~~~~~~~~~~IIII~a~~~~~~~11liiiiiiii~~~~~?~~~[~ !•- - -- - - - _. ~~~~~~~~~~~ ~t£ggQ2~g~~~~~~~~~~~~ ~l'§IHHj'HUH000000000"""""1'1'11II~ii'l~i~~~~~:,J.J..22QOQROO~~~~~~t~~~~~,,- ~ "'.,-i~i"~HiHJ.~.~.~HII~~[[HI' II5"5"5"5"5"5"000""1;'00"'-"'-"'-"'-"'-"-~~-g-\1-g'll]]l1o;,

CHAPTER 6AdvancedTroubleshootingand RepairThis chapter contains advanced troubleshootinginstructions for your VIC-I541. If youhave nol attempted 10 troubleshoot yourVIC-I541 using Chapter 5, "Basic Troubleshoollngand Repair," please do so as that is prerequisite 10this chapter. Most common malfunctlons, such asmisalignment, are corrected by Chapter 5. However.If the malfunction Is caused by a faulty comp

•,. el541 TROUBLESHOOTING & REPAIR GUIDECl:Ise. the measurement is tllken between pin 2 ofintegrated circuit Ve2 and the cIrculi ground. It isimportant to know that the frame of the VIC·1541is not circuit ground. Circuit ground may be foundon pin 1 of connector P5,Once you are given a test point or componentto measure across, you may locate this componentby referring to Appendix A, Section A,4,"VIC-1541 Parts Layouts." Section A.I has an m­dex to help you locate the illustration pertaining tothe subassembly you are troubleshooting. If you arenot familiar with the pin numbering scheme of integratedcircUits,consult Appendix D.The flowcharts may list more than One set oftest points. An example of this is, "Measure voltageacross; R3 for Model 1540, or R4 for Models 1541and 1542." Be SUre to use the tnformation whichapplies to the particular model that you are troubleshooting.II only one set of lest points Is listed wlthoutmention of a model number, that test poIntapplies to aUmodels,6.2 ADVANCEDTROUBLESHOOTINGFLOWCHARTSThis section contains advanced troubleshootingflowcharts which are essentially a continuationof the flowchart in Section 5.3. Re"d Sections 5.2and 6,1 prior to performing the flowcharts whichfollow.6.2.1 Faulty Green LEDG,;",""'"" '

Advan",d T'oubleohootlnB .nd Rep.ir 6g6.2.2 Faulty Red LEDEotor !ollow

70 Cl541 11l.0UBLESHOOTING & REPAIR GUIDE6.2.2 Faulty Red LED(cont.)':~ , '>"'-+.I

Advan""d Troubleshooting .nd Repair 716.2.3 Faulty Power SupplyCO""n".~ ''''''' Ilow '.', "-1,4, 6,2.5 "nd'.2.7Uslni m""'m.'." mo""" V""Ia""'0'0; 065 fo, ",oo.,,~, '" ~lor Mod.l, ,~, & '''2,v1t"90"'w..nu,v&.,25v,'>-"'----->(o'c To _"". "u.lng mu"'m"a,. mooso",'o"sg. '''0'' C2,,,""tog."-'::>"''---~>(V00"'.00 f To Psg. 1311-" V l'2,5 Vu.,ng mu"lma'ar, moosu",'0."0.ac""" C14 10'"'Mel '''0,0'=''''"''''''',.,..,&,'''-'..0_ >"PP'Y""'" f.,,,,Cl>ock PC t>o>ard oo1hwoo1

7.1 elMl TROUBLESHOOTING& REPAIR GUIDE6.2.3 Faulty Power Supply (cont.)E From POQ ...".,Lotod PC_'":::>""-----J~ ""'"'"' ,~, 0' 02, ~3, or RoUalog mUlllmo"", moo""..1'

AdvaOCOld T,oubl..hooIing and RepaIr 'I,6.2.3 Faulty Power Supply [cont.))"'''-- - - - - - - -'li Fou" "•• 10U2, AI.., """".0''''''''.'"" PC 00.'" po"''''''",'''i~:'"C)>!''.'--__------'l{;;:~~~;:~~F.... II•• in .""en",,md"f,." i~ '0 '"o,r",,,,", T1 0'...""'.... wl!'ng

7. Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.3 Faulty Power Supply (cont.)Q F,om,,- 11"';0; mulUm.'"" m..,u,.vOllog. Be""''' CO2 I", M"".'15

Adoanced Tro~ble.hoolillg end RePfllt 756.2.4 Faulty Drive Motor< .."".10 '541 " 1!4l.oor

76 Cl541 TROUBLESHOOTING 8< REPAIR GUIDE6.2.4 Faulty DriveMotor (cont.)PFcomPogo75U"ng ma"""""'. m...,,,,volt.oo.t 0'" 12 of; UC~ I","'00., ,~~. 0' UC2fm MoO...'54' ~ 1542~F.ult 11._ In:UE2 10' ..Od.,"""" I,.. In:llC04 fO'"'_I"''logo"1~. '" UC;2 for .. """,.154' &>J.lI V 1542, ~I.o On"'....ao'.toO, OC_rO ","'t>work,m,~, 0' UC' for M"""" '"" &'~4.2, AI'o oneck...oe'"''PI;""'~ O.,"wo,k

Adv""cod TroubleohoOllng and Repair 776.2.4 Faulty Drive Motor (cont.)K f,om p.... 15Po,Io,," ""I. ",po 1,",,,,,go 5 of "",,,",,,."'n _""" 3,3.1, 5,,"PO.olll)' Align",."'.loed 0' ..,lor """l)'P'WrtI'" lIotoO In Soo1lenJ.l, E"",,,.I"lI '1>00,1,.Unit."'To Pogo 78"'Fo"" II•• In d~,. b.1t0< 111"\'...., boorlng.Using mull'motO'. m...ortloo"llOg.lIot_n lSI &E5 cl dri.. mOlo' .......ol,oult F'C"""'""'10\10 ">1.8 Voo,Fool' 110.In lO

78 Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.4 Faulty Drive Motor (cont.)u"ng m"ltlmotor, m...o".Olt"". bo'woo' E3 & E60'"ri•• moto,""0 01'00"PC board.",'0",It"""6.0 VdoYESu.,," mu"'mo'or, moOS"".oll.g. bo'w""" E. & EJ ,,'.rlva mot"r ••""oImul1PC """",,o,tag. " >",o'--__~ ~,n.>t1.0Vu"og m,ltlmOl.r. m...V",,oll.go botwoo" E2 & .301d,". motor •• "" OIm,"PC bo.,d.Fo.I, II•••" mol< _"0' 0''h. d'.....moto"'ooMmOl.ror .._I.tld ,,'MgF••lt 'I.. '" w','og "t_"~I,k 00011011., PC 00.", ondd,". mO'Of0""0 0Ir

Adu."cod Troubie.hoolin9 illld Repair 7'6.2.5 Faulty Stepping MotorFo,lt lI., 10_.r .uppl,

eo Cl541 TROUBlESHOOTING & REPAIR GUIDE6.2.5 Faulty Stepping Motor (cont.).. F,om POO" 10U.'ngmolllrr.otor........'""'''_''' P'" of u.2 'rModol1~, r 0'0 '.o! UC1 !o, M......1(,01,& '~02,..volto;'''- ->~ltilw

Advnn""d TroubJ..hooting&nd Repoir 8.6.2.5 Faulty Stepping Motor (cont.)tp F""" f>g,"'U.ing moiilm."" "",",..,.0IiO""" 01010' 3,6, & 6 01Pl.re~-"'~,4~.113 ,~moasorom.ni. R ToPog.8">l1.DVl'Whi,"plnh..• , ToP"", 83IO""MCi.."og.,TU,'n~ molilm01er, mo..."""'lOGo.., "'0" Of UF2,.,"'00"' '500,0' pin 0 Of U01'0' "'od.l, 1~\ & '542~F",," II.. in; UFO for "'''''''i.o".g. NO '~~." UO' i", "'00." '541< Iolk>",'n9 to"pol.... RCI1." 'lOpping moio' J?,pIno2&5 30_36 oh""""..t.",. o,lnO T.bi. &-1.J?,pl",2&630_36 oh""J?~I", 1 &2'"~o"";l'.....ano. " ., F",," il•• in ,jeooln~ I,""'o~.-y,~""moet mo'" Q' ...001....F."1t II•• In; OIl"" ",,,,,,i'''0,0' in Q10,,, "'_i, '5416154l. AI.. ohoc' ..'001....PC_m ~t"WO"'.

8. Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.5 Faulty Stepping Motor [eont.}P From_ 8'U.,ng m""lmol"" """"U'.VOl...... of; oln • of UF2 I",M""'" ''"'', ",pin 8 0' UO''",MOdolO '54' & '~012,F...~ II•• '"' UF2"" MoOol'10'0• .,.-uo, '0' Modol.l54,& '542. ~I,oc~""k ...ool.~PC 000'" po""''''''.0

Aduoneed T,.,uble,hocting and RepairU6.2.5 Faulty Stepping Motor (cont.)Q From Pog. e,U>lng m,ltimo'or, mo.,"",volt....." ~In 2 or UF....."'''''.''540. Of Plo '001 UO,for ..."""". '541& '542.F."" ,... 10; UF> 10' ~_,1541].0' UDI for ..."""".,..,&'5012. A'.., 0",,"" ""'0"'''''PC _rd oath""rI

... cisn TROUBLESHOOTING & REPAIR GUIDE6.2.5 Faulty Stepping Motor (cont.)p From Pac. ~,r>ejl,... funo"OOkOj I'".,,""'pt M,""C'OlI ,.."·PP'''IlmO'O,1~""Il mu'''m.'"" .......'·1''''lo\l. 01.'0' of Pl.,~vo""". YES r>'H"'lIo'ng mo",,,,,,t..-. m..o"••o'lo\l••t 0'" '0 of'VC,,", '0'"'oo., ,~, 0

6.2.5 FaultyStepping Motor(cont.)8 From Pog. !WFOIJlt no, 10:UFllOfModol ,&00, OfU01 10'>-'''----l''''_' 1~' & ,..,.AI•• "".0" 0""","'.'PC 1>QOo-' p","wo,..01.'00""'" J' 'rom .,.";>'''----->[;;::::~], "'""",""oo"eel

&6 C1541TROUBLESHOOTING & REPAIR GUIDE6.2.5 FaultyStepping Motor(cont.)>-'''----~c.o) To Pogo s"Poult 11., Inoornoul.'WCUL!, See S.ct;on U.e.F.ull. Oornout., CI,cult,I, Poult ".' ;0; UE~ 10< Mod.I'~""toge -,."'----->io' UC' 1o, Mod.l, 1&4' & ,\q,

AdvancedT""ubleshooting;md Rept>~ .76.2.5 Faulty Stepping Motor (cont.).. foul' ".. 'n; UF:2 I" .. ""., ,~, 0'""It"'·)--'''- ~UD' 10' """.'.'1;00' • '~2, A"ooo" ",o,".,.~ PC boool p"",wo'k.• cTum 011 VIC·1~',~.'""'" 00_, GOrd.Di..,ooo..,' J1 "om .'," ;>'''----->[:;;;=~::~l,osl.,,"oo"'''00',To.ooo as

.. Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.5 FaultyStepping Motor(cont.)Olocoo""", J. from Pl.F.u" ''*'" "'''PIlingmotor or ...",,'.1.0

Ad.anced Trooole,hooting OlldRepair .,6.2.5 Faulty Stepping Motor (cont.)P'om Pog.. 8lIo"'"">-"'----l.(,~ To F.... 80>-"'-----l~ F""n ,... in-' c"co".compoto'S.. ",",,!Ion 6.2.6,FoullyCompu'", C;

90 Cl541 TROUBLESHOOTING & REPAlRGlJIDE6.2.5 Faulty Stepping Motor (coot.)Ualng moll m.tor,m.....'. ,o".g••' pin3 01 P7F",,"ll•• In oomp"'.r-"'-__--;~

Advanced Troubu.shootlns and Rep"" 916.2.5 Faulty Stepping Motor (cont.)fault 11.0 In; UF2'0' "'_'15-"''-- - - ->1°,In UD1 '''' ...0..'-- ...,~fau'' '" "lop.'no mo""~ 0' 0',.... w""'OFaul' '... ,n, Q, '0' "'00." ..0.0'0"I", "'00.1. '541 & ,..2. A,"o oM"•...00,"',," l'

'2 Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.5 Faulty Stepping Motor (cont.)u"ng mu'''"",t.r. mooou",,",tago.t pin," 01; UCO. lorModol t5

Ad"anCCD< for101"".',540). 0' UC2for Moo."1!>1'& ""',.~F... " ,... '" oomp"IO' o"",,1tvolt"". 1+0 so. SocUon 6.2.6, F.u",>3.~ , " ComP"'''- C'",ult,'DU"ng muf'"mo'.r, m...u,.volt...., Fin 11 of; UC04 forMoo.. '5"", or UC2'0< Mod.'.'"'" ~ 1"'"~,o".g. NO>'-5V,'9u..'ng m.ltlmo'." mM'."",It_." pi" 1 01UE2 '0

!il4Cl541 TIl.OUBLESHOOTING & REPAIR GUIDE6.2.5 Faulty Stepping Motor (cont.)BB From Pog& 91u,'ng "'"''''''.'.', ""'.."ro,o',"g••" pIn 2 01 UF2'orModo' 154ll,0' pIn 10 Q' UDI'0' ",~.'541 & '54l,",'O'I'~>"'-_------>~

Advonced Tro~blv'hOling and ,",polrg56.2.5 Faulty Stepping Motor (cont.)TOo """olng mo'o, .",,0.,. '0...,'" .,o.',;oolly. 0>00. ,,,=:>-""----->1 '"~~~~o~~~~:;;ro~o~~, orreodl '''''0 ......u"ng m""lm"or, mOOS"re,o".go .. pin lG 01:\lC04 for'1"".1 '"'0, or UC2 '0< Modol,'(.I' & ,~..,NO" >-"''--------.j~:i\:::;::;;T~;:;;;;l,'",0'lagO>3-" VU.I"O m""'m.'." "",..ur.,01lOgo.. pi" 11 0" UC04 for'1""01'"'0. or uc2 10< Modol,,.., & '~42Fou" "0' 'n oomp"'.' 01"'"".SO3.5V~J

96 CI541 mOUBLESHOOTING & REPAIRGUIDE6.2.6 Faulty Computer ClrcuJtCOn""u" lrom """0.......'n 5o

Advon""d Troubleshooting ""d Rep.ir 976.2.6 Faulty Computer Circuit (cont.)DD F'om pago ..U.log I,mpor wlro, ,hoo1 m. 'O,""",'og plo, ,og",""r 00 lh."""....t 0'; U~Bl 'or Modol 'i\olO, Oruc, 10' Mod.I, '54' & ,..2Sl>o~ 0'. 11 to "'n'Shon 0;... to "'n'Not., Sock.' 0"0' mo, "" .no~OII ''-",v •F"It "0' 10:UC' for"'-''540. or UA'lor M"".'.'54' &,..2, ~"o oh.c< o'oo

,. el541 lll.QlJBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cant.)! FromPOQ.91uSing m"'ltmolor, mo...,",""00' at; p;n 5 01uG.210' Mo~.'1(,010,0'pin 2 01 UOO 10' "dog0 ~~S ot uoo "', "Odo', '541 & 15Cn.ddocprop" dovlce n.mber, Utho VIC·1Ml ~ not dovlce No.8. ,n.nchor>go Iho "8'"ln lIM 1 '0 9, 10, '"11, '" "!'Pk_. Then "RUN'"tn._om ogaln. U_ "umbo", oro coned. then too VIC-IM1

AdvoncodTroubleohoOllng end R..polr 996.2.6 Faulty Computer Circuit (cont.)FFFrom F...,••7Tu,n oil Vlc.'541.Jumo.' p;n. , & J 0' _.1 bu.'Q",'.'''o' IF' on "'_'1540, FJon "'od." 1~" & 1M2),_h.,.130. FI 0_'.•U,ln. m""'m.'o

100 cts-nTROUB1.ESHOO1lNG & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)~ From P'O. Il9U.I,," m""lmo'or. mooo"ro,Ollogo .t 0;" 6 01 UCl2 10'"""."0000, or p'n J 01 UOJ 10'3.~ V & ,~. AI.., 0"'" ...001....Fe"" 110"0: U01 10

A""onced TrtmbieohOllng ""d R"l'll!r 1016.2.6 Faulty Computer Circuit (cont.)H,"""_.."m~"m.."""""",,,""'" ,. , , '"""•• 01. U'",,,"""",.." "VCO""...,,,,, ,",',..~,.."""m.., ,~.... ~.. ,...,,""."' '0.",", ~od'""., .,..,,,,,,,,,0-,,,,." To_ '"

101 crso TROUBLESHOOTING s, REPAIR GUIDE6.2.6 Faulty Computer CJrcuit (com.)

Ad.""ood Trouble,hooting ond RePfllrM,,"01.'~1 &,~J,ITu,"""VIC-''''"U.'"g m,,,,molor, mo..uro>'

104 ctsar TROUBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)~ """'''''0'03Turo Of' v,c-'''''_~".mo,"lumoo' "ombo' .....noln. 13 • 20 00 .",,'" 01: UAB''0' M_"54O, orUCJ '0'.,_.. '54' "$42.,,,,.11602>10'''''''''00UA81 '0' .,""•• '54~,10,.,,,,,,,.,,,,,.'54>'" UCJTum onVIC·'''',j-U"oo mult'''''or,m...,,,,'O'Iaoo., p,

Advanced Troubleshool!ns ""d Rite 1056.2.6 Faulty Computer Circuit (cont.]MM F"'m P.go '04U>lng multlmotor, ",ouuro,o".g••" 0;0 12 01 UO' Fot"'''''01'1>00, or pi, 2 Of UB' 10'"_IO'I>O'&'I>O~..,,U,oltog.>MVNOF.u~ "•• In; VO', C5l\ R4a 0'CRl110t """"' '''0, or UP',Cole,A2S,or CAl lot """.1. , ..,a '''2. ~I.oo"""k ooooo..toojPC boud oatltwo~

106 elMI TROUBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)~ F

Adv

108 Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)ftR F,om Pogo '01A''''e' 0'0'"0"",," ""''''' to 0'" a o~ llCll to.MOO.'1500,'" U05 '0' MOO." '54' ~ ,10(2.000'''0'00'''' ,.ou'" d"p'.' • 'Gu." ......""•• ",,"00 of .pp","m.'o,,"2 no"o"",,,,,d.,Lo....' oo'n, 0' 'Ou"...... mu""" o

Advonc, &,r.>'1A"",," oo,"IIo,eo"""'_ '"pi, '0 "': UCO' 'm "'''''., '500.m UCO '0' "'00." '>0' & '"''To'" "" V,c-'54' """"",.",'"g"'011'"'0''' ...ploy, Ooo'"O""p••"",,,"."010, •'oo'e 'ow 1O'C oln 37 '"UCO, lor "'''''.' 'oco, '" UC4 "" M...", ..., • '54', 0..1110"""'••",,"I~,1t",o.,• oouo'" ""'''''''' ",,"od"' ',0mlO'OMoortO. ,""'." 001" 01'0'"'" ..,.,mu"" ~ Fau"I",'h: GM "" MOO" ,..."'" C" 'or MOO". '50' S ,&42,: AI'" onoc" .....,...0

110 Cl541 TROUBLESHOOTING &REPAIRGUIDE6.2.6 Faulty Computer Circuit (oont.)~ F,oo. P.o. '"In".11 lompo, ..,....n p'n,'" l , 00 .oek.' 01;ucoo ro

Advancod Troubkul>oollng ond RepairIII6.2.6 Faulty Computer Circuit (cant.)UU From PlIO" 110Tu,noff V'

112 Cl541 TROUBLESHOOTING & REI'AIR GUIDE6.2.6 Faulty Computer Circuit (coot.)~ f"'mP.... mTo,n 011 VIC154'_I~omove lumoor l'om bo1woon 0 100 ~ I& II00 .." ...t 01;ucoe lor "'_I154~, 0' Uc.o1o, "'OUV",""110'''_1'54.l., AI.., ,""'" oo_lotOJ.5V0' oor 10' Mo~.11M2., AI.o OM

Adv.nced Troubleshootlng ond Rep.ir 1136.2.6 FaultyComputerCircuit(cont.)IT",om P.g.,(l8T"m of'V'C"~'," ....",••, UCOI; foc ..0-'''- ~'54Il, or UC6"" """."1;4',OrUC7 for .._, '04.2.Also ohook...001.,,,,, PCboa'" P01~wo'k

••4Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.6 faulty Computer Circuit (cont.)'fY"KIm""",,""YES","'""'tao.-'''---''I,or ucefor MO3.5 V AI.o ch.c' • ...,.,'.1.~ PC? 000'" po'n"erlcFOUIt 110. 10; UB7 fOr MO

Adv""cod Troublo,he>tlng ""d Repair 1156.2.6 Faulty Computer Circuit (cont.)Foulll;.. In; UB7"" ..."".,",'-__~>I,'~o, .rUC6lor 101""."&4',," UC'fD'""",", 1&42....,.., 0000" o,"",,;.tod PC>"""'" pOl",,",'"""If"". '" >"""'--,

116 elMl TRQUIlU'SHOOllNG & REPAIRGUIDE6.2.6 Faulty Computer Circuit (cont.)MA F,omPo\lOS 1150'" 1>,;Fault II.. In; u88 10' """.1>-'''- ~'~...,. 0' UCT'0' "0~.1 1~1,0' U08 10' M"".11502,A'oo 0"""" 00""""'0-"'--------,1."~M~,u"ng multlm.'o011.110 0'p'n 1 01;Usa '0' "0~.1 ,~. '" UCI10

Ad.""cod Troubloohooting end RopalrII.,6.2.6 Faulty Computer Circuit (cont.)on 'C5 tOO' "'odol '~1. 0'l>C5"', "

118 elMI TROUBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)F.ul' II., 10:UBll lor 101-." >-"'-__-;~1(,4(), Of ucr 10' 1.10••1150\,';i'~i!; ~ 0' UQl 'Or 101-' 100.1 =rdo=~:~~""I",od I'C

Advancod Tmuble,hOtlng and Ropalr 1196.2.6 Faulty Computer Circuit (cont.)~o..lum"", trom""'w'.' p'",,'9& 21 on 10C'.' 0': uc~ !o'Mo

1&0 elM1 TROUBLESHOQTING& REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.)F.o't Ii.. 10:UBI for M",,",)-''->I'~OW,O'001 for MoOo' ''l4',. or uCH for _ .SU.Al,o oOo40, or UCO Ie' MDOO" '5-41 & ,..2,",t.II Nmoo' bot....n p;n, 22 & 8 on.ocl5'or "'000' '/>40, orUC-< 'or M_I" .., & ,~.,Turn en V'C-f'l4',oTo Pogo '"~

Advonced T,oublo$hootIng and Rep";, 1216.2.6 Faulty Computer Clrcult (cont.)TY'n oll Ylc-'541.Fa"" II.. In, usa '0' M""o'"''--- "" - - >1''''''.'"",UCSI",MgO>3" Y,NOU"ng Iy",oor w''', "'0" '00 lollowlngo"n. '''''.'.... 00 300k",of; UC0510r """., '5

122 Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.6 Faulty Computer Circuit (cont.),jJj F""" Pog. 12'",I'OI'....)-"'-

Advon""d Troublesl>ootlng ond R.pairIll!!6.2.6 FaultyComputer Circuit(cont.)Rom",o olljumpo, wlro••'",,"'1 0 ImOW" goo

124 crsei mOUBLESHOOTlNG& REPAIRGIJIDE6.2.6 Faulty Computer Circuit (cont.)A.ploco; U"B' '"' MMol''''O, QC

Advl>TlCed Troubleohoollng ""d RepairUill6.2.6 Faulty Computer Circuit (cont.)T",nonVIe-,Io4'.Rom... 00 IIno oord.Cl>oW

126 Cl541 TROUBLESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)'"p,,,,,,"m')"''-__~''''~E1000 .To P,g. '4(1'" .0S., up dua' ",,,. o",no.oop' 10 odOOh.M.,. A & D. In""" ,h.nOo' D. """'Meto~""",1 ~ 10 p" , 01: UH7 fo' Mo

Advon""d Troubleshooling ond Repolf 1176.2.7 Faulty Read/Write CircuU(cont.)From Pogo 128I. F""lt .... on,UFO klr Mod.1rolt.... )-""- >11040, or 001 fa' .. "" 11-11>3,5 V • & 1~. Al,o 0000 00101••? PC boo-"'--.. Faull ".. In: 002 forMoo.1~ 154ll. or UCl Po< t.I_,.1..'«I.B V ~ • '''2, AI.o 01' ..." ••"",,1.'",, PC llMtd po,h",,",",.011.~. '>-"'----------i>3.5V."•",n.voltog. )"''-->l0.0V.RRR To F.g.,28--'

11. Cl5411l1.OUBLESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)RRR Fr11.,.-- ~'!;«I. 0' CR'3. a7,VOI""O be"'O., .,.- Fto. 10< "'o~olo '5" ...O-l V ... ~.ll V ,~, AI." CI1,.,..._IotodPC boat-'''- ->1'5010,"rae !or "''''' ''4' &10 Fo." 11."0; a,o !o' "'''''.1

6.2.7 Faulty Read/Write Circuit (cont.)~ FlOmPogo 126Iu"ng moltL_.,. m...ufO'Ollagj IaclOOo; ~'T 10' MMOI1~O, 0' ~'6'Of "''''''.'0'''' & '(,

I!IOCl541 TROUBLESHOOTING &REPAlRGUIDE6.2.7 Faulty Read/Write Circuit (cont.)TTTF,om • ...,o'2Ilw"""form"""!r;clon'om~II'"'. ,~Sot oocIUo,oop. co,",,,, fO' ,""gl. "000.,..."tloO, SYNC ""

Advanced Tmub ...hoollng and RepoirlSI6.2.7 Faulty Read/Write Circuit (cont.)Al..mo' '0 1000·oorto""""",, ,...," "hlloO",""'ing _11100eIA "); p'n'01002 tor "'-. '5-lO. or pln'2 orUD3lor "'''''." '50' & 1'""',Alt.mo' '0 '''"'' ·oorlot,.,.."co ..". wlliloob.o,,'ng OKU...oooo dl,.'O\I, V.,IIy ,no,oKlllo,oo,," "IOOl&y, 0 "~1101 "gn.' """",""." 00'.' "

IsaCl541 TROUBlESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)"",m,' to 10'0 ·0

Ad'laO, OCY" Lt, U""",,,,,, C'O. Cl1. C12, C1" or ClO 10'lr""" • to pin°'°"'''"''00 12 0': UEI '0' MOOoIl!;41l. 0'uEll '0' Modol.1(,o11 & '5

IS"cisn TROUBLESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (oont.)~ ',om P>g, '"V"Ir, ",., 000

Mv.need TTCublEshooting ""d Rep... 1356.2.7 Faulty Read/Write Circuit [conr.]VY'IF",m Pog.'34V.,LIy'ho' 0"""''''''0,", d'opl.... p'lS'which cocu....,o,o~f."" II•• In; UE' '0') 11'''''.1 f"O, or uEti lor.. _ .. ,..' &15

UliCl541 TROUBlESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)zzzF,om Pog.'35Fou" ..a, 'n UF4. l ....';>-,,'-__--i~.nd "'" 'oortOrnlOOOO... t..,· to dOlo,,,,'",..",'c..b'"t,.­.""""f,,

AdvBn""d TlOub!eshOOllngBnd Repair 1376.2.7 Faulty Read/Write Circuit (cont.)AAAAfm", p,., ,:l-"'----l~and '"" .po_"'.o

us Cl541lROUBLESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)~ F'OOl Pog. '37Tv," 0" VIC'M',Ro",o.. ac ""o

Advonced Troubleohoonngand fWpalr 1396.2.7 Faulty Read/Write Circuit (cont.)ecceFmm PO,," 13IlTern olf VIC·,!>I"Ron"",o oc Itn" oor

140 Cl541 TROUBlESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (cont.)lEEEFrom Paga "'"FIomo.. .," m".'"",,,".Fo," II.. " ",,"e de""'"-"'---l, c~, & 01 0' ."'" ",",Aloe>cooaO .,,,,,,I.t.. ,,","gond PC _"' ."h",,'.T"m on VIC''''.FIomo,,", ucoa ""_ul "40. 0' UC2'0'M""u,. ,.., & ,....She" thu 'e'''''''',g Olos'0,,"'""' 00 ,••""',., "'; lICoa ''''"""., '''0. a,UC' ,,,MoOul.,!., & ' .."81>0110'''''''&'SI>oI10''''' '!"81>011 p'"" ,."~o,"' sea..,

AdvancedTrubla'hoollng and Repair 1416.2.7 FllIJlty Read/Write Circuit (cont.)FFfF From P"". "0Tum.,., VIC.l54'," F.u't "."0, UO"or Mod.1 '540,volt.... ~-""-__->~ '"U0210r Mod." 1&0' & ,..,.

14SCl541 TROUBLESHOOTING & REPAIR GUIDE6.2.7 Faulty Read/Write Circuit (coot.)~--.. F"",t "•• 1.' Q3 orCR121Q! MOdO'dI"',ofl...''''0, '" I. OTor CR13for Mooo"Hi., • , ..... ""0 chock ...eeloted." ; PC_rO ..'h"",k.".'~lIrgmU",m...r,mo..u", 'o"ogo ""ro,~_'m ModOI1",0,",R5;!lor Modo" 1041•,..2,4?,",".og.F"""" •• 'n; Q10 '''' MO

Advonced T'OUbleshooting ""d RepairI.'6.2.7 Faulty Read/Write Circuit (cont.)~ FrOOl Pogo 142ICo"oo' ,,"o'lIo,ewe "'00.10' , I"".nn.' .. 1000"""'0' "', a1' I",,,"od.,11.40, 0,a41N Moo.,. "41& 11.42.V.nf, ,.., ''''''''0,",00. d"o'''''' • w".'o,,",;mlla' '0 'hal ,"own In Fig,6-5. H;gh'" po;n'of w...lo,," muo' •• g......,... Ih.n + 11.~ V.nO'0.10....' po'n' """,,~ 1>0 mo,. r>og''''. 'h.n_'.av.J.~.w.",'"""con." ,I Tum 0""VIC·1~1,""mov••o 1In

144 elM1 TROUBLESHOOTlNG& REPAIR GUIOE6.2.7 Faulty Read/Write Circuit (cont.)6.2.8 Blown Fuses(f""""""" 110m ,,_oat,'n ""c""" 5.3.~~;::';l:~b~i::"~o'"I""••,. F' w""",.0 ~ f",o.O,"ooon",t J1 f""" P'.....I \':,~::'6:Cv:~~;'~rd.IW.lt:llJ_oM,I ~~~ oc 't:~~OrdI ~"~~ on~ fn._III,4foo" ~ Fault II.. In "onoform.r00. Tl or...""f.,.~ wfrlnmFault fi.. fn Ul, Ul, CRl, CR:!, Cf, or04.Fault moyOlIO'"' In; C". C6.2 lor"lod.I, f~oIQ, or C'S & CIT for ,,"od.l.'(,011 & ,~.2. ~IIO

CHAPTER 7Advanced Theoryof OperationThis chapter provides the fourth level of theoryof operation, discussed on the componentlevel using the circuit schematic.Section 7.1 covers Model 1540 and Section 7.2covers Model 1541. Because Model 1542 Isso similarto Model 1541, Section 7.3 only points out theminor differences between Models 1541 and 1542.If you are troubleshooting Model 1542, read Sections7.2 and 7.3.7.1 ADVANCED THEORY.MODEL 15401.1.1 Frame Electrical Theory(Refer to Figs, 7·1 and 7·2)The electrical tuncticn of the frame assembly isto condition and convert the ec bne voltage beforeapplying It to the power supply on the disk controllerPC board.The ac line voltage enters the disk drive at J9,which is both a connector and an RFI filter. Afterpassing through the flIter, the ec voltage is appliedto the SPST power switch, S1. The output of thepower switch Is applied to Fl, which providesovercUJTent protection. Flis a t-emcee, 250·voltslow blow fuse. The output of Fl ls fed to the transformer,11. Tl steps down the ac tine voltage Intoies9 volts ac lind 16 volts ec. Both of these outputshave their own secondary windings and are isolatedfrom each other.,,","fig. 1_1. Block diagram of frame assembly. Moo.II540.1.1.2 Power Supply ElectricalTheory (Refer to Figs, 1-3 and 7.4)",-"''NO,,,..". '" .,''''''''',00--',-,,,- "Fig. 1·2. Schemal!c offrame .....mbly, Mod.11540The VIC-1541 power supply produces tworegulated voltges, +12 volts de lind +5 volts de.These volta!!"s are derived, respectively, from the16 volts ac and 9 volts ac supplied by the frameassembly. The power supply, located on the diskcontroller PC board, has a rebability switch whichremOves power from the write amplifiers in the

.46 CI541 1ll.OUBLESHOOTING & REPAIR GUIDE••."-,..... ,""". . """" @., . .1~-I~" .."' ,..", ..., .'," .." .., I"....'" • .",1~;f I!JJ.'I~-·~··--~1. . • .r" rUb- I'.I, IiI:.r-+"•,. '"'FIg. 7·3. Schematic oIpow.r luW1y. Modal 1540.~+-".Fig. 7-4.event of a +5-volt failure or during power up/down. Thus, the reliability switch protects the dataon the floppy disk by disabling the write amplifierswhenever the +5-voltllne goes below 3.9 volls.7.1.2..1 +12. VoltsDCSixteen volls ac Is applied to the power supplyvia pins I and 4 of PI. From PI, the ec power Isapplied to bridge rectifier CRI. CRI rectifies (fuJiwave) the 16 vchs ac to produce approximately+21 volts dc. The output of the rectlfler is appliedto a filter consisting of CI and CSI, which smoothsout the pulsating dc from CRI. The output of thefilter Is applied to U2, a + 12-volt regulator. Theoutput of U2 Is the regulated + 12 volts dc outputof the power supply. C2, C62, and C3 reduce linenoise, and CR2 protects the regulator against negativevoltage excursions during power up/down.Block diagram ofpowar supply, Mod.ll5407.1.2.2 +5VoI!5DCThe + 5-volt leg of the power supply operatesin the same fashion as the + 12-1I01t leg, the onlydifference between them is in voltage levels. Ninevolts ac Is applied to the power supply via pins 2and 3 of PI. The ac power is applied to bridgerectifier CR3. After redification, the resulting + 10volts dc Is filtered by C4 and C52 before It Isapplied to the +5-volt regulator, U1. The output ofUIIs the regulated +5 volts de output of the powersupply. Both C5 and C65 reduce line noise andCR4 protects the regulator against negative voltageexcursions during power up/down.7.1.2.3 RellabUtty SwitchThe reliabIlity switch consists of Ql,Q2, CRS,and associated components. Q2 and CR5 form acomparator. When the +5'volt line exceeds +3.9

Advan""d Tn-ory of Opor

1.. Cl541 TROUBl.ESHOOTlNG & REPAIR GUIDEbe controUed. Floppy disks have fewer sectors pertrack on the innermost track (track No, 35) than onlhe outermost track (track No. 1~. This variation innumber of sectors per !rack keeps the bit densityfairly constant throughoul the wriling surface of thedisk. Each disk is further divided into lour zones,with each zone containing a unique number of sec·tors per track. The programmable divider has fourpossible output frequencies, with each frequencycorresponding 10 one 01 the four zones on thefloppy disk. In order to maintain lalrly even bit den·sitles, the encoder/decoder must be clocked at afaster rate when wrtting on the outer tracks thanwhen writing on the inner tracks, This is becausethe outer surface 01 the disk is passing Over thehead more quickly than the Inner surface, Thus, itis the encoder/decoder clock that determines howmany sectors willfit on any given track.The division factor of the programmable di·vider is controlled by the CLOCK SEL A andCLOCK SEL B lines. Table 7-1 defines parameterslor each zone. The programmable divider consistsof UE7, UE5C, and UE5D. UE7 is configured as apresetlable 4-bit binary up counter. The output 01UE7 Is taken off pin 12, the TC output. The TCoutput (active low terminal counU goes low whenthe counter overflows from 1111(21 to OOOO(2). Thisactive low pulse Is Inverted by UE5C, producing apositive pulse. The output of UE5C Is applied toUE5D and to the encoder/decoder circuit, Theoutput of UE5D Is an active low pulse that Isapplied to the load input of the presetlable counter.When the load input goes low, the counter is presetto the values present on the A, B, C, and D lines.The C and D lines are strapped low and thereforeeach hne is set to 0. If the A and B lines are bothlow (zone 4 condition). the counter Is preset to0000(21' Sixteen counts later the load line will resetthe counter to 0000(2). [f the A line only Is a logic 1(zone 3 condition), the counter is preset to 0001(21and 15 counts later the load line wID again presetthe counter to 00011Z). Note that only 15 countswere required, since the counter had a head start ofone count. If the B line only is a logic 1 (zone 2condition), the counter Is preset to 0010(Zl' Thecounter now has a head start of two counts and willrequire only 14 counts before it is preset again. IIboth the A and B lines are at logic 1 (zone 1 condition).the counter Is preset to OOlllZ). The counternow has a head start of three counts and will requireonly 13 counts before it is preset again.Table 1·1.Timing Clroui! P..,amet""ZONEl ZONE! ZONE. ZONEtCLOCK8EL A c • oCLOCK SEL B• • o cDMokonFOCIo, rais reEn

Adoonced Theo:y 01O",,'oIion .49SEA'AL·~~=-~f::::-;:-_lClOCOOATAS€O...l "V"'.H"FAct".i •• 0'rate at which the microprocessor executes Instructionsls determined by the 1 clock present at pin 37of UCD5. The 1 clock ls produced by the timingcircuits (refer to Sectlon 7.1.3, 'Timing ElectricalTheory"), The microprocessor In turn produces aninverted, nonoverlapping dock signal (Le., 2) fromthe 1 clock. The 2 signalls present at pin 39 ofUCDS. Two NOT gates, UB6A and UB6B, bufferthe 2 clock before it is sent to the VIAs (UCD4and UABl) and to the write logic. The 2 slgnallsused to synchroni2e write oper1ltlons; therefore, theROM does not require the 2 signalThe nonmaskable Interrupt (NMI, UCD5, pin6) is disabled by R23 and ls not used. The readyline (RDY, UCD5, pin 2) ls held at a logic hIgh byR22 and also is not used.There are three lines entering the microproces·sor that allow hardware devices In the VIC·I541to change the sequence of instructions executedby UCD5, These Unes are: set overflew (SO, pin38), Interrupt request (IRQ, pin 4), and reset (R5T,pin 40). When the set ovetflow ~ne goes high, itsets the overflow bit in the status register internalto UCD5. The sequence of instructions may bechanged by testing the overflow flag using the BVC(branch if overllow clear) or BV5 (branch If over·flow set) instructions.When the interrupt request line goes low, themicroprocessor calls the subroutine whose startingaddress is stored !It loc"tions FFFE1hsxJ (low byte)and FFFF1,,",,1 (high byte). FFFElhn) contains FE 1 ...)FIg. 7·7. Block di"ll'Offi 01 oompv"" C~C"!t, Mod.ll540,and FFFF1hoo(} contains 67Ih.,.)· These two bytes formthe 16-bit address FE67!h.>

150 Cl541 TROUBLESHOOTING & REPAIR GUIDEP3.9EJU,L1IUSSERCI(IIOSE:RATN1/0!EROAT"110Arn'I'SEA SAQ INGNO'""'. SERIAL BUSSER Q( 110 ......,. '~+=~JSER A'NM) 3SERDATA 1/0 5SER SAO IN 1 t-GND 2uaR32LOIC»ev."I.OKUClF~'MLS14I'"'V""12----------------+-,.4·--------+--,UOIC'J67~"'--_'"V'.:~~.-'-t>.'L-r' UG28UOUIUC~11614L.S14*7 I'" 74LSlI6 11'6 740603'1.0K1-.... ..... 2~ Iuc"'''7'''''''-t>o-21m~~~~~~lJ'67406ElNO'"E2NO'"+ C..IIOO llF'.. 11iVI20•U'"981229-01810(1 ROM~:c~:!:~:I~~:Vo2114L311

T20Advanced Theory 01Operation 151--40 CAl vee rnCA2DOcoo .,::m~~,... VIA 04.........oe.6...e .'IISO~M RStPA7 RS2AS3 --10 P80--II Pli CSt--12 Pe2--13 Pi] RIW--t~ F'B" 1M--IS P8S '2--0 ... ""--17 PS? V.CLOCK SEL ACLOCK SEL BI.+.so,.,-++I--f-----....+-_liVfE1iYiiC IYTE SYNC,. IN >7"'OS6S02s., ao« :S.OKUV + v + V. ~E181TW\J R" 02' """'" ,-R.V ecirculi, Model 1540.

152 Cl541 TROUBLESHOOTING & REPAIR GUIDEOOOO-OOFFOIOO-01FFThe zero page contalns variables, pointers, andother data used by the DOS. The mlcroprocessorstack is used for lemporary storage of data.When the MPU writes to the RAM, the data tobe written Is placed on the dllta bus (DO throughD7J, the location that the dllta is to be written Into isplaced on the address bus (AO through AI5). andthe WE (write enable) and CS (chip select) lines arebrought low. When the MPU reads from the RAM,the location to be read is plllced on the address bus(AO through A15) and the CS line Is brought low.Data Is then gated from the RAM to the data bus{DO through D71.7.1.4.4 Addr_DecoderThe address d""",der selects one of the deviceslisted In Table 7-2 when the address bus containsan address within the address range of the device.UB7B, UB7C, and UB7D decode the ROM lowand ROM hIgh addresses. UB7C is configured as aNOT gale, which inverts AI3 before it is applied toUB7D. UB7D enables UAB4, the low ROM, whenAl5 = logle 1 and AI3 = logic I. UB7B enablesUAB5, the high ROM, when AI5 = logic 1 andAI3 = logic 1. AO through AI2 are decoded bythe selected high or low ROM, Notice that AI4 isnot decoded, and n theretore does not affect theoperation of the decoder. The end resuk is twoidentical 16K blocks of ROM. Each of the ROMchips has two valid address ranges. One range isused wlth AI4 = logic 1 as in Table 7·3.Table 7.1.DEVICERAM, Low IUB2 8

Advancro Theory of Oper.~on 153put Is used to select the high RAM palr. Table 7-4illustrates the RAM address range, The 2 through 5outputs of UBB are not used. With four imagesbeing produced, this leaves the following locationsnot addressing any devkes: 0800-17FF 1ho , ), 2800­37FF{hnj, 4800-57FF 1 ..." and 6800- 77FF II ""'I.Tllbt~ 7·4.RAM Im"9~'A13 - O. 1\l3 _ 1. AI3=O, A13_ I,A14~O A14~ 0 A14~ 1 A14~ IOOClO-03ff 2000-23fF 4000_43FF 6000·63fFRAM. -~ High O4(IO_07ff 2400-Z7fF 4400-47FF 6400·b4FFThe 6 output 01 UB8 enables the serial busVIA, UAB1 Notice that UAB1 decodes AOthrough A3. A4 through A9 are not decoded,again producing redundant images. There are 64Images of the 16 VIA registers In the 1024·byteblock enabled by UB8, There are IIlsofOllr imagesof each lO24-byte block thai Is selected. This givesa total of 256 images of the VIA registers. Typically,lhe serial bus registers are accessed at 1800­180F 1 ...,) by the DOS.The 7 output of UBB is used to enable the diskcontroller VIA, UCD4. Again, this VIA has a totalof 256 redundant images. Typically, the disk controllerVIA is accessed at 1COO-ICOF n""1 by theDOS.7.1.4.5 Write LogtcUB6C and UB7A form the write logic circuit.UB6C Inverts the R!W (read/write) line from pin34 of UCD5. The output of UB6C will be high duringa write cycle and .....ill be applied to the NANDgate UB7A together with the 2 signlll from UB6B.The output 01 UB7A drives the WE (write enable)lines on the RAM chips UB2, UB3, UA2, andUA3. The write logic lor the ViAs Is Inlernlll to theVIAs. Therefore, the R/W line and the 2 signalare applied directly to the VIA chips,7.1.4.6 Serial B...The serial bus circuits consist of UAB1, UG2B,UDl, UClA, UC1B, UCIE, UC1F, and associatedcomponents, The serial bus circuits interiacethe computer .....ith the serial bus and allow theVIC-1541 to communicate with the VIC 20/Commodore64. The serial bus circuits also control thereset line for the VIC-1541 computer,When power is first applied 10 the VIC-l54l.C56 is in II dlschllrged stale. producing a logic 0 atthe Input of UDIE, This makes lhe oulput of UDIEa logic I, which is applied to pin 9 of UD1D. Theresulting logic 0 out of UDID drives the reset linefor UABI, UCD4, and UCD5, causing them toassume their Initialized states. After a short period'01 time. C56 ..... 111 be charged through R43. up tothe logic threshold of UDIE. This causes the output01 UD1E to change states. In turn, UD1D changesstates and places the reset line high, allowing thecomputer to start execution of the DOS. If the VIC20/Commodore 64 is reset, the reset line on theserial bus (pin 6 of P3 and P4) willgo low (logic 0).This logic 0 is inverted by UCIE and applied a. alogic 1 to the Input of UD1F, which discharges C56to a logic O.Subsequent action of the reset clrcuit Isas described earlier. CR 17 Is provided to dischargeC56 If po .....er is momentarily removed from theVIC-154l. The reset circuits are active only duringpower-up of the VIC-1541 or the VIC 20/Commodore64The VIC-1541 serial bus is simllario the IEEE­488 bus (also known as GPIB Or HPIB), but It isslower and does not use some of the control signals.Like the IEEE-488 bus. the VIC-1541 busmay be interfaced with several peripherals, eachhaving a unique address. All the peripherals aredaisy-chained together. Daisy"chalnlng means lheflrsl peripheral is connected to the computer, thesecond peripheral is connected to the first. thethird peripheral is connected to the second, and soon, Daisy-chaining Is the reason the two serial busconnectors, P3 and P4, are wired in parallel. Theusers of the bus (e.g., VIC 20/Commodore 64,VIC-1541, printers) clln be divided into threegroups according to their actiVities at any giveninstant: controll.... talker, and listener.Only the VIC 20/Commodore 64 may be acontroller, talker, and a listener. The peripheralsmay either be talkers or listeners. The controllerdictates bus commllnds to the peripherals which tellthe addressed device whether to talk, listen, untalk.or unltsten, These bus commands are:Talk-Addresses a specific device andInstructs the device to prepare to send data,Untalk-AddreSSl!d device is instructed tocease transmissions.Listen-Addressed device is Instructed toprepare to receive data.Unlisten-Addressed device is instructed to

15. cisn TROUBLESHOOTING & REPAIR GUIDEignore any further data transmissions. Dellicewin walt for next command.These bus commands are sent as an 8-bItbyte,Five of the bits are used for the address and theothers are used for the command deflnillon. A totalof 28 devices may be addressed by the selial bus.However, even though the address range of theserial bus Is 4 through 31, it can only drive fiveloads at any gillen time.CAUTIONConnecttng more than f1~ devlcee to thesertai bu. could ,e.ult in permanent damage tothe .......1bus circuits.Applicable bus signals used by Ille VIC·I54Iare:SER CK-Primarlly used to indicate that dataIs lIalid on the serial data lme. Also used as aready-to-send signal.SER DATA~PrImar11yused to carry data bits.Alsoused as cleared to send, EOI&clmowledge, and handshaking slgnal.SER ATN-When false, serial data containsdata to be transferred. When active, It Indicatesthat the data bus contains a command. Onlythe controller may drive this tine.All of these signals are actIlle low signals. Thesignal tines are driven by open ooIledor outputs, allowingall the peripherals to be write-ORable. ThatIs, any or all of the devices may drille the bus linesat the same time. If any devtce pulls a bus lineeceve (low), the resuh will be an active line. Inorder for a Une to be mecnve (high), all peripheralsmust release the line to high.Refer to FIg. 7-9 lor a typical data transmissionslgnaL PrIor to TO, the bus Is In Its s1andby state,the serial dock line Is held low by the talker, andthe data line Is held low by the listener. The SERATN line Is high, Indicating the transmission to takeplace Is data rather than a command. At TO, thetalker signals "ready to send" by releaslng the clocktine. At n, the listener acknowledges the "ready tosend" by slgnating "clear to send." The listener slg·nels "clear to send" by releasing the clock line to alogic high. If the listener Is busy, It will not slgnal"clear to send." The time between TO and Tl Isundefined and Is determined by the listener. Within200 microseconds, the talker pulls the clock tinelow at T2. At some time between T2 and T3, thetalker places Ihe least significant blt on the SERDATA line. Since the bus Unes are actille low, thedata appears Inverted. That Is, a low represents a"true" bit. At T3, the clock line is released 10 logic1, Indicating to the listener that the data bit on theSER DATA line Is valid. The talker holds this conditionuntil T4, where the talker releases the dataline to a logic I and pulls the dock Une low. Thissequence continues until TIB. After docking In themost significant bit at TI7, the talker once againpulls the clock line low and releases the data line atTIB. Now the talker is wailing for the handshakesignal which occurs at TI9. At TI9, the listenerpulls the data line low. After TI9, the serial bus isback In ils standby condition, as it was prior to TO,Throughoulthe transmission of this byte, the talkerkeeps control of the clock line, The talker has"....0«"~-r ,,,,o~ ,,,,, , , , , , , , , , , , , , , , ,TO T' " T> T' " T< " f, " "" T" flO. To> T14 TO' "., , , """"""',+- - - - -i' , , , , , " ",."" , ,r----7i'~,II.

control of the dlltll bus from T2 to TlS only. Therest of the time the listener uses the data line forhandshaking. Datil transfers continue In this fashionuntil the IllS! byte to be transferred. The last byte tobe transferred contllins "end or identify" handshaking.The handshaking signal for "end or identify"takes place between Tland T2 (refer to Fig. 7-10for "end or identify" Information). The talker signals"end or identify" by not pulhng the clock nne lowfor at least 200 microseconds. After approximately200 microseconds, the l!stener acknowledges the"end or identify" at TIA by pulling the serial dataHne low, At TlB, the listener releases the SERDATA line to logic 1, Informing the talker to transmitthe last byte. At T2, the talker pulls the clockUne low and the byte Is transmitted. At some timeafter Tl9, the talker and the listener release theclock and doto lines, respectively, These actionsoccur at T20.A bus command is transmitted In the samemanner lIS bus data, except that the SER ATN hneis pulled low during the transmlsslon. When a buscommand is being transferred, the VIC 20/Commodore64 is the bus controller ond oll the peripheralson the Une become Usteners. After the buscommand, a secondary address moy also appear.The secondary address is optional and is used tocontrol and specify a subchanneL After the buscommand is issued, the addressed device assumesthe role Issued by the bus command. Usually, theVIC 20/Commodore 64 assumes the oppositerole. For example, if a talk command is Issued, thecomputer lISSumes the role of the l1stener. All thedevices in the bus that are not involved wtth thetransfer of date release control of the bus hnes andawait the next command (I.e.. SER ATN pulledlow). It is possible for the controller k> issue a l!stencommand to one peripheral and a talk commandto another peripheral, causing data to be trensferredbetween two peripherals while the VIC 20/Commodore 64 is free to perform other tasks.Such a possibility Is dillicult to accomplish, but theVIC-I541 bus Iscapable of doing so.UCIF Is the Une receiver for the sertal clockline. The output of UC IF is entered into the sertalbus VIA, UABl. When the VIC-I54l is a talker, ittakes control of the serial clock line using port B, bit3 (pIn 13, UABl) of the seriol bus VIA. When pin13 of UABI goes high, UDIC pulls the clock lineactive. UDI has open collector outputs.UClA is the line receiver for the SER DATAline. The data is Inverted and applied to the serialbus VIA. The SER DATA line is driven in the writemode by t,lDIA, The serial-to-parlllleland paralleltc-senelconversions are performed by the software.UCIB is the line receiver for the SER ATNline. The output of UCIB is applied to pin 40 ofUABl, generating an interrupt to the computer,The output is also applied to pin 17 to allow thecomputer to sample the state of the SER ATNUne. When the SER ATN line is active, the SERDATA Uneis pulled low by UG2B and UDIB. TheVlC·I541 releases the data Une by using the otherInput (pin 4) of the Exclusive OR gate, UG2B,El and E2 set the address of the VIC-I541,Refer to Chapter 1 for Instructions on configurtngEland E2,UABI is a versatile interlace adapter [VIA)containing two parallel ports, Interrupt logic, andtwo 16-bit counters, all of which ore accessible tothe computer through the data bus,7.1.4.7 DlokConttollerViAUCD4, the disk controller VIA, has two S_bitports which are used 10 interface with the timing,>E, «.......m ~ n n _ ft ~ n " " _ rn ro m N m l~" """",, , , , , , , , , , , , , , , ,-,,----'c-f'-;' . , , . , , , , . , , , ,'" '" lI., "­ ':, , ," , fig. 7_10. Endorldentlty.

156 C1541 TROUBLESHOOTING & REPAIRGUIDE+l2Vf3-{>o-IZUF2F1/6 7406+SV7~~193 +"• SUA ~2 AI/eo-.UFZ,lPO,+-'ZV DftIVE MaTOIt+1211OFF.Gl,0«>Fig. 7-11. Schematic of track select circuit, Model 1540.Table 7-5.Track Select Truth TableON/OFF oI>SELA oI>SELB 01>1 01>2 01>3 of>4 OFF/ONOV X X +12V +12V +12V +12V +5V+5V OV OV OV +12V +12V +12V OV+5V +5V OV +12V +12V +12V OV+5V OV +5V +12V +12V OV +12V OV+5V +5V +12V +12V +12V OV OVread, write, encoder/decoder, track select, andoptics circuits. UCD4 also contains interrupt logicand two 16-bit counters that may be accessed bythe computer.7.1.5 Track Select Electrical Theory(Refer to Figs. 7·11 and 7.12)The track select circuit consists of UE2, UF2A,UF2B, UF2C, UF2D, UF2F, UG4C, and Q4through Q7. UE2, the phase decoder, pulls the selected(N) output low. To step inward (increasingtrack number), the four (N) lines must be clockedin ascending order (i.e., 1, 2, 3, 4, 1, 2... ). To step outward, the (N) lines must beclocked in descending order (i.e., 4, 3, 2, 1,4, 3 . . . ). Each of the (N) outputs is bufferedby a NOT gate (UF2A, UF2B, UF2C, UF2F) and atransistor (Q4-Q7) configured as a common-emitterbuffer. The windings of B2 (the stepping motor)form the collector loads for Q4-Q7. CR13-CR16clip any overshoot produced by the inductive characteristicsofthe windings of B2.When a logic 1 is applied to pin 9 of UF2D(ON/OFF line), the output of UE2 is enabled.When a logic 0 is applied to pin 9 of UF2D, theoutput of UE2 is disabled and none of the (N)lines are driven.UG4C buffers the enable signal for UE2 and

Advanced Theory of Operation 157OFF/~IlUFFEIlDRiVE MOTOR SERVO CIRCUITMOTOR/TACHOMETERTACH MOTOR// // ~--_---I~ , J 'Fig. 7-12. Block diagram of track select circuit, Model 1540.applies this signal to the motor driver servo circuit.Since the motor enable and step enable controlsare both accomplished with the same line, trackscan only be changed while the drive motor (B1) isrunning. Table 7-5 illustrates the relationship betweenthe ON/OFF, SEL A, and e SEL B linesand the 1, 2, 3, cf>4, and OFF/ON lines.7.1.6 Drive Motor System ElectricalTheory (Refer to Figs. 7-13 and 7-14)The purpose of the drive motor system is tomaintain the disk at a constant speed. The drivemotor system consists of the drive motor servo circuitand the drive motor tachometer.7.1.6.1 DriveMotor/TachometerThe drive motor/tachometer contains a depermanent magnet motor and a tachometer ona common shaft. The tachometer acts as a lowpowerac generator. The voltage output of thetachometer increases with increasing drive speedand provides feedback to the drive motor servo circuit.This feedback contains motor speed informationthat the drive motor servo circuit uses to determinehow hard to drive the motor. The drive motorservo circuit adjusts the motor current as necessaryto maintain a constant speed of 300 rpm. This isnecessary because each floppy disk may offer differentmechanical loads to the motor, due to manufacturers'differences or age of the floppy disk.7.1.6.2 DriveMotor Servo CircuitTachometer information enters the drive motorcircuit at E4 and E5. This Information, a sineFig. 7-13. Block diagram of drive motor system, Model 1540,wave, is rectified by the bridge rectifier consistingof CR1 through CR4. R1 provides a load for thetachometer. The output of the rectifier is applied topin 1 of ICI.IC1 is the speed controller. Power is suppliedthrough a low-pass filter (R3 and C5). C2 Is alsoprovided for filtering. R2, RIO, and VR1 determinethe speed of the floppy disk. VR1 is used to calibratedisk speed. C3 and C6 provide filtering. Theoutput of IC1 (pin 5) will Increase If the voltage atpin 1 is less than the threshold set by VRI. Conversely,the output at pin 5 willdecrease if the voltageat pin 1 is greater than the voltage set by VRl.The circuit willsettle when the feedback at pin 1 isequal to the threshold set by VRI. The output ofthe speed controller (IC1, pin 5) is applied to themotor driver.The motor driver consists of Q1 through Q4,R4 through R9, C4, and C7 through C9. Q2 is aninverting de amplifier. C4 provides filtering. R4 limitsbase current. The combination of Q1, CR5, andR7 enables or disables Q2. A logic low at E2 turnsoff Q1, allowing Q2 to operate normally. A logichigh at E2 turns on Q1, shutting off Q2 by shuntingits base current to ground and thus shutting off themotor. Q4 is the final pass transistor. When its baseis pulled low by Q2, through R6, it will conductharder. As Q2 increases in conduction, Q4 willproportionatelyincrease its own conduction. R9 andQ3 form a current limiter. As emitter current in Q4increases, the voltage drop across R9 increases.When the drop across R9 reaches approximately0.65 volt, Q3 will conduct. When Q3 starts conducting,it shunts some of the bias current for Q4 to

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,160 el541 TROUBLESHOOTING & REPAIR GUIDE~d ~ ~~ hmi~~~miu+Fig. 7-15. Schematic of write circuit, Model 1540.

Advanced Theory of Operation 161WRITE PROTECTFig. 7-16. Block diagram of write circuit. Model 1540.CR8 via the read/write winding (UIL1) and thebias winding (UIL2).The output of UH7, the first video amplifier(see Fig. 7-18), is applied to a low-pass filterformed by L8 through Lll and C16. C15 and C24block the dc offset out of the UH7 to prevent theoffset from disturbing the input bias to UH5. R16and R17 set a bias voltage of +6 volts which is filteredby C23 and C57 and applied to the input signalof UH5 via R18 and R19. The output of UH5 isapplied to the comparator via C58, C59, R27, andR28. C58 and C59 block the de offset out of UH5to prevent the offset from affecting the bias on theinput of the comparator, UH4. A +6-volt bias isapplied to the input signal of the comparator fromR16 and R17 via R14 and R15.The output of the comparator is applied to thevalid pulse detector (UG2D, UG3A, and UF6A).UG2D, along with C27, R24, and R25, forms anedge detector. Pin 11 of UG2D will produce a500-nanosecond active high pulse on rising edgesof the comparator's output and willproduce a 150­nanosecond high pulse on falling edges of the comparator'soutput. The pulse out of UG2D is appliedto UG3A, a single-shot multivibrator. UG3A producesan active low pulse which is approximately2.5 microseconds wide. Flip-flop UF6A is clockedon the trailing edge of the output pulse of UG3A.The output of the comparator must be maintainedfor at least 2.5 microseconds in order to be latchedinto the flip-flop. If a narrow noise pulse triggersthis circuit, the output of the flip-flop will notchange since the noise pulse will terminate beforeUG3A triggers UF6A. The output of the flip-flop(UF6A) will reflect the data delayed by approximately2.5 microseconds.The valid data out of the valid pulse detector isapplied to an edge detector consisting of UG2Aand UG3B. UG2A operates the same as UG2Dabove. The pulses out of UG2A trigger UG3B, asingle-shot multivibrator. UG3B produces a narrowpulse, which represents transitions of the data. Thisoutput is applied to the timing circuit to synchronizethe encoder/decoder clock, and to the encoder/decoder, which will detect the data and perform aserial-to-parallel conversion. Notice that pin 5 ofUG3A is connected to the read/write line, causingDATABIT SYNCR~ADIWRITEHEADFig. 7-17. Block diagram of read circuit, Model 1540.

162 CI541 TROUBLESHOOTING & REPAIR GUIDEHEADAHEADBc.,IN.. r.......CIllOIN,,j...." '.101(." ",OKR27"0.2'"0.OT220the valid pulse detector to be disabled during awrite operation.The video amplifiers willoften oscillate with nodata in, but these oscillations are high enough infrequency that they seldom get past the valid pulsedetector.7.1.9 Encoder/Decoder ElectricalTheory (Refer to Figs. 7-19 and 7-20)The encoder/decoder circuit encodes and decodesthe transition positions which are written to,or read from, the disk. The encoder/decoder circuitalso performs the serial-to-parallel and parallel-to-serialconversionsnecessary to move the databetween the computer and the floppy disk.7.1.9.1 DecoderThe decoder consists of UF4 and UE5A. Thedecoder has two outputs. Pin 1 of UE5A is theserial data output and pin 2 of UF4 is the serialclock output. The serial data output contains aclock bit between data bits. The serial clock outputis high whenever the clock or data bits are valid onthe serial data line.A cell Is four encoder/decoder clock pulseswide. As mentioned in read circuit theory, if a transition(or pulse into the decoder) occurs at the beginningof a cell, that cell is a logic 1. If no transitionoccurs, the cell is a logic O. When a transition doesoccur, UF4 (a binary counter) is cleared and thetiming circuit is reset to start the encoder/decoderclock at the beginning of its cycle. Pins 6 and 7 ofUF4 are at logic lows, causing the output of UE5A,the serial data line, to go to a logic 1.Two encoder/decoder clock pulses later, theserial clock (pin 2 of UF4) goes high. When the serialclock line is high, the serial data line is valid. Theserialclock line remains high for two clock cycles.Fig. 7·18. Schematic ofreadA bit cell is now complete. At this time, pins 2and 3 of UF4 will again be a logic 0 and pin 6 willbe a logic I. The logic 1 on pin 6 of UF4 causes theserial data line (pin 1 of UE5A) to be a logicO. If notransition occurs at the beginning of the next cell,the serial data line willremain at a logic 0 when theserial clock line goes high, two encoder/decoderclock cycles into the cell.7.1.9.2 Bft CounterThe bit counter produces the byte sync signalto the microprocessor and the shift/load signal forthe parallel-to-serial converter. UE3, UF3, andUCIB form the bit counter. UE3 is a 4-bit binarycounter that is clocked by the serial clock. Everyeight serial clock pulses, when the outputs of QA,QB, and QC go to logic I, the output of UF3Agoes low. The logic 0 from UF3A causes the outputof UCIB to go high. The high output of UCIB isthen applied to UF3B and UF3C. UF3C NANOsthe output of UCIB with the byte sync enable linefrom the disk controller VIA and with the invertedserial clock from UE5B. The output of UF3C informsthe microprocessor that a byte is ready to beread into the computer. When in the write modethe output of UF3C is used to indicate that the nextbyte to be written should be loaded.UF3B NANOs the output of UCIB with theserial clock and with the QA output of UF4. Theoutput of UF3B, when low, causes the next byteto be transmitted to be loaded into the parallel-toserialconverter.7.1.9.3 Serial-to-Parallel ConverterThe serial-to-parallel converter consists of U02and UE4. UD2 produces eight bits in parallel,which may be entered into the computer. UE4adds an additional two bits, which are used to de-

Advanced Theory of Operation 163- ·i~~:~______'-_,,It:)61~~4tVce~A ClR Q5 -cl:- lIZ :_:2.1[1 •+OV.-J ~DATAREADJWRITEcircuit, Model 1540.ue•I!ST4LII4'-D>o-'...+ un.14 V3 'I'4LllOl-'===±=====1===t=:P'MAOI ~-+--/---=-----.,.:;;;----/.,lYTl~:~:t-\....-.lv,,,"'iIliTI IYlle [NM!. .l-rJ;ac+~t~Q~__O-_V414UOOFig. 7-19. Schematic of encoder/decoder circuit, Model 1540.

164 cisai TROUBLESHOOTING & REPAIR GUIDEẉ.ffi 00 0 zz~~ ~~0~ ~~PORT AENCODER'DEcooER croc«DATADATADATAFig. 7-20. Block diagram of encoder/decoder circuit, Model 1540.teet block sync signals. Serial data is presented tothe input of UD2 (pin 2). The serial clock, which isapplied to the clock input of UD2 (pin 8), shifts thecontents of the serial-to-parallel converter on its risingedge. Data on the disk is encoded using lO-bitgroup code recovery (GCR). The computer encodesand decodes the GCR code. GCR codingprevents more than two zeros from appearing together.Because GCR coding uses 10 bits to definea decoded 8-bit byte, the encoder/decodermust deliver five bytes of encoded data to the computerin order for the computer to decode fourbytes of data.7.1.9.4 BufferThe buffer, UC3, gates data onto port A ofUCD4 when in the read mode. When in the writemode, the buffer is tristated, allowing data fromport A of UCD4 to be applied to the parallel-toserialconverter without conflict from UD2.7.1.9.5 Sync DetectorA block sync signal consists of at least 16 logicIs (clock and data bits set to logic 1). During a readoperation, the output of UC2 goes low when 10consecutive logic Is are detected by the serial-toparallelconverter. The block sync signal is availableon pin 9 of UC2. The leading edge of the blocksync signal interrupts the computer, which thenmonitors the signal until its falling edge. After thefalling edge occurs, the computer enables the bytesync and waits for the byte sync to become active.When the byte sync becomes active, the receivedbyte is loaded into the computer. All received datais synchronized in this manner.7.1.9.6 Parallel-to-Serial ConverterIn the write mode, data from port A of UCD4is applied to the parallel-to-serial converter, UD3.When the output of UF3B becomes active, the byteto be written is loaded into the serial-to-parallelconverter. The inverted clock signal is used to shiftbits out of the parallel-to-serial converter. UF3Cinforms the computer to load the next byte to bewritten.7.1.9.7 EncoderThe encoder consists of UF5B and UF6B. Theencoder must produce a transition for each high bitpresented to it and must not produce a transitionfor a low bit. UF5B gates the inverted clock signalto the flip-flop (UF6B) when a high is applied toUF5B from UD3. When a low from UD3 is appliedto UF5B, no clock pulse is gated to UF6B. UF6Bwillchange states whenever a clock pulse is appliedto pin 11. The result is a transition for every high bit

Advanced Theory of Operation 165out of U03. UF6B may be disabled by applying alogic low to pins 13 and 12 of UF6B. The complementaryoutputs of UF6B are available on pins 8and 9 and are applied to the write circuit.7.1.10 Optics Circuit ElectricalTheory (Refer to Figs. 7-21 and 7.22)The optics circuits consist of OS1 on the caseassembly; OSl, CR1, and Q1 on the drive unit;and UF2E, R35, R36, R44, and R45 on the diskcontroller PC board.R45 provides current limiting for the powerLEO, OSl on the case assembly. R35 provides currentlimitingfor CR1, the optical transmitter, on thedrive unit. Both CR1 on the drive unit and OSl onthe case assembly turn on as soon as the +5-voltline becomes active (power on). The optical receiver,Q1 on the drive unit, is positioned underCR1 in such a manner that the write protect notchis directly between them when the floppy disk isseated. Q1 on the drive unit conducts (produces alogic 0) when the write protect notch is left uncovered(writing permitted). When the write protectnotch is covered, Q1 on the drive unit does notconduct (logic 1). The write protect output of theoptical receiver is available on pin 12 of P6 and isapplied to the write circuit. UF2E drives the access/error LEO. A high on the LEO line causes OSl onthe drive unit to illuminate. R36 limits the currentthrough OS1.+5VJt8,PWR LEDPWR LEDPWR LED.N'LEOJ~HV .~__------...,~~ ACC£ aS sERROflLED.. sv ••_--------i~ ~11(WRITE PROTECT ....... r:::l~Fig. 7-22. Block diagram of optics circuit, Model 1540.7.2 ADVANCED THEORY.MODEL 15417.2.1 Frame Electrical Theory(Refer to Figs. 7-23 and 7-24)The electrical function of the frame assembly isto condition and convert the ac line voltage beforeapplying it to the power supply on the disk controllerPC board.The ac line voltage enters the disk drive at J9,which is both a connector and an RFI filter. Afterr----------,J8, PWR LEDtiP l ~ER IIPWR LED I ~ (GN)Nle s IGNO 2 r- - --1IL .JI CASE ASSY IJP',·OPTICSJ6, OPTICSLEO ""'-111>0-10-----{ACCESs/ERROR LED +5V ROR36NIC NIC OSi•NIC NIC· ACCESS/-VUf2' eolie 140«1NIC NICERROR LEO••NIC ERR'6R'TED .K912 WRIT[ PROTECT WRITEPROTECTLED 2 RO7 NIC LT " RDWRITE PROTECT 12ro NIC NIC 7 .,•••V NIC e WRITE N/C NIC 10 PROTECT""'- CR'e-;NICNICSENSOR WRITE PROTECT EMITTER"" NIC NIC Z WRITE: PROTECT LED NICI .N' GN' " VI" .ND GN' I BUFig. 7-21. Schematic of optics circuit, Model 1540."

166 Cl541 TROUBLESHOOTING & REPAIR GUIDEACLINE9VA.C16VACJI,AC INPUTFig. 7·23. Block diagram of frame assembly, Model 1541.passing through the filter, the ac voltage is appliedto the SPST power switch, S1. The output of thepower switch is applied to F1, which providesovercurrent protection. F1 is a I-ampere, 250-voltslow blow fuse. The output of F1 is fed to the transformer,T1. T1 steps down the ac line voltage into9 volts ac and 16 volts ac. Both of these outputshave their own secondary windings and are isolatedfrom each other.7.2.2 Power Supply ElectricalTheory (Refer to Figs. 7-25 and 7-26)The VIC-1541 power supply produces tworegulated voltages, +12 volts de, and +5 volts dc.These voltages are derived, respectively, from the16 volts ac and 9 volts ac supplied by the frameassembly. The power supply, located on the diskcontroller PC board, has a reliability switch whichremoves power from the write amplifiers in theevent of a +5-volt failure or during power up/down. Thus, the reliabilityswitch protects the dataon the floppy disk by disabling the write amplifierswhenever the +5-volt line goes below 3.9 volts.II~VAC.50-60HzFig. 7·24. Schematic of frame assembly, Model 1541.7.2.2.1 +12 Volts DCSixteen volts ac is applied to the power supplyvia pins 1 and 4 of PI. From PI, the ac power isapplied to bridge rectifier CR1. CR1 rectifies (fullwave) the 16 volts ac to produce approximately+21 volts dc. The output of the rectifier is appliedto a filter consisting of C1 and C17, which smoothsout the pulsating de from CR1. The output of thefilter is applied to U2, a + 12-volt regulator. Theoutput of U2 is the regulated + 12 volts dc outputof the power supply. C2, C21, and C3 reduce linenoise, and CR2 protects the regulator against negativevoltage excursions during power up/down.7.2.2.2 +5 Volts DCThe +5-volt leg of the power supply operatesin the same fashion as the + 12-volt leg, the onlydifference between them is in voltage levels. Nine9VIDI9V .,leV"116 1D2CR'IN4002.>'--+-'-'.:-'-

Advanced Theory of Operation 1679VAC1------1~-.+5V16VAC1-_.--1--. +12V+VSWFig. 7·26. Block diagram of power supply, Model 1541.volts ac is applied to the power supply via pins 2and 3 of Pl. The ac power is applied to bridge rectifierCR3. After rectification, the resulting + 10volts de is filtered by C4 and C16 before it is appliedto the +5-volt regulator, U1. The output ofU1 is the regulated +5-volts dc output of thepower supply. C5 reduces line noise and CR4 protectsthe regulator against negative voltage excursionsduring power up/down.7.2.2.3 Reliability SwitchThe reliability switch consists of Q1, Q2, CR5,and associated components. Q2 and CR5 form acomparator. When the +5-volt line exceeds +3.9volts, base current of Q2 flows through the baseemitterjunction via R4, R3, and CR5. The cutoffvoltage is determined by CR5 (3.3 volts) and thebase-emitter drop of Q2 (0.6 volt). As the baseemittercurrent increases, collector-emitter currentalso increases. When Q2 begins to draw collectorcurrent, it forces Q1 into conduction by causingbase-emitter current to flow through Q1 via L8,Q2, R3, and CR5. When Q1 is turned on, approximately11.6 volts is applied to the +Vsw line toenable the write amplifiers. If the + 5-volt line dropsbelow 3.9 volts, Q2 is turned off, in turn turning offQ1. With Q1 turned off, power is removed fromthe +Vsw line and the write amplifiers are disabled.R2 ensures that Q1 is properly turned off by shuntingany Q21eakage current away from Q1. L8 andC15 form a low-pass L-type filter which isolates thenoise produced by the motors in the + 12-volt line.C35, C40, and C47 are bypass capacitors whichreduce noise in the +Vsw line.7.2.3 Timing Electrical Theory(Refer to Figs. 7·27 and 7.28)The timing circuit produces the clock signals.One of the outputs is a I-MHz square wave. Thisfixed I-MHz clock signal is applied to the microprocessor,controlling the rate at which the microprocessorexecutes instructions. The second output is avariable frequency pulse which is used to controlthe encoder/decoder circuit. The timing circuitconsists of a 16-MHz oscillator, a divide-by-Ifi frequencydivider, and a programmable divider.1 MHzCLOCK SEL ACLOCK SEL 881T SYNCENCODEAIDECODERCLOCKFig. 7·27. Block diagram of timing circuit, Model 1541.7.2.3.1 16·MHz OscillatorThe 16-MHz oscillator is Y1, a crystal-controlledsquare-wave oscillator. The output of the16-MHz oscillator is applied to the divide-by-16 frequencydivider and to the programmable divider.7.2.3.2 Dlvlde·by.16 Frequency DIviderThe divide-by-16 frequency divider consists ofa 4-bit binary counter, UD5. Pin 5 (the divide-by-2output) of UD5 is applied to pin 6 of UD5 in orderto clock the last three stages of the counter. Theoutput of the divide-by-16 frequency divider istaken from pin 12 and is applied to the microprocessorvia L3 and R1, which filter the clock line toreduce noise.7.2.3.3 Programmable DividerThe programmable divider produces the clockfor the encoder/decoder circuit and may be reset to

168 Cl541 TROUBLESHOOTING & REPAIR GUIDEr----~-----------------------lr------------1+llV Ll I I JZ,2~1t I : I,----+-+-----'--hI III I IIIFig. 7-28. Schematic of timing circuit, Model 1541.allow the phase of the encoder/decoder clock tobe controlled. Floppy disks have fewer sectors pertrack on the innermost track (track No. 35) than onthe outermost track (track No.1). This variation innumber of sectors per track keeps the bit densityfairly constant throughout the writing surface of thedisk. Each disk is further divided into four zones,with each zone containing a unique number of sectorsper track. The programmable divider has fourpossible output frequencies, with each frequencycorresponding to one of the four zones on thefloppy disk. In order to maintain fairlyeven bit densities,the encoder/decoder must be clocked at afaster rate when writing on the outer tracks thanwhen writing on the inner tracks. This is becausethe outer surface of the disk is passing over thehead more quickly than the inner surface. Thus, itis the encoder/decoder clock that determines howmany sectors willfiton any given track.The division factor of the programmable divideris controlled by the CLOCK SEL A andCLOCK SEL B lines. Table 7-6 defines parametersfor each zone. The programmable divider consistsof UE6 and UCl. UE6 is configured as a presettable4-bit binary up counter. The output of UE6 istaken off pin 12, the TC output. The TC output(active low terminal count) goes low when thecounter overflows from 1111(2) to 0000(2). Thisactive low pulse is applied to UC1, the encoder/decoder circuit. An output of UCl, (pin 22), is anactive low pulse that is applied to the load input ofthe presettable counter. When the load goes low,the counter is preset to the values present on the A,B, C, and D lines. The C and D lines are strappedlow and therefore each line is set to O. If the A andB lines are both low (zone 4 condition), the counteris preset to 0000(21' Sixteen counts later the loadline will reset the counter to 0000(21' If the A lineonly is a logic 1 (zone 3 condition), the counter ispreset to 0001(2) and 15 counts later the load linewill again preset the counter to 0001(2). Note thatonly 15 counts were required, since the counterhad a head start of one count. If the B line only is alogic 1 (zone 2 condition), the counter is preset to0010(21' The counter now has a head start of twocounts and will require only 14 counts before it ispreset again. If both the A and B lines are at logic 1(zone 1 condition), the counter is preset to 0011(21'The counter now has a head start of three countsand will require only 13 counts before it is presetagain.Table 7-6.Timing CircuitParametersZONEI ZONE2 ZONE3 ZONE4CLOCK SEL A 1 0 1 0CLOCKSELB 1 1 0 0DivisionFactor 13 14 15 16Encoder/DecoderGlockFreq (MHz) 1.2307 1.1428 1.0666 1.00Sectors per Track 21 20 18 17Track Numbers 1-17 18-24 25-30 31-35L4 through L7 filter the signal lines to reducenoise. Ll, L2, L7, and C10 through C14 form a

Advanced Theory of Operation 169low-pass L-type filter which prevents the couplingof noise from the timing circuit to the +5-volt lineand vice versa.Pin 22 of UCI is the BIT SYNC output. TheBIT SYNC output produces a pulse whenever theprogrammable counter, UE6, overflows or whenevera high-to-low or a low-to-high transition occursin the serial data on the disk. When this pulseoccurs, the encoder/decoder clock is set to thebeginning of its cycle and the clock is synchronizedwith the serial data. UCI maintains the phase relationshipbetween the serial data and the encoder/decoder clock to within 62 nanoseconds.7.2.4 Computer Electrical Theory(Refer to Figs. 7-29 and 7-30)The computer performs two major functionsserialbus communications and floppy disk control.Communication with the serial bus is accomplishedby the serial bus interface. Interfacing with thefloppy disk is accomplished by the read, write, trackselect, motor drive, timing, and optics circuits alongwith the drive unit itself. The computer communicateswith these devices through the versatile interfaceadapter (VIA). The computer consists of theMPU, ROM, RAM, write logic, address decoder,VIA, and the serial bus interface.7.2.4.1 MPUUC4 is a 6502, 8-bit microprocessor. Themicroprocessor fetches an instruction from ROM orRAM and executes the instruction. The instruction,in turn, causes the microprocessor to alter data inRAM, internal registers, or registers in the VIAs.After completing each instruction, the MPU fetchesthe next instruction and the cycle continues. Therate at which the microprocessor executes instruc- .tions is determined by the 1 clock present at pin37 of UC4. The 1 clock is produced by the timingcircuits (refer to Section 7.2.3 "Timing ElectricalTheory"). The microprocessor, in turn, producesan inverted, nonoverlapping clock signal (i.e., 2)from the 1 clock. The 2 signal is present at pin39 of UC4. Two NOT gates, UC5A and UC5F,buffer the 2 clock before it is sent to the VIAs(UC2 and UC3) and to the write logic. The 2 signalis used to synchronize write operations; therefore,the ROM does not require the 2 signal.The nonmaskable interrupt (NMI, UC4, pin 6)is disabled by RlO and is not used. The ready line(RDY, UC4, pin 2) is held at a logic high by R9 andalso is not used.There are three lines entering the microprocessorthat allow hardware devices in the VIC-1541to change the sequence of instructions executed byUC4. These lines are: set overflow (SO, pin 38),interrupt request (IRQ, pin 4), and reset (RST,in 40). When the set overflow line goes high, itsets the overflow bit in the status register internalto UC4. The sequence of instructions may bechanged by testing the overflow flag using the BVC(branch if overflow clear) or BVS (branch if overflowset) instructions.r---------------~ 1 MHzCLOCKDATAATNHARDWARECONTROLFig. 7·29. Block diagram of computer circuit, Model 1541.

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Advanced Theory of Operation 171+OY=========. 04[00 U en CAl ~~---......c------------+-h~BYTES'ttlCENAll.trl " f ~ ~• 04 PAl2. De !'A2D6 2708 PA301 21 D1 .....ACl!ll Rsa llC2- ",.5=======::;-;===:;~'~~:~"::J~ 6~1z,.2 :;~·~RS3 ,.0...llV.....Z4- ell Pel~~~~~~ - ~ I-- E:~~~' 2S Ill. ;:: PISl-. ,3+ iiiT PM,_....19---'READ/WI8Tf3~PAI4-'-,.,2S~PA3.-.",..."----. '8 ----.P .'-.PA7IO---pli Sf:L A11----'_ SEL BIZ-'-ONtOff13----'LEDr4~~CLOCK sa ACl..OCKSELB:======~Hlli======~t+11~81.0CKSYNC~,l... ,-===========IT.. "[:JluceeeczBBITWu RIO fl9 RUZ.(ll( a.OK 2J)K~== II~D-II -II 1)0-10ucs1/414LSOO....,-+++-_----.....f-~BYfE." ""..-"'" ,-+IV'UClA. UCSF'4 lie "'504 1/8 'HLS04S'l'NC1'£»2 -13-[>o-1i!L...,~3~:8-----1 ~...SJ,. 1/6 m5041.11'6l'tLSOOUC!I116 MLI04circuit, Model 1541.structions which make up a machine language programcalled the DOS (disk operating system). TheROMs are located between addresses COOO(hex) andFFFF(hex)' Data is applied to the data bus (DOthrough 07) from the ROM when the CE line (pin20) goes low. The address inputs (AO throughA12) determine which one of the 8192 bytes In theROM willbe applied to the data bus. While the CEline is high, the data outputs are trIstated andessentially disconnected from the data bus.7.2.4.3 RAMThe RAM is UB2, a 2K-byte RAM. The RAMis located between addresses 0 (OOOOlhex)) and2047 (07FF 1hexl)' Significant locations in RAMare:OOOO-OOFF0100-01FFZero PageMicroprocessor StackThe zero page contains variables, pointers, andother data used by the DOS. The microprocessorstack is used for temporary storage of data.

172 Cl541 TROUBLESHOOTING & REPAIR GUIDEWhen the MPU writes to the RAM, the data tobe written is placed on the data bus (DO throughD7), the location that the data is to be written into isplaced on the address bus (AO through A15), andthe WE (write enable) and CS (chip select) lines arebrought low. When the MPU reads from the RAM,the location to be read is placed on the address bus(AO through A15) and the CS line is brought low.Data is then gated from the RAM to the data bus(DO through D7).7.2.4.4 Address DecoderThe address decoder selects one of the deviceslisted in Table 7-7 when the address bus containsan address within the address range of the device.mally used. It is just a by-product of the addressdecoder scheme. Notice that the read/write signalsare not decoded for ROM addresses. TheVIC-1541 hardware does not prevent a bus conflictbetween the microprocessor and the ROMs. Thehardware design merely assumes any memorytransfer at or above 8000(hex) is a read operation.CAUTIONNever write to memory locations at orabove 8000Ihex)' A bus conflict may occur, causingpermanentdamage to UB3, UB4,or UC4.Table '-7.AddressDecoder ParametersDEVICERAM, (UB2)VIA, Serial Bus (UC3)VIA, Disk Conrrol(UC2)ROM, Low (UB3)ROM, High (U84)UC6B and UC6C decode the ROM low andROM high addresses. UC5D is a NOT gate, whichinverts A13 before it is applied to UC6B. UC6Benables UB3, the low ROM, when A15 = logic 1and A13 = logic O. UC6C enables UB4, the highROM, when A15 = logic 1 and A13 = logic 1. AOthrough A12 are decoded by the selected high orlow ROM. Notice that A14 is not decoded, and ittherefore does not affect the operation of the decoder.The end result is two identical 16K blocksof ROM. Each of the ROM chips has two valid addressranges. One range is used with A14 = logic 0and the other range is used with A14 = logic 1 asin Table 7-8.ROM, Low (UB3)ROM, High (U84)Table 7-8.ADDRESS RANGE (HEX)ROM ImagesAI4 = LOGIC 08000-9FFFAOOO-BFFF0000-07FF1800-180FICOO-ICOFCOOO-DFFFEOOO-FFFFAI4 = LOGIC ICOOO-DFFFEOOO-FFFFData that is read from address 8000(hex) isidentical to the data read from address COOO(hex).This must be so because both address the samelocation in the same ROM. The redundant 16Kblock between 8000(hex) and BFFF(hex) is not nor-UC7, a BCD-to-decimal decoder, decodes theRAM and VIA address ranges. Address lines AlO,All, and A12 are connected to the A, B, and Cinputs, respectively, of UC7. As a result, the outputsof UC7 decode one of eight 1024-byte blocks.Address line A15 is applied to the D input of UC7.When the D input is a logic 0, one of the 0 through7 outputs will be active (i.e., logic 0). When the Dinput is a logic 1, outputs 0 through 7 willbe inactive,effectively disabling UC7. Any address at orbelow 7FFF(hex) willenable UC7. Any address at orabove 8000(hex) willenable the ROM array.As noted previously, UC7 can decode one ofeight 1024-byte blocks of memory. Notice thatUC7 does not decode A13 or A14. As in the ROMaddress decoder, this produces redundant imagesof the 8K block decoded by UC7. Since two bitsare not decoded, UC7 produces four identical 8Kblocks of memory as opposed to the two identicalblocks produced by the ROM address decoder. Theaddress ranges for each 8K block are as follows:0000-lFFF(hex), 2000-3FFF(hex), 4000-5FFF(hexloand 6000-7FFF(hex). Writing to location OOOO(hex)produces the same result as writing to locations2000(hexlo 4000(hexlo or 6000(hex). The redundantranges of 2000-3FFF(hexlo 4000-5FFF(hexlo and6000-7FFF(hex) are not normally used. UC6 andUC5 combine the 0 and 1 outputs of UC7 to selectthe 2K RAM, UB2. Table 7-9 illustrates the RAMaddress range. The 2 through 5 outputs of UC7are not used. With four images being produced,this leaves the following locations not addressingany devices: 0800-17FF(hexlo 2800-37FF(hexlo4800-57FF(hexlo and 6800-77FF (hex)'

Advanced Theory 01Operation 173Table 7-9.RAMImagesA13= 0, A13 = 1, A13 = 0, A13 = 1,A14 = 0 A14 = 0 A14 = 1 A14 = 1RAM (UB2) 0000-03FF 2000-23FF 4000-43FF 6000-63FFThe 6 output of UC7 enables the serial busVIA, UC3. Notice that UC3 decodes AO throughA3. A4 through A9 are not decoded, again produclngredundant images. There are 64 images ofthe 16 VIA registers in the 1024-byte block enabledby UC7. There are also four images of each 1024­byte block that is selected. This gives a total of 256images of the VIA registers. Typically, the serialbus registers are accessed at 1800-180F1hex) bythe DOS.The 7 output of UC7 is used to enable the diskcontroller VIA, UC2. Again, this VIA has a total of256 redundant images. Typically, the disk controllerVIA is accessed at 1COO-120Flhexl by the DOS.7.2.4.5 WritelogicUC5B and UC6A form the write logic circuit.UC5B inverts the R/W (read/write) line from pin34 of UC4. The output of UC5B willbe high duringa write cycle and will be applied to NAND gateUC6A, together with the 2 signal from UC5F.The output of UC6A drives the WE (write/enable)line on the RAM chip UB2. The write logic for theVIAs is internal to the VIAs. Therefore, the R/Wline and the 2 signal are applied directly to theVIA chips.7.2.4.6 Serial BusThe serial bus circuits consist of UC3, UD3A,UA1A, UA1B, UA1E, UAlF, UBlA, UB1B, UB1E,UBlF, UD3B, and associated components. Theserial bus circuits interface the computer with theserial bus and allow the VIC·1541 to communicatewith the VIC 20/Commodore 64. The serial buscircuits also control the reset line for the VIC-1541computer.When power is first applied to the VIC-1541,C46 is in a discharged state producing a logic 0 atthe input of UD3B. The resulting logic 0 out ofUD3B drives the reset line for UC2 and UC4, causingthem to assume their initialized states. After ashort period of time, C46 will be charged throughR25, up to the logic threshold of UD3B. Thiscauses the output of UD3B to change states, placingthe reset line high, allowing the computer tostart execution of the DOS. If the VIC 20/Commodore64 is reset, the reset line on the serial bus (pin6 of P3 and P2j willgo low (logic0). This logic 0 isinverted by UA1A and applied as a logic 1 to theinput of UB1A, which discharges C46 to a logic O.:Subsequent action of the reset circuit is as describedearlier. CR7 is provided to discharge C46 if poweris momentarily removed from the VlC-1541. Thereset circuits are active only during power-up of theVIC-1541 or the VIC 20/Commodore 64.The VIC-1541 serial bus is similar to the IEEE­488 bus (also known as GPIB or HPIBj, but it isslower and does not use some of the control signals.Like the IEEE-488 bus, the VIC-1541 busmay be interfaced with several peripherals, eachhavinq a unique address. All the peripherals aredaisy-chained together. Daisy-chaining means thefirst peripheral is connected to the computer, thesecond peripheral is connected to the first, the thirdperipheral is connected to the second, and so on.Daisy-chaining is the reason the two serial busconnectors, P3 and P2, are wired in parallel. Theusers of the bus (e.g., VIC 20/Commodore 64,VIC-1541, printers) can be divided into threegroups according to their activities at any giveninstant: controller, talker, and listener.Only the VIC 20/Commodore 64 may be acontroller, talker, and a listener. The peripheralsmay be either talkers or listeners. The controllerdictates bus commands to the peripherals which tellthe addressed device whether to talk, listen, untalk,or unlisten. These bus commands are:Talk-Addresses a specific device andinstructs the device to prepare to send data.UntaIk- Addressed device is instructed tocease transmissions.Listen-Addressed device is instructed toprepare to receive data.Unlisten-Addressed device is instructed toignore any further data transmissions. Devicewillwait for next command.These bus commands are sent as an 8-bit byte.Five of the bits are used for the address and theothers are used for the command definition. A totalof 28 devices may be addressed by the serial bus.However, even though the address range of theserial bus is 4 through 31, it can only drive fiveloads at any given time.

174 Cl541 TROUBLESHOOTING & REPAIR GUIDECAUTIONConnecting more than five devices to theserialbus could result in permanent damage tothe serialbus circuits.Applicable bus signals used by the VIC-I541are:SER CK-Primarily used to indicate that datais valid on the serial data line. Also used as aready to send signal.SER DATA-Primarily used to carry data bits.Also used as cleared to send, EOIacknowledge, and handshaking signal.SER ATN-When false, serial data containsdata to be transferred. When active, it indicatesthat the data bus contains a command. Onlythe controller may drive this line.All of these signals are active low signals. Thesignal lines are driven by open collector outputs, allowingall the peripherals to be write-aRable. Thatis, any or all of the devices may drive the bus linesat the same time. If any device pulls a bus lineactive (low), the result will be an active line. Inorder for a line to be inactive (high), all peripheralsmust release the line to high.Refer to Fig. 7-31 for a typical data transmissionsignal. Prior to TO, the bus is in its standbystate, the serial clock line is held low by the talker,and the data line is held low by the listener. TheSER ATN line is high, indicating the transmission totake place is data rather than a command. At TO,the talker signals "ready to send" by releasing theclock line. At Tl, the listener acknowledges the"ready to send" by signaling "clear to send." Thelistener signals "clear to send" by releasing the clockline to a logic high. If the listener is busy, it will notsignal "clear to send." The time between TO andTl is undefined and is determined by the listener.Within 200 microseconds, the talker pulls the clockline low at T2. At some time between T2 and T3,the talker places the least significant bit on the SERDATA line. Since the bus lines are active low, thedata appears inverted. That is, a low represents a"true" bit. At T3, the clock line is released to logic1, indicating to the listener that the data bit on theSER DATA line is valid. The talker holds this conditionuntil T4, where the talker releases the dataline to a logic 1 and pulls the clock line low. Thissequence continues until T18. After clocking in themost significant bit at T17, the talker once againpulls the clock line low and releases the data line atT18. Now the talker is waiting for the handshakesignal which occurs at T19. At T19, the listenerpulls the data line low. After T19, the serial bus isback in its standby condition, as it was prior to TO.Throughout the transmission of this byte, the talkerkeeps control of the clock line. The talker hascontrol of the data bus from T2 to T18 only. Therest of the time the listener uses the data line forhandshaking. Data transfers continue in this fashionuntil the last byte to be transferred. The last byteto be transferred contains "end or identify" handshaking.The handshaking signal for "end or identify"takes place between Tl and T2 (refer to Fig. 7-32for "end or identify" information). The talker signalsSER CKTO TI, ,, ,ITO··Ir---fr-, ,,,SER DATASER ATN 0~F--,·.Fig. 7-31. Typical data transmission.

Advanced Theory of Operation 175"end or identify" by not pulling the clock line lowfor at least 200 microseconds. After approximately200 microseconds, the listener acknowledges the"end or identify" at T1A by pulling the serial dataline low. At T1B, the listener releases the SERDATA line to logic 1, informing the talker to transmitthe last byte. At T2, the talker pulls the clockline low and the byte is transmitted. At some timeafter T19, the talker and the listener release theclock and data lines, respectively. These actionsoccur at T20.A bus command is transmitted in the samemanner as bus data, except that the SER ATN lineis pulled low during the transmission. When a buscommand is being transferred, the VIC 20/Commodore64 is the bus controller and all the peripheralson the line become listeners. After the buscommand, a secondary address may also appear.The secondary address is optional and is used tocontrol and specify a subchannel. After the buscommand is issued, the addressed device assumesthe role issued by the bus command. Usually, theVIC 20/Commodore 64 assumes the oppositerole. For example, if a talk command is issued thecomputer assumes the role of the listener. All thedevices on the bus that are not involved with thetransfer of data release control of the bus lines andawait the next command (i.e., SER ATN pulledlow). It is possible for the controller to issue a listencommand to one peripheral and a talk commandto another peripheral, causing data to be transferredbetween two peripherals while the VIC 20/Commodore 64 is free to perform other tasks.Such a possibility is difficult to accomplish, but theVIC-1541 bus is capable of doing so.UA1B is the line receiver for the serial clockline. The output of UA1B is entered into the serialbus VIA, UC3. When the VlC-1541 is a talker, ittakes control of the serial clock line using port B, bit3 (pin 13, UC3) of the serial bus VIA. When pin 13of UC3 goes high, UB1E pulls the clock line active.UBI has open collector outputs.UA1E is the line receiver for the SER DATA'line. The data is inverted and applied to the serialbus VIA. The SER DATA line is driven in the writemode by UB1F. The serial-to-parallel and parallelto-serialconversions are performed by the software.UA1F is the line receiver for the SER ATNline. The output of UA1F is applied to pin 40of UC3, generating an interrupt to the computer.The output is also applied to pin 17 to allow thecomputer to sample the state of the SER ATN line.When the SER ATN line is active, the SER DATAline is pulled low by UD3A and UB1E. TheVIC-1541 releases the data line by using the otherinput (pin 1) of the Exclusive OR gate, UD3A.E1 and E2 set the address of the VIC-1541.Refer to Chapter 1 for instructions on configuringE1 and E2.UC3 is a versatile interface adapter (VIA) containingtwo parallel ports, interrupt logic, and two16-bit counters, all of which are accessible to thecomputer through the data bus.7.2.4.7 Disk Controller VIAUC2, the disk controller VIA, has two 8-bitports which are used to interface with the timing,read, write, encoder/decoder, track select, andoptics circuits. UC2 also contains interrupt logic andtwo 16-bit counters that may be accessed by thecomputer.7.2.5 Track Select Electrical Theory(Refer to Figs. 7-33 and 7-34)The track select circuit consists of UC1, UD1B,UD1C, UDlD, UD1E, and Q8 through QU. UC1, ,, ,, , , , , , , , , , " I, , , , , , I' ,I,0----7 ,,,TO TITIA TIB T2 T3 T' T6 T7 T. T' TlO Til TI2 TI3 Tl4 T" Tl6 Tl? Tie Tl9 720, ,I I , , I , , , , , , , , "~-r'I I , , , , , , ,,",SER CK,,,SER DATAFig.7·32. End or identify.

176 el541 TROUBLESHOOTING & REPAIRGUlDEOC"~":" QO~: ~~~~~~[.-t>::fl SEL A::====12 ST[PO '1'2 1/6o 7406SEL 8 .. 10 STEP 1 '1'3 IOM/OFF • 8 MTRS hffiiSO

Advanced Theory of Operation 177Table 7-5.Track Select Truth TableON/OFF ,.SELA ,.SELS ,.1 ,.2 ,.3 "4OFF/ONOV X X +12V +12V +12V +12V +SV+SV OV OV OV +12V +12V +12V OV+SV +SV OV +12V +12V +12V OV+SV OV +SV +12V +12V OV +12V OV+SV +SV +SV +12V +12V +12V OV OVTo get a more comprehensive understandingof the internal operation of VCI, see Section 7.1,"Advanced Theory, Model 1540." VCI is essentiallya custom IC that contains the discrete ICsused in the 1540. Also see Appendix E.7.2.6 Drive Motor System ElectricalTheory (Refer to Figs. 7-35 and 7·36)The purpose of the drive motor system is tomaintain the disk at a constant speed. The drivemotor system consists of the drive motor servo circuitand the drive motor/tachometer.DRIVE MOTOR SERVO CIRCUITMOTOR/TACHOMETERTACll// /

IIIIIIIrp;';T-';F- - - - ~I I I I ~:~~E a':.~;l IL L ~~oJ

Advanced Theory of Operation 179Q4 to maintain motor current at a safe level for Bl(the drive motor). C7 through C9, R5, and R8control the slew rate and noise of the motor driver.The collector of Q4 is tied to the drive motor/tachometer to complete the servo loop. Cl is providedto bypass noise from the + l2-volt supply.7.2.7 Write Circuit ElectricalTheory (Refer to Figs. 7-37 and 7-38)The write circuit consists of the following majorblocks: write logic, bias switch, amp enable switch,differential write amp, and the diode switch.7.2.7.1 Write LogicThe write logic consists of UA1C and UCI.UA1C inverts the write protect signal and appliesthis signal to UC1 and to the disk controller VIA.When the output of UA1C is high, the write protectnotch is uncovered. UCI gates the read/write lineonly when the write protect input (pin 6) is high.When gated, the B output of UC1, pin 2, is low.This line turns on the amp enable switch. Addition-'+ally, when writing is enabled, the B output of UC1,pin 40, is high; this is applied to the bias switch. Formore information concerning UC1, see Appendix E.7.2.7.2 Bias SwitchDuring a write operation, the bias switch appliescurrent through the bias winding (U1L2) in theread/write head. One side of the bias switch, Q6,drives the positive side of the bias Winding. Q6 isgated into conduction by the input of UD2F, whichis low when writing. The other side of the biasswitch, Q7, drives the negative side of the biasWinding. Q7 is driven into conduction by the inputof UD2E, which is high when writing. Bias currentflows through U1L2 via Q6, R5l, Q7, CR12, andCR14 (both diodes are forward biased).7.2.7.3 Amp Enable SwitchThe amp enable switch consists of Q3 andUD2B. A low is applied to UD2B while writing,driving Q3 into conduction. When Q3 is conducting,power is applied to the differential write amp.l'CLR123 elKIN1l£A/)lilIlITl~'l~EPOQO!JT 25yo IeY'17-e •iiTR e.2111 YBO 5 ~o.o 2221 'SI .;. 8~ 3'iI~ ;: s§ sy..c 3731 "'. '"32 YU36 vet'-----~~~~-+._t>_.'------+.-t>-.1=;;====~'"eRie",lOOKP6,OPTICSERI'lOR,ACCESSLED'" '" '"'"WltIT[, ,~10 ~/C8 + ~vII'Ole14 Nit14 .../ePltOTECT2 WRITE PROTECT LEO, ""13 GNOFig. 7·37. Schematic of write circuit, Model 1541.

180 Cl541 TROUBLESHOOTING & REPAIR GUIDEWRITE PROTECTFig. 7·38. Block diagram of write circuit, Model 1541.7.2.7.4 Differential Write AmpThe differential write amp consists of UD2C,UD2D, Q4, and Q5. UD2C and UD2D are drivenby the encoder/decoder and, in tum, drive the differentialtransistor pair, Q4 and Q5. When Q5 isconducting, Q4 is turned off. When Q4 is conducting,Q5 is turned off. The outputs of the differentialwrite amp are applied to the read/write head viathe diode switch.7.2.7.5 Diode SwitchThe diode switch consists of CRl5 and CRI8.When in the write mode, the center tap of theread/write winding (UILI) is at ground potentialbecause of bias switch Q7 and CRI4. When Q7goes into conduction, current flows through theread/write winding via either Q4, CRI8, CRI4,and Q7 or via Q5, CRI5, CRI4, and Q7, dependingupon the state of the differential write data fromthe encoder/decoder circuit.7.2.8 Read Circuit Electrical Theory(Refer to Figs. 7·37.7.39. and 7.40)The read circuit senses and amplifies data fromthe floppy disk. The amplified data is checked forvalid pulse widths to improve noise immunity. Theoutput of the read circuit is a narrow pulse whichoccurs on both the rising and falling edges of thedata.The read circuit does not care if the data ishigh or low. Only the positions of the transitions aresignificant. The data is divided into cells. If a transitionoccurs at the beginning of a cell, the cell isinterpreted as a logic 1. If no transition occurs, thecell is interpreted as a logic O.The data is sensed by the read/write head andapplied to the first video amplifier (UF3j via thediode switch (see Fig. 7-37). When in the readmode, Q3, Q6, and Q7 are not conducting. CRl6and CRl7 are forward biased via the read/writewinding (UIU), CRl4 (which is also forward biased),and CRl3 (a 5.2-volt zener diode). Thecathodes of CRl6 and CRl7 are at approximately+6 volts, causing the data to be applied to the firstvideo amplifier (UF3). The +6-volt bias is appliedto the cathodes of CRl8 and CRI5.READ/WRITEDATABITSYNCREAD/WRITEHEADFig. 7·39. Block diagram of read circuit, Model 1541.

Advanced Theory of Operation 181CRI6111141.HEAD"..,9 10KHEAD B'.n11t4!48..,..'"t n, ,~ '2 - I U£:l~ LM311."'""" "'"II474L_ """:~iD-"-1l+5Y~ ".'".. t·,1~~2.2K" "+5'/4--11 'l-~~~ZICLR24011\1RE,I,D/WIliTl_--"'--;';,.J~:~:STEP I"''''" YBOQO~; 25"vava""

182 el541 TROUBLESHOOTING & REPAIR GUIDEThe encoder/decoder is fully integrated intoUC1 on Models 1541 and 1542. The encoder/decoder decodes the serial data which is applied topin 21. Both data and sync information are sepapliedto the comparator via C42, C39, R20, andR22. C42 and C39 block the de offset out of UF4to prevent the offset from affecting the bias on theinput signal of the comparator, UE4. A +6-voltbias is applied to the input signal of the comparatorfrom R16 and R36 via R19 and R21.The output of the comparator is applied to thevalid pulse detector (UD3C, UD4A, and UC1).UD4A, along with C34, R14, andR27, forms anedge detector. Pin 8 of UD3C will produce a 500­nanosecond active high pulse on rising edges ofthe comparator's output and will produce a 150­nanosecond active high pulse on falling edges ofthe comparator's output. The pulse out of UD3Cis applied to UD4A, a single-shot multivibrator.UD4A produces an active low pulse which is approximately2.5 microseconds wide. A flip-flop inUC1 is clocked on the trailing edge of the outputpulse of UD4A. The output of the comparator mustbe maintained for at least 2.5 microseconds inorder to be latched into the flip-flop. If a narrownoise pulse triggers this circuit, the output of theflip-flop will not change since the noise pulse willterminate before UD4A triggers the flip-flop inUCl. The output of UC1, pin 25, will reflect thedata delayed by approximately 2.5 microseconds.The valid data out of the valid pulse detectorpart of UC1 is applied to an edge detector consistingof UD3D and UD4B. UD3D operates the sameas UD3C above. The pulses out of UD3D triggerUD4B, a single-shot multivibrator. UD4B producesa narrow pulse which represents transitions of thedata. This output is applied to the timing circuit viaUC1 to synchronize the encoder/decoder clock,and to the encoder/decoder, which will detect thedata and perform a serial-to-parallel conversion.Notice that pin 5 of UD4A is connected to theread/write line, causing the valid pulse detector tobe disabled during a write operation.The video amplifiers willoften oscillate with nodata in, but these oscillations are high enough infrequency that they seldom get past the valid pulsedetector.7.2.9 Encoder/Decoder ElectricalTheory (Refer to Fig. 7.41)+ 5V (1) (40) BB (2)(39) BRa (3)(38) SOEa (4) UC1 (37) SYNCMTR (5) 235572-01 (38) OEA (6)(35) YB7(7) (34) YB6MTR (8) (33)(9) (32) YB5STEP 1 (10)(31) YB4(11) (30) YB3STEP 0 (12)(29) YB2(13) (28)(14) (27) YBlY3 (15)(26) YBDY2 (16)(25) a OUTYl (17)(24) V INYO(18)(23) ClK INClK (19)(22) lOADGND(2D) '"'L.r- (21) ClRFig. 7-41. Disk controller integrated circuit, Model 1541.rated internally. The separated data is converted toeight parallel bits which are available on pins 26,27,29,30,31,32,34, and 35. Three sync signalsare also provided: bit sync, pin 22; byte sync, pin39; and block sync, pin 37. In order to decode datathe read/write input, pin 36, must be high.When encoding data, the read/write input,pin 36, and write protect input, pin 6, must both behigh. When encoding data, eight parallel bits areapplied to pins 26,27,29,30,31,32,34, and 35.The encoder/decoder converts this byte to serialdata which is encoded into transitions. The differentialencoded data is available at pins 3 and 4.The bit sync and byte sync outputs are availableduring encoding.All timing for the encoder/decoder is derivedfrom the encoder/decoder clock, pin 17. The remainingpins on UC1 are dedicated to other diskcontroller functions. For more information concerningUC1 see Appendix E and encoder/decodertheory for Model 1540, Section 7.1.9.7.2.10 Optics Circuit ElectricalTheory (Refer to Figs. 7-42 and 7.43)The optics circuits consist of DS1 on the caseassembly; DS1, CR1, and Q1 on the drive unit;and UD1F, R46, R45, R55, and R44 on the diskcontroller PC board.R55 provides current limiting for the powerLED DS1 on the case assembly. R46 provides current'limiting for CR1, the optical transmitter, onthe drive unit. Both CR1 on the drive unit and DS1

Advanced Theory of Operation 183+5V~" PWR CEO1 PWR LEDR55 3 PWR LED2202 GND"r---------.,(D=JILED 1~~N~ER:IPWA -:!JtNle 3GNO 2 r- - - - iILI-.JCASE ASSY IJP6, OPTICS.16, OPTICSLED """'-13po... 12 ACCESs/ERROR LEO BV•R" a NIC N/CUOIF'50 ·"/C Nle'/81'06 , N/C NIC•B,NleERROR LED+'V '2 wRITE PROTECTBRWRITE PROTECT LER" +'V 7 NICLT ROWRITE PROTECT1001

184 Cl541 TROUBLESHOOTING & REPAIR GUIDEAIO 15AODRE5S~1114BUS 1312A9 ---"UC2, PIN'237 ----,UC3, PIN 23MODEL 1541~==:~:D-II--II-t>o-~UB2, PINS 18820UC6UC51/4 74LSOO 1/6 74LS04A10 15 AADDRESS '12 14BUS A 13~9 ----. UC2, PIN 237 ----'UC3, PIN 23AI5 12MODEL 15422 -12~ -"'--I-- 131.....J"'"11- 1I,.....-1O----.,UB2, PINS IB 8 20UC7UC61/4 74LSOO 1/6 74LS04Fig. 7-44. RAM/VIA address decoder changes, Model 1542,UC6C'1/4 74LSOOUB4,PIN20......-8-eQ:1;] ~, ""'\...J- 4--B 9UB3 PIN 20 ""'-6 ~5 -4 AI5 ADDRESSUB4, PIN20UB3, PIN 20UC6BUC5D1/4 74LSOO 1/6 74LS04MODEL 1541-'D~J ~AI5II. 7.~~b705erence designator, as even the pin numbers remainthe same, This change is illustrated in Figs. 7-44and 7-45.The computer's write circuit changed fromModel 1541 to Model 1542 (see Fig. 7-46), Inaddition to the reference designator changes, pins 1and 2 on the NAND gate (UC7, Model 1542) havebeen swapped. The inverted read/write line is appliedto pin 2 on Model 1542 instead of pin 1 onModel 1541. Also, the 1/>2 signal is applied directlyto the NAND gate from pin 39 of UC4 on ModelBUS...-6 -4 AI3 ADDRESS BUS4--8 9UC7UC6D1/4 74LSOO 1/6 74LS04MODEL 1542Fig. 7-45. ROM address decoder changes, Model 1542,1542 instead of going through the two buffers firstas it did on Model 1541. Functionally, there is nodifference between Models 1541 and 1542 concerningthis change.The reset circuit on Model 1542 has beenchanged to provide a sharper edge to the reset signal.An inverter with a Schmitt trigger input hasbeen added between C46 and UD3B. Also, UD3Bis configured as a noninverting buffer in Model1542 instead of being configured as an inverter inModel 1541 (see Fig. 7-47).

Advanced Theory of Operation 185VCSAUCSF1/6 74LS04 1/6 74LS04UC4. PIN 39""'-- I ~2 --13 -t>0-'2C UC2 a UC3. PIN 25UC4. PIN 34 ~ 3 -t>o- 4 ~D-3 .... UB2, PIN 21UCSBUC6A1/6 74LS04 1/4 74LSOOMODEL IS41UC6AUC6F1/6 74LS04 1/6 74LS04UC4. PIN 39 L I -t>o- 2 --13i>o-I2---..... UC2 a UC3. PIN 25~ L_ 2, D-3 ......... UB2. PIN 21UC4. PIN 34 ""'--3 ,.....-4UC6BUC7A1/6 74LS04 1/4 74LSOOMODEL 1542Fig. 7-46. Write logic changes. Model 1542.1"SV +5VR25lOOKiOOIIFrC4616VMODEL 1541+SV+SVJUNCTION OFL14 a RBR2S6.aKI C46_ 16VIOOVFMODEL 1542Fig. 7-47. Resel circuitchanges. Model 1542.7.3.2 Drive Motor Servo Circuit(Refer to Figs. 7-48 and 7-49)The drive motor servo circuit in Model 1542 isdrastically different from the drive motor servo circuitused in Model 1541. Although input and outputsignals are the same. the two drive motor servocircuits use different ICs to control motor speed.The following discussion applies to the drive motorservo circuit on Model 1542 (Newtronics driveunit).Tachometer information from the drive motor/tachometerenters the drive motor servo circuitat E4 and E5. This information is applied to Rl andR2. which form a voltage divider as well as a loadfor the tachometer. From the voltage divider. thetachometer information is coupled to ICI. the governor,via coupling capacitor C1. ICI compares thisinformation with a speed standard set by VRl, R3.R4, C2, and ClO.The output of ICl, pin 11. drives the motorcontrol transistor TR2 via R7. TR1 in turn drivesthe drive motor/tachometer. If the tachometer informationindicates that the motor is turning tooslow, then ICI will drive TR2 harder. If. on the

186 Cl541 TROUBLESHOOTING & REPAIR GUIDEi-DRiVE'MOTORsERVOCIRCUIT - iIIII- -'-I+01 IOFF/ON I :ILII...JIi - MClTORITACHOMETER - - -:I TACH MOTOR IIIIIother hand, the tachometer information indicatesthat the motor is turning too fast, ICI will reducethe drive current to TR2. TRI and RIO providecurrent limitingfor the drive motor. When approximately1 ampere is being drawn by the motorthrough RIO and TR2, TRI will turn on, causingthe drive current for TR2 to be shunted around thebase-emitter junction of TR2 via TR1. The governoris disabled (motor turned off) when pin 8 of ICIis high. When pin 8 of ICI is low, the governor isenabled (motor turned on). C3, C5, and R5 filterthe +I2-volt supply line to ICI. R6, R8, C4, C6,and C7 sample motor current changes and providethis information to pins 10 and 12 of ICI.Fig. 7-48. Block diagram of drive motor servo circuit,Model 1542.+12VBR+/2V ~+12V~ CSGNO ~ 10vFoom~8RIIS.6KTACHTACHYLRIi.OKGYI,...-----7R3S.IKR468KICIGOVERNOR14 3 916L-tJC310vF10-----.--1+C4r 047vFTRI25A733R7B20./\CIO +D.033vF ~/ I C2\Y = IO~FDISK 5PEED AD~VAt20KFig. 7-49. Schematic of drive motor servo circuit, Model 1542.RIO0.68./\TR2258633E'--_....._+-""R"'OO MOTOR....------' foGND

APPENDIX ATechnical DataThis appendix provides technical data for theVIC-I541. Included in this appendix are anindex, interconnect diagrams, schematics,parts layouts, and parts lists.The interconnect diagrams illustrate how thevarious connectors are arranged in the VIC-1541.When tracing a signal to a connector, the interconnectdiagram illustrates which subassembly isplugged into that connector. Once the subassemblyis identified on the interconnect diagram, the schematicfor that subassembly may be consulted. Thesignal-tracing process may then continue to thenext schematic. The interconnect diagram is ameans of linkingthe Individual schematics together.The block diagram is a composite simplifiedexplanation of how the individual circuits are logicallyarranged.The schematic diagrams illustrate how all ofthe components are electricallyconnected. Readinga schematic diagram can be an art in itself. Somepeople might not be able to get much informationfrom a schematic, while those with a lot of experiencecould get enough information from a schematicto almost make the rest of the information inthis book redundant. If you are interested in learningmore about reading schemattcs, the followingbook is recommended:A.lHow to Read Schematics, 4th Ed., by DonaldE. Herrington. Howard W. Sams & Co.,1986. (Cat. No. 22457)The parts layouts are simply maps that can beused to locate a part in question. Although mostparts are labeled on the PC board, these labels maybecome illegibledue to dirt, wear, or age. If a referencedesignator is illegible or a part is not labeled(such as motors or LEOs), consult the appropriateparts layout.Like the parts layouts, the parts lists are providedin the event that a part number or color codebecomes illegibledue to burns, dirt, or wear. If youcannot read a part number, consult the appropriateparts list.Section A.l provides an index to individualfigures and listscontained in this appendix.FIGUREA-1A-2A-3INDEX TO TECHNICAL DATAInterconnect DiagramsTInEPAGEBlockDiagram, All ModelsInterconnect Diagram, Model1540. 189. 190Interconnect Diagram, Models 1541 and1542 191187

188 APPENDIX ASchematicsFIGURETmEA-4 Disk Controller Schematic,Model 1540 .A-5 Disk Controller Schematic,A-6A-7A-8A-9A-lOA-11A-12Parts LayoutsPAGE192Model 1541 196Disk Controller Schematic,Model 1542 . . . . . . . . . . . . . . . . .. .. 200Case Assembly, All Models 204Drive Unit Schematic, Models 1540and 1541 204Drive Unit Schematic, Model 1542 , 205Drive Motor Servo Circuit, Models 1540and 1541 . . . . . . . . . . .. 205Drive Motor Servo Circuit, Model 1542 . 206Frame Assembly, All Models 206FIGURE TITLE PAGEA-13 Subassembly Identification,Model 1540 . . . . . . . . . . . . . . . . . . . . . .. 207A-14 Subassembly Identification,Model 1541 .. . . . . . . . . . . . . . . . . . . . .. 208A-15 Subassembly Identification,Model 1542 . . . . . . . . . . . . . . . . . . . . . .. 209A-16 Disk Controller Parts Layout,Model 1540 . . . . . . . . . . . . . . . . . . . . . .. 210A-17 Disk Controller Parts Layout,Model 1541 210A-18 Disk Controller Parts Layout,Model 1542 211A-19 Case Assembly Parts Layout,AllModels 211A-20 Drive Unit Parts Layout, Model 1540 . .. 212A-21 Drive Unit Parts Layout, Model 1541 . .. 212A-22 Drive Unit Parts Layout, Model 1542 . .. 213A-23 Drive Motor Servo Circuit Parts Layout,Models 1540 and 1541 213A-24 Drive Motor Servo Circuit Parts Layout,Model 1542 214A-25 Frame Assembly Parts Layout,Model 1540 214A-26 Frame Assembly Parts Layout, Models1541 and 1542 214SECTIONParts ListsTITlEPAGEA.5 Model 1540 Parts List 215A.6 Model 1541 Parts List 217A.7 Model 1542 Parts List. 219

Fig. A-I. Block diagram, all models.Technical Data 189

190 APPENDIX AA.2 VIC-1541INTERCONNECT DIAGRAMSDISK CONTROLLERTRACK 0E]SELECT 0 J7IoPn{~EJIQQDRIVEMOTOR UUI~~GEJII8e- ~G[jr----------I7IIIIIIIICASE ASSY(PWR LED)DRIVEUNITI I L...---__------'oSERIAL INPUT (l JIDeusPOWERU1........ 1IEJ t,;,FRAMEASSY1.......... ......Fig. A-2. Interconnect diagram, Model 1540.

Technical Data 191DISK CONTROLLERTRACK 0E]SELECT0 J7I~"8EJDRIVEIQQ} I DRIVEIUNIT}MOTORLJLJI"..-88ICASE ASSYII(PWR LED)8~OL ~8EJI-------~~~~ .....8~ =,d"11--- 1} I I}1FRAME ASSY8t,;,11-. _Fig. A-3. Interconnect diagram, Models 1541 and 1542.

192 APPENDIX AA.3 VIC-1541 SCHEMATICS,..IN400Z§~!r:lr====;--=-:;;i:l. ~-'--o-"'''-+----''"''--~IN400ZI+-:c+z-+---

Technical DataII'S-"M.LIlQI.,.OIlIAIll!'n,.'.... UNLIllSI, ~=.:::r~I),"OHMS3,fHllil'OU.O'lWtG ...' ..... CoflPj\Q'f0lll .....CONMfCTtDeETWefNlltf .. 5VlIOttANDOIIOUNO....I,.I.T_CAPAClTORSlISTEDoUOEo.. ~f,Cf""'''1Cce C7 CI CI1C"CltC20ct'CIlIeltC30C:I1C3ZC3IC3llC31C31C31g::;::::f::;::coecoeC01cq-­.(,!''''NDu"'OO"".. tHeOlSll.CONTAOLLEIIIAOOAUS========== :~ ~~'-: ::...u '.TWU·•• =·.!loU -Il· ~======;-;:J¢==#~ :"" .t::: .. f-""--~f­H.'f.t>:.:--~Q:'1~MU04.!.L4~schematic, Model 1540.

194 APPENDIX A'" .-~,11141.' .~t o.oa"....... "'"~='2J1~~1000....'"no0.1_'~.tn ~.- ,~,..... ~.... ...- :)C>l:~'"l~.. ṫun.~~==1==========t===f:6-'.7'UID'+.::::¢>~--1/,74LaOO..\rT;Q:__ -4- -::1/47....00------.~.------­'" NOFig. A-4. Diskcontroller

Technical Data 195..,~:'7"" ,R45 a PWR L~O220 2011D' .......lIlfSl.T.uoctI&Vl_U(D'NotNSUNLESllOTIlERWlIEOIOTEO3. THE FOLLOWING BYPASIICAPACrfOI'SAII'ECONNECTEO l£TWffN THE • ~~ LINE...0GIIOUI«lALlTItEHCAPAC,TOllSUSTEOAMD' ~F.CI'IlA"1CC1I cr ClI CHC"C"QlI~'cn~ C$l~'C32C3l1C3l1C31C31C31coo CO. COl c.) C«l CO$ COl CIT COlC53 cw CSlI C«I ct--"-1>--,~~......'"141T ~"...~- ,-1>-• ...~.. I.DIlLED ~II-t>o-'QUf2E,..,-IQII.SO.,zv-OPfAlf~~QIIl/ilCCUILEO~.~.~'MIfTEI'IIOTECT10 - Nle ~••WII Mle14 Nit" ~, " -I Wlt/TlPItOTECT LrD~".W 1117411IlllADA"UOI'"...schemallc, Model 1540 (conI.)

196 APPENDIXA:~~ rnr===:::;----:~b.II .~ '>'-~-'-"=-+---I +~M~+r-+-....--..------.-1t. AollllUlaTOAS"'flll0'llo,.I'I. UNLUSNOTEDa, ,t,U RUlStANCE " EXPIlEM£O IN OHM'UNUM OTHEIIWlIENOTED3. THE FOt.~OWING IYPASS CAPACltoRI"'''ECOfrINECTlEOIE'fWEEN1HE +S~UNEANOGROuND ALL THEH CJIlPAClTOI'I8LIlTEDAREO.l ~F,CEIlAMICCl C7 ce ClICl,C20CUC23ca. as calal Cal ca C30.~, El.NOUI"flOQIUlMTtlEDlI'"COfIlTIlOI..LEIIAOOIIIII,,"". "...".CLOSED"'.CLOSEDccceee-AOORE/lll'" "'.117 UAIIlOW ''''~$l~$(~::'~gr1~~i;~~~-f''''''lI~·-t>o-·_-----------+----,iiiffi....... SlllllfOnllCkl10.....TNI/OSU04U,/O"'"WAIIIIQVO-..1.0K"~ID1,IT4U14E-3 I~E----Fig. A-5. Diskcontroller

Technical Data 197~~~~--:----------------------~:------------1L" I" I,--+-4-4---'-'-"-f-, L$ :c:J .. 4'l~0 ' ..I 00.8. I IIIIIL$ II,I., "'I',I"~~_TCI~:='I CLQCII- ,II___________ .J'frl:-; .===================~:L;l~~~i~ :~2~~120ICDTO,+f~ =~L-_~ __~,_~::r.;~;-......-.t.,.......,============ :':; E 10=l7 ;"II .T~==rfOI7" D7 ... S?+---o__--f.jfJ~ :;;,"12 lllII'fIPU~ :: .: :============== ':: ., .. '-+-:_ __O_---.J""11~. ~1 20 .-II;: .: ez ·Slt_L&::: v.'YI.III1r.~schematic, Model 1541.

~,198 APPENDIX A." ocI~••,~j~/",":,i:' i".;.'~~ISEl.~IOSTEP'OH/6FF~BMTRS8YHSY'lCEN~:JlIALLRE81UORS AI'IElo"'.'Aw UNUUJrlOJ(OENCOOERfOECOOERClOC~~~ClK",,"0"""'-26 vee

~,~,Technical Deta 199-~:~:,~"~55 3 PWJI LED220 2 GNO-----------.-,-t>-.. ~-L-.LF\1/67417----------+.-t>-.-------+'-t>-'1=;====:.e••"414BLE\l~13~1Z 1~63,117_,,,."~'~O"/Acens LED."wRlTEl'lIOTECTr "10 Nit, .~14 Nle14 Nle2 WRITE ~"onCT LEO, ,~13 IlNIl"-t>-,, -~L--f.t·1lJ)2F 1.3I/BUIT...HUll A,HU08smschematic, Model 1541 (cont.)

~,200 APPENDIXA~1,INl't.IT'lWN~'-"'-+--'1,.~~+' ---+-~---.------.-­J..IH400~ION'I$14LS14';'~~i~m~~lL'.J>o-·------+--,IU::~ +~ 4;:d-1-------~---_hGNO 1/674001KIIC.,IO_.TIlI/O."'GArAI/OiiDiT$("_1101, oU.I.RUllTOfl8 .....El0......... "'LINU8$~2. ~=:r:~~::-m'"OHM'J.TNI'OLLOWIHO.Y'.... CAPACITOflSAfllCOtI.. ICT(OllElWEENTHE.5VLlNE .....OGIlOUNO.ALLTHUECAl"ACITOfIlIUSno...MO.'llf . CIMMIC..ADol'lESS~.CLOUD "ClOSEO~.uelOHOCLOROOPENOPENea Cl CII el, Cli c:ao C22 Q3CH~enarcaCl'lC3DFig. A-6. Diskcontroller

Technical Data 201r;;V~L~--- - - ~ ~ - - - - - - -- - --- - - -- - - -, ~ ~------------,Z,hll LZ I I IIII1"I:::""I:~'" I"~_+-+__---C.-'I,-'----1~ Ii',:, :[32]".~',: cur • (::~~G '"',' I r;::=::. ~':' • :" 00" '€l:'~'~"-"-'-l ::_____________________________ ~Lr-fȯ" ~ i.~ l:" :: ;.:.,) L :",""II _I___________ -Jschematic, Model 1542.

202 APPENDIXANOTES:1. ALL RESISTORS ARE 10%, 1I4W UNLESSNOTED.-.UAIC 20"""" ~2. ALL RESISTANCE IS EXPRESSED IN OHMSUNLESS OTHERWISE NOTED.3. THE FOLLOWING BYPASS CAPACITORS ARE•.CONNECTED BETWEEN THE+5V LINE ANDGROUND. ALL THESE CAPACITORS LISTEDARE 0.1 ~F, CERAMIC.C6 C7 C8 C18 C19 C20 C22 C23C24 C25 C28 C27 C28 C29 C30E1 AND £2 PROGRAM THE DISKCONTROLLER ADDRESS.ADDRESS8•to"etCLOSEDOPENCLOSEDOPEN'2ctoseoCLOSEDOPENOPEN..~!."-I>-'O~---_Fig. A-6. Disk controller

Technical Data 203'H'"'"IUD"".~~ .....'''.I ?Wll LEO"" :5 PWR LED220 2 GIlDL.::""•-/>0-...." ""' ..PT,fllA,CKSELECT,-t>-.".""roo'00."7 ."-ell'.~"'I~2SA733~..-t>-.-t>-."'"$C94$elll},,. I/IIM'TUD2e'1/6741113-£>0-12Cilia." 1o-12 11.3~~~o" ....ccus LEDVOl' 1501/61_." '"_""",_",,","--1 7 ;iITE I'fIOTtcT10 'lie..~II Ill(;'of fUCI. ,""Ct----F===:::::::=1===~r;l::::...:om~ :",:E PROTECT LEO'SONDschematic, Model 1542 (cont.)

204 APPENDIX A.18(1540).1405411J4(154Z)PWRLEDN'

Technical Data 205...IIIUNlC........"....D.....,NI, OPTICS"I< "'"mliiiUl> ""WRITE. PftOTECTlE.wtmE PflOTEeT"I

206 APPENDIX A+I2VBR+12V ~+12VC310pFTRI2SA733RIO0.681\~ C5GNO ~ 10pFENIm~BRII5.6KTACHTACHYLRII.OKGYICIGOVERNOR10-----...----1R78201\TR22SB633EL-_....~--jf-.:.:RO"oMOTOR,.-----7R35.IKCIOR4'68KrO.033PF ~/DISK SPEE0 AO~VRI20k4' 3 9 16IfI C2-e- 10pFC4'r 047pF12- ....-VV"""' 'V'v"v----j+Fig. A-It. Drive motor servo circuit,Model 1542.DRJI,AC INPUTole HIONDole LO16V 029V 013 9V 021I1SVAC,50-80HzFig. A-12. Frame assembly. all models.

Technical Data 207A.4 VIC-1541 PARTSLAYOUTSCASE ASSY(TOP HALF).4.3DISK CONTROLLERPC BOARDJ6J7FRAMEABSYCASE ASSY(BOTTOM HALF)IiFig. A-l3. Subassembly identification, Model 1540.

208 APPENDIX ACASEABBY(TOPHALF)p,p,J,FRAMEASBYFig. A·14. Subassembly identification, Model 1541.

Technical Data 209CASE ASSY(TOP HALF)Fig. A-IS. Subassembly Identification. Model 1542.

210 APPENDIX AFig. A-16. Diskcontroller parts layout. Model 1540.Fig. A-17. Diskcontroller parts layout, Model 1541.

Technical Data 211Fig. A-IS. Disk controller parts layout, Model 1542.Fig. A-19. Case assembly parts layout, all models.

212 APPENDIX AQ'CR'OS,Fig. A·20. Drive unit parts layout, Model 1540.OS,Fig. A-21. Drive unit parts layout, Model 1541.

Technical Data 213VRI~@[JC3~ICI-c:::J- -c:::J-RIOR2os-Fig. A·22. Drive unit parts layout, Model 1542.-=-~:;~-r-r!!8 CRS RT GOon C90 ~RI ~R3QI V~ CM ~R4 yo-OCT RI ROEI.+12VE2,ON/OFFE3,GNDE4,TACHES,TACHE6,M+Fig. A-23. Drive motor servo circuitparts layout, Models 1540 and 1541.

214 APPENDIX A® "0 ~~8B~gg --j '" f---1'" ~OC7 -uD- OC8a:: lei ~ ~ __...-Gilfl3~® g =BEt@--Q;oFig. A-24. Drive motor servo circuit parts layout. Model 1542.~-...._- 8ROWN~-...._. 8LACKORANGERED8LlIEYELLOW~RAYF1FlJ'51Fig. A-25. Frame assembly parts layout, Model 1540.Fig. A-26. Frame assembly parts layout,Models 1541 and 1542.

Technical Data 215A.5 MODEL 1540 PARTSLISTA.5.lDisk Controller PC Board (cont.)A.5.lDisk Controller PC BoardDESIGNATOR DESCRIPTION VALUE/PART NUMBERCI Capacitor 1.0~F, 50VC2 Capacitor 47~, 16 VC3 Capacitor 0.1 ~FC4 Capacitor 1.0~, 50VC5 Capacitor 47~, 16 VC6 Capacitor O.I~C7 Capacitor O.I~C8 Capacitor O.I~C9 Capacitor 0.1 ~FCIO Capacitor 68pFcn Capacitor 0.1 ~FCI2 Capacitor 1O~,25VCI3 Capacitor O.I~FCI4 Capacitor 0.1 ~FCI5 Capacitor 0.47 ~F, 35 VCI6 Capacitor 680pFCI7 Capacitor O.I~CI8 Capacitor O.I~CI9 Capacitor O.I~C20 Capacitor 0.1 ~FC21 Capacitor O.I~FC22 Capacitor O.I~FC23 Capacitor 3.3~F, 25 VC24 Capacitor 0.47~, 35VC25 Capacitor 0.1 ~FC26 Capacitor 1000 pFC27 Capacitor 680pFC28 Capacitor 330pFC29 Capacitor O.I~C30 Capacitor O.I~C31 Capacitor O.I~C32 Capacitor 0.1 ~FC33 Capacitor 150pFC34 Capacitor 0.1 ~FC35 Capacitor 0.1 ~FC36 Capacitor O.I~FC37 Capacitor 0.1 ~FC38 Capacitor 0.1 ~FC39 Capacitor 0.1 ~FC40 Capacitor 0.1 ~FC41 Capacitor O.I~C42 Capacitor 0.1 ~FC43 Capacitor O.I~C44 Capacitor O.I~FC45 Capacitor O.I~FC46 Capacitor 0.1 ~FC47 Capacitor 0.1 ~FC48 Capacitor O.I~C49 Capacitor 330pFC50 Capacitor 680pFC51 Capacitor 6800 ~F, 25 VC52 Capacitor IO,OOO~, 16 VC53 Capacitor 0.1 ~FC54 Capacitor O.I~FC55 Capacitor 0.1 ~FC56 Capacitor lOO~, 15VC57 Capacitor 0.1 ~FDESIGNATOR DESCRIPTION VALUE/PART NUMBERC58 Capacitor .022 ~FC59 Capacitor .022~C60 Capacitor 0.1 ~FC61 Capacitor O.I~C62 Capacitor 4.7 ~FC63 Capacitor 1.0~FC64 Capacitor 0.1 ~FC65 Capacitor 220~F, IOVCRI Bridge Rectifier 8241CR2 Diode IN4002CR3 Bridge Rectifier 8240CR4 Diode IN4002CR5 Zener Diode 3.3VCR6 Diode IN4148CR7 Diode IN4148CR8 Diode IN4148CR9 Diode IN4148CRIO Diode IN4148CRIl Diode IN4148CRI2 Zener Diode 5.2VCRI3 Diode IN4002CRI4 Diode IN4002CRI5 Diode IN4002CRI6 Diode IN4002CRI7 Diode IN4002FI Fuse 3AGIA250VLlI Inductor L2 Inductor L3 Inductor L4 Inductor L5 Inductor L6 Inductor L7 Inductor L8 Inductor L9 Inductor LlO Inductor LlI Inductor Ll2 Inductor Ll3 Inductor Ll4 Inductor Ll5 Inductor Ll6 Inductor*QI Transistor 2SA952Q2 Transistor 2SC945Q3 Transistor 2SC945Q4 Transistor 2SC2001Q5 Transistor 2SC2001Q6 Transistor 2SC2001Q7 Transistor 2SC2001Q8 Transistor 2SAlOI5Q9 Transistor 2SAI015QIO Transistor 2SAlOI5QIl Transistor 2SAI015RI Resistor, ~ W 33011R2 Resistor, ~ W 33011R3 Resistor, ~ W 4711R4 Not UsedR5 Resistor, ~ W 330 IIR6 Resistor, ~ W 1.0kllR7 Resistor, ~ W 22 kllR8 Resistor, ~ W 9111,1.0%/

216 APPENDIX AA.5.1 Disk Controller PC Board (cont.) A.5.1 Disk Controller PC Board (cont.)DESIGNATOR DESCRIPTION VALUE/PART NUMBERR9 Resistor, ~W 68011R10 Resistor, \ W 22 kllR11 Resistor, ~W 1.10 kllR12 Resistor, J4W 9.10 kllR13 Resistor, J4W 9.10 kllR14 Resistor, ~W 2.2kllR15 Resistor, y,.w 2.2kllR16 Resistor, Y.w 22011R17 Resistor, Y.w 22011R18 Resistor, Y.w 15011R19 Resistor, Y.w 15011R20 Resistor, Y.w 33011R21 Resistor, Y.w 3.0kllR22 Resistor, Y.w 3.0kllR23 Resistor, Y.w 3.0kllR24 Resistor, Y.w 51011R25 Resistor, Y.w 36011R26 Resistor, Y.w 2.2kllR27 Resistor, Y.w 47011R28 Resistor,1f,.W 47011R29 Resistor, %W 22 kllR30 Resistor, y,.w 36011R31 Resistor, Y.w 1.0kllR32 Resistor, Y.w 1.0kllR33 Resistor, Y.w 1.0kllR34 Resistor, Y.w 1.0kllR35 Resistor, Y.w 15011R36 Resistor, Y.w 15011R37 Resistor, %W 33011R38 Not UsedR39 Resistor, Y.w 68011R40 Resistor, Y.w 68011R41 Resistor, y. W 68011R42 Resistor, y.W 68011R43 Resistor, y.W 1.0kllR44 Resistor, %W 100kllR45 Resistor, y.W 220 IIR46 Not UsedR47 Resistor. y. W 47011R48 Resistor, y.W 1.5kllR49 Resistor, %W 10011R50 Resistor, y.W 47011R51 Resistor, y.W 2.2kllR52 Resistor, y.W 2.2 kllR53 Resistor, Y.w 22kllR54 Resistor, y.W 150 IIR55 Resistor, y.W 47011R56 Resistor, Y.w 2.2 kllR57 Resistor, Y.w 47011R58 Resistor, Y.w 1.0kllUA2 1024 X 4-BItStatic RAM 2114L3UA3 1024 X 4-Bit Static RAM 2114L3UAB1 Versatile Interface Adapter 6522UAB4 8K X 8 ROM 235302-01UAB5 8K X 8 ROM 981229-01UB2 1024 X 4-Bit 5tatic RAM 2114L3UB3 1024 X 4-Bit Static RAM. 2114L3UB6 Hex Inverter 74LS04UB7 Quad 2-Input Pas. NANDGate74LSOOUBB BCD-ta-Decimal Decoder 74LS42DESIGNATOR DESCRIPTION VALUE/PART NUMBER* Values not availableA.5.2VCI Hex Schmitt-TriggerInverter 74LS14UC2 13-lnput Pos. NANDGate 74LS133uca Octal Bus Transceiver 74LS245UC6 Binary Presettable Counter/Latch74LS197UC? Quad 2·Input Pas. NOR Gate 7402UCD4 Versatile Interface Adapter 6522UCD5 8-Blt Microprocessor 6502UOI Hex Inverter Buffer/Driver 7406UD2 8-Bit Parallel Output SerialShift Reglster74LSl64UD3 ParallelLoad 8-Bit ShiftRegister withComplementary Outputs 74LS165UE2 Oual2- to 4-Line Decoder!Multiplexer74LS139UE3 Binary Synchronous Up/DownCounter74L5191UE4 Dual-DFlip-flop 74LS74UE5 Quad 2-Input Pos. NOR Gate 74LS02UE? Binary w/Clear SynchronousUp/Down Dual ClockCounter74LS193UF2 Hex Inverter Buffer/Driver 7406UF3 Triple 3-Input Pas. NANDGate74LSlOUF4 Binary w/Clear SynchronousUp/Down Dual ClockCounter74LS193UF5 Quad 2-lnput Pos. NANDGate74LSOOUF6 Dual-DFlip-Flop 74LS74UG1 Hex Schmitt-TriggerInverter 74LS14UG2 Quad 2-lnput Exclusive-ORGate74LS86UG3 Dual Retrlggerable ResettableMonostable Multivlbrator 9602UG4 Hex Buffer/Driver 7417UH4 Comparator w/Open CollectorOutputLM311UH5 DifferentialVideo AmpUfier NE592NUH7 DifferentialVideo Amplifier NE592NY1 Crystal 16 MHzDESIGNATORC1C2C3C4C5C6C7C8C9CR1Drive Motor Servo CircuitDESCRIPTIONCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorDiodeVALUE/PART NUMBER10 "F, 35V4700 pF0.033"F, 100 V0.47 "F, 35V1O"F,35V1O"F,35V0.47 "F, 35 V0.013 "F, 10%0.47,.F,35V1N4148

"Technlcal D.t. 217A.5.2Drive Motor Servo Circuit (cont.)A.6.1Disk Controller PC Board (cont.)DESIGNATORDESCRIPTIONVALUE/PART NUMBERDESIGNATOR DESCRIPTION VALUE/PART NUMBERA.6 MODEL 1541 PARTSLISTA.6.1CR2CR3CR4CR5ICIQlQ2Q3Q4HIR2R3R4R5R6R7R8RIOVRIDtodeDlodeDiedeDiodeSpeed ControllerTransistorTransistorTransistorTransistorResistorResistorResistorResistorResistorResistorResistorResistorResistorVariable ResistorDisk Controller PC Board1N41481N41481N41481N4148Sony 246325C278525C278525A101525B569lOkll68kll220113.3kll2.7kll8201110 kll0.6811,3W3.32 kll20kllDESIGNATOR DESCRIPTION VALUE/PART NUMBERC1 Capacitor 1.0"",50VC2 Capacitor 47 ~F, 16VC3 Capacitor 0.1 ~FC4 Capacitor 1.0~F,50VC5 Capacitor 47 ~F,16 VC6 Capacitor O.l~FC7 Capacitor O.l~FC8 Capacitor O.l~FC9 Capacitor O.l~FClO Capacitor 0.1 ~FCll Capacitor 1.0~FC12 Capacitor 0.33 ~FC13 Capacitor 220~F, 25VC14 Capacitor 1.0~FC15 Capacitor 1O"",25VC16 Capacitor 4700~F, 16VC17 Capacitor 6800 ~F, 25 VC18 Capacitor 0.1 ""C19 Capacitor 0.1""C20 Capacitor 0.1 ""C21 Capacitor4.7 ""C22 Capacitor 0.1 ~FC23 Capacitor 0.1 ~FC24 Capacitor 0.1 ~FC25 Capacitor 0.1 ~FC26 Capacitor 0.1 ~FC27 Capacitor 0.1 ~FC28 Capacitor 0.1 ~FC29 Capacitor 0.1 ~FC30 Capacitor O.l~FC31 Capacitor 150pFC32 Capacitor 330pFC33 Capacitor 680pFC34 Capacitor 680pFC35 Capacitor 0.1 ~FC36 Capacitor 330pFC37 Capacitor 0.47 ~F, 35VC38 Capacitor 0.47"",35 VC39 Capacitor 0.022 ~FC40 Capacitor 0.1 ~FC41 Capacitor 1000 pFC42 Capacitor 0.022 ~FC43 Capacitor0.1 ""C44 Capacitor 3.3"",25VC45 Capacitor 680pFC46 Capacitor 100 ~F, 15 VC47 Capacitor 0.1 ~FC48 Capacitor 0.1 ~FCR1 Bridge Rectifier 8241CR2 Diode 1N4002CR3 Bridge Rectifier 8240CR4 Diode 1N4002CR5 Zener Diode 3.3VCR6 Diode 1N4148CR7 Diode 1N4002CR8 Diode 1N4002CR9 Diode 1N4002CRlO Diode 1N4002CRll Diode 1N4002CR12 Diode 1N4148CR13 Zener Diode 5.2VCR14 Diode 1N4148CR15 Diode 1N4148CR16 Diode 1N4148CR17 Diode lN4148CR18 Diode 1N4148Ll Inductor 2.2~HL2 Inductor L3 Inductor L4 Inductor L5 Inductor L6 Inductor L7 Inductor*L8 Inductor 100~HL9 Inductor LlO Inductor Lll Inductor Ll2 Inductor Ll3 Inductor Ll4 Inductor Ll5 Inductor Ll6 Inductor*Q1 Transistor A952Q2 Transistor C945Q3 Transistor 25A1015Q4 Transistor 25A1015Q5 Transistor 25A1015Q6 Transistor 25A1015Q7 Transistor 25C945Q8 Transistor 25C2001Q9 Transistor 25C2001

218 APPENDlXAA.6.1Disk Controller PC Board (cont.)A.6.1Disk Controller PC Board (cont.)DESIGNATOR DESCRIPTION VALUE/PART NUMBERQlO Transistor 25C2001Qll Transistor 25C2001R1 Resistor, %W 4711R2 Resistor, '4W 1.0kllR3 Resistor, if,. W 33011R4 Resistor, y,.w 22011R5 Resistor, %W 1.0kllR6 Resistor, '4W 1.0kllR7 Resistor, y,.w 1.0kllR8 Resistor, %W 1.0kllR9 Resistor, '4W 2.0kllRlO Resistor, '4W 2.0kllRll Resistor, '4W 2.2kllR12 Resistor, '4W 22kllR13 Resistor, '4WR14 Resistor, '4W 36011R16 Resistor, '4W 20011R17 Resistor, y,.w 15011R18 Resistor, y,.w 15011R19 Resistor, y,.w 36011R20 Resistor, y,.w 47011R21 Resistor, y,.w 2.2kllR22 Resistor, y,.w 47011R23 Resistor, y,.w 33011R24 Resistor, y,.w 36011R25 Resistor, y,.w 1.0kllR26 Resistor, y,.w 2.0kllR27 Resistor, %W 51011R28 Resistor, y,.w 10011R29 Resistor, '4W 15011R30 Resistor, YeW 47011R31 Resistor, '4W 33011R32 Resistor, %W 2.2 kllR33 Resistor, '4W 2.2 kllR34 Resistor, %W 2.2kllR35 Resistor, %W 22kllR36 Resistor, '4W 22011R37 Resistor, '4W 47011R38 Resistor, '4W 47011R39 Resistor, y,.w 22kllR40 Resistor, y,.w 1.5kllR41 Resistor, '4W 47011R42 Resistor, y,.w 68011R43 Resistor, y,.w 1.0kllR44 Resistor, '4W 100kllR45 Resistor, y,.w 15011R46 Resistor, y,.w 15011R47 Resistor, y,.w 68011R48 Resistor, y,.w 68011R49 Resistor, y,.w 68011R50 Resistor, y,.w 68011R51 Resistor, y,.w 9111,1%R52 Resistor, ~ W 22kllR53 Resistor, ~ W 910 kllR54 Resistor, ~ W 910kllR55 Resistor, ~ W 22011UA1 Hex Schmitt-TriqgerInverter 74LS14UBI Hex Inverter Buffer/Driver 7406UB2 2KX8RAM 2016UB3 8KX8ROM 235302-01UB4 8K X 8 ROM 901229-03DESIGNATOR DESCRIPTION VALUE/PART NUMBERUC1 LogicArray 325572-01UC2 Versatile Interface Adapter 6522UC3 Versatile Interface Adapter 6522UC4 8·Blt Microprocessor 6502UDI Hex Inverter Buffer/Driver 7406UD2 Binary w/Clear SynchronousUp/Down Dual ClockCounter74LS193UD3 Quad 2-lnput Exclusive-ORGat.74LS86UD4 Dual Retriggerable ResettableMonostable Multivibrator 9602UD5 Binary Presettable Counter/Latch74LS197UE4 Comparator w/Open CollectorOutputLM311UE6 Binary w/Clear SynchronousUp/Down Dual ClockCounter74LSl93UF3 DifferentialVideo AmpUfier NE592NUF4 DifferentialVideo Amplifier NE592NY1 Crystal 16 MHz·Values not availableA.6.2Drive Motor Servo CircuitDESIGNATOR DESCRIPTION VALUE/PART NUMBERC1 Capacitor lO~F, 35VC2 Capacitor 4700 pFC3 Capacitor 0.033 ~F, 100 VC4 Capacitor 0.47 ~F, 35 VC5 Capacitor lO~F, 35VC6 Capacitor lO~F, 35VC7 Capacitor 0.47 ~F, 35VC8 Capacitor O.o13,.F,1O%C9 Capacitor 0.47 ~F, 35VCR1 Diode 1N4148CR2 Diode 1N4148CR3 Diode 1N4148CR4 Diode 1N4148CR5 Diode 1N4148IC1 Speed Controller Sony 2463Q1 Transistor 25C2785Q2 Transistor 25C2785Q3 Transistor 25A1015Q4 Transistor 25B569R1 Resistor 10 kllR2 Resistor 68 kllR3 Resistor 22011R4 Resistor 3.3kllR5 Resistor 2.7 kllR6 Resistor 82011R7 Resistor 10 kllR8 Resistor 0.6811,3WRlO Resistor 3.32kllVR1 Variable Resistor 20 kll

Technical Data 219A.7 MODEL 1542 PARTSLISTA.7.1Disk Controller PC Board (cont.)A.7.1Disk Controller PC BoardDESIGNATOR DESCRIPTION VALUE/PART NUMBERC1 Capacitor 1.0"",50VC2 Capacitor 47 ~F,16VC3 Capacitor 0.1 ""C4 Capacitor 1.0"",50VC5 Capacitor 47~F,16VC6 Capacitor 0.1 ~FC7 Capacitor 0.1 ~FC8 Capacitor 0.1 ~FC9 Capacitor 0.1 ~FCIO Capacitor 0.1 ~FCll Capacitor 1.0~FC12 Capacitor 0.33 ~FC13 Capacitor 220 ~F, 25 VC14 Capacitor 1.0~FC15 Capacitor 1O"",25VC16 Capacitor 4700 ~F, 16 Vcn Capacitor 6800 ~F, 25 VC18 Capacitor 0.1 ~FC19 Capacitor 0.1 ~FC20 Capacitor 0.1 ~FC21 Capacitor 4.7 ~FC22 Capacitor 0.1 ~FC23 Capacitor 0.1 ""C24 Capacitor 0.1""C25 Capacitor 0.1 ""C26 Capacitor 0.1 ~FC27 Capacitor 0.1 ""C28 Capacitor 0.1 ~FC29 Capacitor 0.1 ~FCOO Capacitor 0.1 ~FC31 Capacitor 150pFC32 Capacitor 330pFC33 Capacitor 680pFC34 Capacitor 680pFC35 Capacitor 0.1 ~FC36 Capacitor 300pFC37 Capacitor 0.47 ~F, 35VC38 Capacitor 0.47 ~F, 35VC39 Capacitor 0.022 ~FC40 CapacitorC41 Capacitor0.1 ""1000 pFC42 Capacitor 0.022 ~FC43 Capacitor 0.1 ~FC44 Capacitor 3.3~F, 25VC45 Capacitor 680~FC46 Capacitor 100 ~F, 15 VC47 Capacitor 0.1 ~FC48 Capacitor O.l~FCR1 Bridge Rectifier 8241CR2 Diode 1N4002CR3 BridgeRectifier 8240CR4 Diode 1N4002CR5 Zener Diode 3.3VCR6 Diode 1N4148CR7 Diode 1N4002CR8 Diode 1N4002CR9 Diode 1N4002DESIGNATOR DESCRIPTION VALUE/PART NUMBERCRIO Diode 1N4002CRll Diode 1N4002CR12 Diode 1N4148CR13 Zener Diode 5.2VCR14 Diode 1N4148CR15 Diode 1N4148CR16 Diode 1N4148CR17 Diode 1N4148CR18 Diode 1N4148Ll Inductor 2.2~HL2 Inductor L3 Inductor L4 Inductor L5 Inductor L6 Inductor L7 Inductor*L8 Inductor 100~HL9 Inductor LlO Inductor Lll Inductor Ll2 Inductor Ll3 Inductor Ll4 Inductor Ll5 Inductor Ll6 Inductor*Q1 Transistor A952Q2 Transistor C945Q3 Transistor 25AlO15Q4 Transistor 25AlO15Q5 Transistor 25AlO15Q6 Transistor 25AlO15Q7 Transistor 25C945Q8 Transistor 25C2001Q9 Transistor 25C2001Q10 Transistor 25C2001Qll Transistor 25C2001R1 Resistor, y.. W 47lJR2 Resistor, ~W 1.0klJR3 Resistor, ~W 330lJR4 Resistor,J4W 220lJR5 Resistor,~W 1.0klJR6 Resistor, y.. W 1.0klJR7 Resistor,J4W 1.0klJR8 Resistor,J4W 1.0klJR9 Resistor,J4W 2.0klJR10 Resistor,J4W 2.0klJRll Resistor,y..W 2.2 klJR12 Resistor,J4W 22klJR13 Resistor,'kWR14 Resistor,y..W 360lJR16 Resistor,%W 200lJR17 Resistor,'kW 150lJR18 Resistor,%W 150lJR19 Resistor,'kW 360lJR20 Resistor,"%W 470lJR21 Resistor,%W 2.2klJR22 Resistor,%W 470lJR23 Resistor, 'k W ·330lJR24 Resistor, 'k W 360lJR25 Resistor, %. W 1.0klJR26 Resistor, 'k W 2.0klJ

220 APPENDIX AA.7.1 Disk Controller PC Board (cont.) A.7.2 Drive Motor Servo CircuitDESIGNATOR DESCRIPTION VALUE/PART NUMBER DESIGNATOR DESCRIPTION VALUE/PART NUMBERR27 Resistor, %W 51011 CI Capacitor 1.0~F, 50VR28 Resistor, y,.w 10011 C2 Capacitor 1O~,35VR29 Resistor, %W 15011 C3 Capacitor 1O~F,35VR30 Resistor, %W 47011 C4 Capacitor 0.47 ~,50VR31 Resistor, %W 33011 C5 Capacitor lO~F, 35VR32 Resistor. %W 2.2kll C6 Capacitor 0.068 ~F, 50 V,R33 Resistor, %W 2.2kll 10%R34 Resistor, Y.w 2.2kll C7 Capacitor 2.2~F, 50VR35 Resistor, %W 22kll C8 Capacitor 0.47 ~F, 50VR36 Resistor, %W 22011 C9 Capacitor lOOpF,50V,R37 Resistor, y,.w 47011 10%R38 Resistor, %W 47011 CIO Capacitor 0.033~, rooR39 Resistor, y..w 22kll V,IO%R40 Resistor, %W 1.5kll ICI Governor LAG 570R41 Resistor, %W 47011 RI Resistor 1.0kllR42 Resistor, Y.W 68011 R2 Resistor 1.0kllR43 Resistor. %W 1.0kll R3 Resistor 5.1 kll, 3%R44 Resistor, Y.w lOOkll R4 Resistor 68kll,l%R45 Resistor, %W 15011 R5 Resistor 10011R46 Resistor, %W 15011 R6 Resistor 3.3kllR47 Resistor, %W 68011 R7 Resistor 82011R48 Resistor, %W 68011 R8 Resistor 2.7kllR49 Resistor, %W 68011 R9 Resistor 15011R50 Resistor, -y.w 68011 RlO Resistor 0.6811,3 WR51 Resistor, %W 9111,1% Rll Resistor 5.6kllR52 Resistor, %W 22kll TRI Transistor 2SB633ER53 Resistor, y,.w 910kll TR2 Transistor 2SA733R54 Resistor. %W 910kll VRI Variable Resistor 20kllR55 Resistor, y,.w 22011UAI Hex Schmltt·Trigger Inverter 74LSI4UBI Hex Inverter Buffer/Driver 7406UB2 2KX8RAM 2016UB3 8K X 8 ROM 235302-01UB4 8K X 8ROM 901229-05UCI Logic Array 325572-01UC2 Versatile Interface Adapter 6522UC3 Versatile Interface Adapter 6522UC4 8-Blt Microprocessor 6502UC6 Hex Inverter 7713UC7 Quad 2·1nput Pas. NANDGate74LSOOUC8 BCD-to-Declmal Decoder 74L542UDI Hex Inverter Buffer/Driver 7406UD2 Binary w/Clear SynchronousUp/Down Dual ClockCounter74LSI93UD3 Quad 2·lnput Exclusive-OftGate74LS86UD4 Dual Retrlggerable ResettableMonostahle Multivlbrator 9602UD5 Binary Presettable Counter/Latch74LSI97UE4 Comparator w/Open CollectorOutputLM311UE6 Binary w/Clear SynchronousUp/Down Dual ClockCounter74LSI93UF3 Differential Video Amplifier NE592NUF4 Differential Video Amplifier NE592NVI Crystal 16 MHz* Values not available

APPENDIXBFabrication ofVideo DetectorMaterials Required• One set of meter leads• One capacitor, O.OII'F, 50 V• One resistor, 1.0 kO, 10%, Y. W• One diode, IN4148 or equivalentEquipment and Supplies• Knife• Soldering ironPreparation1. Cut meter leads as shown in Fig. B-1:• Wire cutters• Needle-nose pliers• Heat shrink tubing, 'kinch• Heat shrink tubing, 0/,6 inch• Solder, 60/40 resin core• Scale (ruler)• Ohmmeter• String or two wire tiesNOTE:STRIP OFF INSULATION3/16" FROM BOTH SIDES OF CUT.1 3116"1rCUT HEREFig. B-1. Preparation, step 1.221

222 APPENDIX B2. Prepare diode as shown in Fig. B-2:3. Prepare resistor as shown in Fig. B-3:Fig. B·2. Preparation. step 2.4. Tin all leads on resistor, diode, and meter leads.AssemblyFig. B-3. Preparation, step 3.1. Slide 1 'I.-inch length of 'fa-inch heat shrink tubing onto red meter lead as shown in Fig. B-4.Do not shrink the tubing at this time.3" LENGTH OFRED METER LEADHEAT SHRINKABLETUBING (118-)Fig. B-4. Assembly, step 1.2. Solder diode, resistor, and remaining end of meter lead together as shown in Fig. B-5. Note properpolarity of diode.DIODEFig. B-5. Assembly, step 2.CATHODEMARKINGRESISTOR\ I~~~/HEREREMAINING END OFRED METER LEAD

Fabrication of Video Detector 2233. Slide heat shrink tubing over diode and resistor, leaving one lead of resistor exposed, and then shrinkthe tubing. See Fig. B-6.Fig. B-6. Assembly, step 3.4. Solder capacitor and black meter leads as shown in Fig. B-7. Tie meter leads where shown.- ~ - - /!'''' --)-1'1"":.-fl;TIE HEREFig. B-7. Assembly, step 4.SOLDERHERESOLDERHERE5. Slide a 2-inch length of 'k-inch heat shrink tubing over capacitor and then shrink the tubing. SeeFig. B-8.Fig. B-8. Assembly, step 5.

APPENDIXCMOS HandlingPrecautionsWhen handling the controller board or anyof the MaS ICs used in the VlC-1541,you must be aware of the possible damageto the MaS ICs from static discharge.A static charge of only several hundred volts isenough to cause permanent damage to a MaS IC.It is not uncommon for the human body to accumulatetens of thousands of volts of static charge.The following precautions will help to reduce damagecaused by static charges:• Avoid wearing synthetic material whenservicing the VIC-1541.• Do not service the VIC-1541 in a roomwith carpeting on the floor.• The use of conductive floor mats and wriststraps is advised (ifpossible).• Before handling the PC board, touch aground such as a shop ground or a coldwater pipe for 30 to 60 seconds in order todischarge any static charge in your body.Also touch any tools being used orantistatic devices (i.e., conductive foamrubber or conductive packaging tubes) tothe same ground.• Avoid touching the pins of the ICs as muchas possible.• After removing a MaS IC fortroubleshooting purposes, place the IC intoconductive foam until it is to be reinstalled.• When replacing MaS ICs, always groundconductive packaging to shop ground orcold water pipe before handling the IC.224

\APPENDIX 0Standard rcPin NumbersLocations of IC pin numbers are illustrated inFigs. 0-1 through 0-9 below. This numberingsystem is standard throughout the electronicsindustry and is not unique to the VIC-1541.8 7 6 5123456789Fig. 0-4. I8-pin dual in-line package.81 234Fig. 0-1. 8-pin dual in-line package.1413121110 9 82019 18 1716 15 14 13 12 11~::~~N;~::J1 2 3 4 5 6 7 8 9 10Fig. 0-5. 20-pln dual In-line package.G1234587Fig. 0-2. I4-pln dual in-line package.1615141312 1110 9[~~~~]1 234 567 8Fig. 0-3. I6-pin dual In-line package.lr24 232221 20 19 18 17 16 15 14 1324 PIN DIP1 2 3 4 5 6 7 8 9 10 1112Fig. 0-6. 24-pln dual In-line package.225

226 APPENDIX D. ~::::~~~~:::::I IOOO:~N~I~b032827262524 2322 21 201918 17 16 15 10 9 8 7 6 5 4 3 2 1loooo::~~ooooo1 2 3 4 5 6 7 8 g 10 1112 13 14Fig. 0-7. 28-pin dual in-line package.Fig. 0-9. lO-pln single In-line package.~~::::::::::~::::::::::I1 2 3 4 5 6 7 8 9 1011121314151617 18 19 20Fig. 0-8. 4O-pln dual in-line package.

APPENDIXEDescription of DiskController ICWhen Commodore upgraded the VIC­1541 from Model 1540 to Model 1541,they created a custom integrated circuit.This integrated circuit (UC1, Models 1541 and1542) reduces power consumption, heat, and productioncosts. The pin description of this integratedcircuit is illustrated in Fig. E-1.uci235572.Q,A block diagram of this disk controller integratedcircuit is shown in Fig. E-2.Internally, this integrated circuit contains essentiallythe same circuit that is used in the 1540.Table E-1 lists the parts that are integrated into thenew disk controller integrated circuit. For theory ofoperation of these parts, refer to the theory of operationfor Model 1541 (Chapter 7, Section 7.2).The encoder/decoder track select and read circuitsare affected by this integrated circuit.Table E·!.UCIBUC2UC3UD2UD3UE2UE3UE4AUE4BUE5AUESBUE5CParts Integrated into UC1UE5DUF2DUF3AUF3BUF3CUF4UF5AUF5BUF5CUF6AUF6BUG2CFig. E-l. Disk controller Integratedcircuit, pinouts.227

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