Systolic arrays for matrix multiplications

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Fault tolerance Fault tolerance has become an essentialdesign requirement in designing VLSI/WSIarray processors In systems involving large number of PEsand intensive computations it is highlylikely that some components arepermanently or temporarily faulty Such systems are systolic arrays
How fault tolerance can beachieved? Through some kind of redundancy: information,space and/or time redundancy or byreconfiguration We used space-time redundancy followed bymajority voting The purpose of our work was to synthesize SAwith optimal number of PEs for a given problemsize. Fault tolerance is achieved through triplicatedcomputation of the same problem instancefollowed by majority voting
Page 1 and 2: Systolic arrays formatrix multiplic
Page 3 and 4: Accelerators To provide the desired
Page 5 and 6: Systolic arraysSystolic Arrays-SA a
Page 7 and 8: ApplicationsDigital signal processi
Page 9 and 10: Basic SA topologies 2D SA
Page 11 and 12: Address generators Address generato
Page 13 and 14: Solution Since number of PEs (p) is
Page 15 and 16: The ordering of the input items at
Page 17 and 18: The ordering of the input items at
Page 19 and 20: Hardware structure of MIS_C
Page 21 and 22: Hardware structure of MIS_B
Page 23 and 24: FPGA implementation Implementations
Page 25: p = 20Area overhead (%)p = 25Area o
Page 29 and 30: Fault tolerant algorithm for SA A S
Page 31 and 32: BLSA with pipeline period λ=3
Page 33 and 34: Results In the case of both, BLSA a
Page 35 and 36: How we achieve this? Fault toleranc
Page 37 and 38: A detail concerning voting mechanis
Page 39 and 40: Which of the proposed solutions isb
Page 41 and 42: Simulation results for matrix dimen
Page 43 and 44: Conclusions Systolic arrays can be

Systolic arrays for matrix multiplications

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