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AS5215 Data Sheet - SE Spezial-Electronic Sp. z o.o

AS5215 Data Sheet - SE Spezial-Electronic Sp. z o.o

AS5215 Data Sheet - SE Spezial-Electronic Sp. z o.o

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<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Pin Assignments4 Pin AssignmentsFigure 2. Pin Assignments (Top View)132313029282726252422332245<strong>AS5215</strong>2120619718891011121314151716VSS_1VSS_2SINP_1 / SINN_1SINN_1 / SINP_1 / CM_SIN_1SINP_2 / SINN_2SINN_2 / SINP_2 / CM_SIN_2COSP_1 / COSN_1COSN_1 / COSP_1 / CM_COS_1CS_2CS_1DCLK_2DCLK_1VDD_2VDD_1NCNCDIO_1NCDIO_2NCTC_1NCTC_2A_TST_1NCNCA_TST_2NCPROG_1COSN_2 / COSP_2 / CM_COS_2PROG_2COSP_2 / COSN_24.1 Pin DescriptionsTable 1. Pin DescriptionsPin Name Pin Number DescriptionDIO_1 1DIO_2 2TC_1 3TC_2 4A_TST_1 5A_TST_2 6PROG_1 7PROG_2 8<strong>Data</strong> I/O for digital interfaceTest coilAnalog test pinOTP Programming Padwww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 3 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Pin AssignmentsTable 1. Pin DescriptionsPin Name Pin Number DescriptionVSS_1 9VSS_2 10Supply groundSINP_1 / SINN_1 11 Switchable buffered analog outputSINN_1 / SINP_1 / CM_SIN_1 12 Switchable buffered analog or common mode outputSINP_2 / SINN_2 13 Switchable buffered analog outputSINN_2 / SINP_2 / CM_SIN_2 14 Switchable buffered analog or common mode outputCOSP_1 / COSN_1 15 Switchable buffered analog outputCOSN_1 / COSP_1 / CM_COS_1 16 Switchable buffered analog or common mode outputCOSP_2 / COSN_2 17 Switchable buffered analog outputCOSN_2 / COSP_2 / CM_COS_2 18 Switchable buffered analog or common mode outputNC 19NC 20NC 21NC 22NC 23------NC 24NC 25NC 26VDD_1 27VDD_2 28Digital + analog supplyDCLK_1 29DCLK_2 30Clock input for digital interfaceCS_1 31CS_2 32Clock input for digital interfacewww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 4 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Absolute Maximum Ratings5 Absolute Maximum RatingsStresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation ofthe device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.Table 2. Absolute Maximum RatingsParameter Min Max Units CommentsSupply voltage (VDD) -0.3 7 VInput pin voltage (V_in) VSS - 0.5 7 VInput current (latchup immunity), I_scr -100 100 mA Norm: EIA/JESD78 Class II Level AElectrostatic discharge (ESD) ±2 kV Norm: JESD22-A114ETotal power dissipation (P tot ) 275 mWPackage thermal resistance (Θ_JA) 27 ºC/W Velocity =0; Multi Layer PCB; Jedec Standard TestboardStorage temperature (T_strg) -65 150 ºCPackage body temperature (T_body) 260 ºCNorm: IPC/JEDEC J-STD-020C.The reflow peak soldering temperature (body temperature)specified is in accordance with IPC/JEDEC J-STD-020C“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”.The lead finish for Pb-free leaded packages is matte tin(100% Sn).Humidity non-condensing 5 85 % MSL = 3www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 5 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Electrical Characteristics6 Electrical CharacteristicsUnless otherwise noted all in this specification defined tolerances of parameters are assured over the whole operation conditions range and alsoover lifetime.Table 3. Operating ConditionsSymbol Parameter Condition Min Typ Max UnitVDD Positive Supply Voltage 4.5 5.5 VVSS Negative Supply Voltage 0.0 0.0 VT_amb Ambient temperature -40 150 ºCTable 4. DC/AC Characteristics for Digital Inputs and OutputsSymbol Parameter Condition Min Typ Max UnitCMOS InputV_IHV_ILHigh level Input voltageLow level Input VoltageI_LEAK Input Leakage Current 1 µACMOS OutputV_OH High level Output voltage 4 mAV_OL Low level Output Voltage 4 mAVSS +0.4VC_L Capacitive Load 35 pFt_slew Slew Rate 30 nst_delay Time Rise Fall 15 nsCMOS Output TristateI_OZ Tristate Leakage Current 1 µATable 5. Magnetic Input <strong>Sp</strong>ecificationSymbol Parameter Condition Min Typ Max UnitTwo pole cylindrical magnet, diametrically magnetized:d MAG Diameter 4 6 mmB pp Magnetic input field amplitude 200 – 800 Gauss 20 50 80 mtf rot Rotational speed Max 30000 RPM 0 500 Hzdisp Displacement 250 µmTable 6. Electrical System <strong>Sp</strong>ecificationsSymbol Parameter Condition Min Typ Max Unitt power_on Power up time 200 500 700 µst prop Propagation delay -40 to 150ºC 18 22 30 µsM Magnetic Sensitivity 1G = 0.1 mT 3 4.5 6 mV/G0.7 *VDDVDD -0.5VDD -0.5VDD +0.5VDD +0.5VVVV outAnalog output rangeVss+0.25Vdd-0.5Vwww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 6 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Electrical CharacteristicsTable 6. Electrical System <strong>Sp</strong>ecificationsSymbol Parameter Condition Min Typ Max UnitSF=SF 25C- (AP1_1/AP2_1)Amplitude ratio tracking accuracyover temperature-40 to 150ºC -1 +1 %SF=AP1_1/AP2_1V offset1Amplitude ratio mismatch at roomtemperatureDC Offset6.1 Timing CharacteristicsRemark: The digital interface will be reset during the low phase of the CS signal.-2 2 %0.294 0.3 0.306 V / VDDRatiometric to VDDV offset2 DC Offset 0.49 0.5 0.51 V / VDDDC offdrift DC Offset Drift -40 to 150ºC -50 +50 µV/ºCTHD Total Harmonic Distortion 0.2 %SR Slew Rate 1 V/µsCLOAD Capacitive Load 1000 pFTable 7. Timing CharacteristicsSymbol Parameter Condition Min Typ Max Unitt1_3 chip select to positive edge of DCLK 30 - nst2_3 chip select to drive bus externally 0 - nst3t4t5t6t7t8t9_3t10_3t11t12t13_3setup time command bitdata valid to positive edge of DCLKhold time command bitdata valid after positive edge of DCLKfloat timepositive edge of DCLK for last command bit to bus floatbus driving timepositive edge of DCLK for last command bit to bus drivedata valid timepositive edge of DCLK to bus validhold time data bitdata valid after positive edge of DCLKhold time chip selectpositive edge DCLK to negative edge of chip selectbus floating timenegative edge of chip select to float bussetup time data bit @ write accessdata valid to positive edge of DCLKhold time data bit @ write accessdata valid after positive edge of DCLKbus floating timenegative edge of chip select to float bus30 - ns15 - ns-DCLK/2+0DCLK/2+0DCLK/2+0DCLK/2+0DCLK/2+0ns- nsDCLK/2+30ns- ns- ns- 30 ns30 - ns15 - ns- 30 nswww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 7 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Detailed DescriptionFigure 4. 3D-Graph of Vertical Magnetic Field of a 6mm Cylindrical MagnetBZ; 6mm magnet @ Z=1mmarea of X- Y-misalignment from center:±0.5mmcircle of Hall elements on chipBz [mT]Y -displacement [mm]X -displacement [mm]As shown in Figure 5 (grey zone), the Hall elements are located on the chip at a circle with a radius of 1.1mm. Since the difference between twoopposite Hall sensors is measured, there will be no difference in signal amplitude when the magnet is perfectly centered or if the magnet ismisaligned in any direction as long as all Hall elements stay within the linear range.www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 9 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Detailed DescriptionFor the 6mm magnet (shown in Figure 5), the linear range has a radius of 1.6mm, hence this magnet allows a radial misalignment of 0.5mm(1.6mm linear range radius; 1.1mm Hall array radius). Consequently, the larger the linear range, the more radial misalignment can be tolerated.By contrast, the slope of the linear range decreases with increasing magnet diameter, as the poles are further apart. A smaller slope results in asmaller differential signal, which means that the magnet must be moved closer to the IC (smaller airgap) or the amplification gain must beincreased, which leads to a poorer signal – to – noise ratio. More noise results in more jitter at the angle output. A good compromise is a magnetdiameter in the range of 5…8mm.Small Diameter Magnet (6mm)+++ wider linear range =larger horizontal misalignment area-- weaker differential signal =poorer signal / noise ratio,smaller airgapsFigure 5. Vertical Magnetic Field across the center of a Cylindrical MagnetBz; 6mm magnet @ y=0; z=1mmBz [mT]Hall elements (side view)X -displacement [mm]www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 10 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Detailed DescriptionFigure 9. Magnetic Field Lines in Plastic or Copper ShaftIf the magnet is mounted in non-magnetic material, such as plastic or diamagnetic material, such as copper, the magnetic field distribution is notdisturbed. Even paramagnetic material, such as aluminium may be used. The magnet may be mounted directly in the shaft (see Figure 9).Note:Stainless steel may also be used, but some grades are magnetic. Therefore, steel with magnetic grades should be avoided.Figure 10. Magnetic Field Lines in Iron ShaftIf the magnet is mounted in a ferromagnetic material, such as iron, most of the field lines are attracted by the iron and flow inside the metal shaft(see Figure 10). The magnet is weakened substantially.This configuration should be avoided!www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 13 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Detailed DescriptionFigure 11. Magnetic Field Lines with <strong>Sp</strong>acer between Magnet and Iron ShaftIf the magnet has to be mounted inside a magnetic shaft, a possible solution is to place a non-magnetic spacer between shaft and magnet, asshown in Figure 11. While the magnetic field is rather distorted towards the shaft, there are still adequate field lines available towards the sensorIC. The distortion remains reasonably low.7.1.6 Summary• Small diameter magnets (6 mm Ø) have a wider linear range and allow a wider lateral misalignment. The flatter slope requires shorter axialdistances.• The linear range decreases with airgap; Best performance is achieved at shorter airgaps.• The ideal vertical distance range can be determined by using magnetic range indicators provided by the encoder ICs. These indicators arenamed MagInc, MagDec, MagRngn, or similar, depending on product.www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 14 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Application Information8 Application Information8.1 Sleep ModeThe target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode.Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powereddown with respect to fast wake up time.8.2 SSI InterfaceThe setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. Thesynchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface isdone in a way that the digital clock frequency can vary in a wide range.Table 8. SSI Interface Pin DescriptionPort Symbol Functionchip selectCSindicates the start of a new access cycle to the deviceCS = LO → reset of the digital interfaceDCLK DCLK clock source for the communication over the digital interfacebidirectional data input outputDIOcommand and data information over one single linethe first bit of the command defines a read or write accessTable 9. SSI Interface Parameter DescriptionSymbol Parameter Notes Min Typ Max Unitf_DCLKf_EZ_RWf_EZ_PROGf_EZ_ARBclock frequency@ normal operationclock frequency@ easy zap read write accessclock frequency@ easy zap access program OTPclock frequency@ easy zap analog readbackInterface General @ normal modeprotocol: 5 command bit + 16 data input outputcommanddataInterface General @ extended modeprotocol: 5 command bit + 33 data input outputcommanddataInterface Modesnormal read operation modeextended read operation modenormal write operation modeextended write operation modeThe nominal value for the clock frequency canbe derived from a 10MHz oscillator source.Correct access to the programmable zenerdiode block needs a strict timing – the zap pulseis exact one period.The nominal value for the clock frequency canbe derived from a 10MHz oscillator source.20 pF external load allowed.The nominal value for the clock frequency canbe derived from a 10MHz oscillator source.5 bit command: cmd ← bit16 bit data: data ← bit5 bit command: cmd ← bit34 bit data: data ← bitcmd = → 1 DCLK per data bitcmd = → 4 DCLK per data bitcmd = → 1 DCLK per data bitcmd = → 4 DCLK per data bitno limit 5 6 MHzno limit 5 6 kHz200 - 650 kHzno limit 156,3 162,5 kHzwww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 15 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Application Information8.3 Device Communication / ProgrammingTable 10. Digital Interface @ normal mode# command bin mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 023WRITE CONFIG110111 write go2sleep gen_rst analog_sig OB_bypassed16 EN_PROG 10000 write 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0Namego2sleepgen_rstanalog_sigOB_bypassedFunctionalityEnter/leave low power mode (no output signals)Generates global resetSwitches the channels to the test bus after the PGADisable and bypass output buffer for testing purposeTable 11. Digital Interface @ extended mode# command bin modeFactory SettingsUser Settings 31 WRITE OTP 11111 xt write otp test ID 10µbiastrim vref osclock_OTPn.c.invert_channelcm_sin cm_cos gaindc_offsethall_bias25 PROG_OTP 11001 xt write otp test ID 10µbiastrim vref osclock_OTPn.c.invert_channelcm_sin cm_cos gaindc_offsethall_bias15 RD_OTP 01111 xt readotp testID 10µbiastrim vref osclock_OTPn.c.invert_channelcm_sin cm_cos gaindc_offsethall_bias9 RD_OTP_ANA 01001 xt readRemark:1. Send EN PROG (command 16) in normal mode before accessing the OTP in extended mode.2. OTP assignment will be defined/updated.NameOtp_testIDnc.10µbiastrimvrefosclock_OTPinvert_channelcm_sincm_cosgaindc_offsetHall_bDummy fuse bit used in production testPart identificationNot connected10µ bias current trim bitsBias Block reference voltage trim bitsOscillator trimming bitsFunctionalityTo disable the programming of the factory bits Inverts SIN and COS channel before the PGA for inverted output function (0...SIN/COS, 1...SINN/COSN)Common mode voltage output enabled at SINN / CM pin (0...differential, 1...common)Common mode voltage output enabled at COSN / CM pin (0...differential, 1...common)PGA gain setting (influences overall magnetic sensitivity), 2bitOutput DC offset (0…1.5V, 1…2.5V)Hall bias setting (influences overall magnetic sensitivity), 6bitwww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 16 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Application InformationFigure 12. Sensitivity Gain Settings - Relative Sensitivity in %Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting600550Relative Sensitivity in %5004504003503002502001501000 10 20 30 40 50 60Hall Current OTP setting (6 bits)M_PGA_00M_PGA_01M_PGA_10M_PGA_11The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) settings (see Figure 12).Figure 13. Sensitivity Gain Settings - Sensitivity [mV/mT]Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting0.70.6Sensitivity [mV/mT]0.50.40.30.2M_PGA_00M_PGA_01M_PGA_10M_PGA_110.100 10 20 30 40 50 60Hall Current OTP setting (6 bits)www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 17 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Application Information8.8 Analog Sin/Cos Outputs with External InterpolatorFigure 17. Sine and Cosine Outputs for External Angle Calculation+5VVDD100kVDDDAVDD PROGSINP_1/SINN_1SINN_1/SINP_1/CM_SIN_1MicroControllerDDAASINP_2 / SINN_2SINN_2/SINP_2/CM_SIN_2 AS5130COSP_1/COSN_1COSN_1/COSP_1/CM_COS_1<strong>AS5215</strong>100nVSSDACOSP_2/COSN_2COSN_2/COSP_2/CM_COS_2VSSVSSNotes:1. We recommend to use a 100k pull-up resistance.2. Default conditions for unused pins are: DCLK_1/2, CS_1/2, DIO_1/2, TC_1/2, A_TST_1/2, TBO_1/2, TB1_1/2, TB2_1/2,TB3_1/2 connect to VSSThe <strong>AS5215</strong> provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the userto perform the angle calculation by an external ADC + µC, e.g. to compute the angle with a high resolution. The output driver capability is 1mA.The signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance.Through the programming of one bit, you have the possibility to choose between the analog Sine and Cosine outputs (SINP, COSP) and theirinverted signals (SINN, COSN). Furthermore, by programming the bits you can enable the common mode output signals of SIN andCOS.The DC bias voltage is 1.5 or 2.5 V.www.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 20 - 24


<strong>AS5215</strong><strong>Data</strong> <strong>Sheet</strong> - Ordering Information10 Ordering InformationThe devices are available as the standard products shown in Table 14.Table 14. Ordering InformationOrdering Code Description Delivery Form Package<strong>AS5215</strong>-HQFT Sine and cosine analog output magnetic rotary encoder Tape & Reel 32-pin QFN (7x7mm)Note:All products are RoHS compliant and Pb-free.Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirectFor further information and requests, please contact us mailto:sales@austriamicrosystems.comor find your local distributor at http://www.austriamicrosystems.com/distributorCopyrightsCopyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent ofthe copyright owner.All products and companies mentioned are trademarks or registered trademarks of their respective companies.DisclaimerDevices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regardingthe freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices atany time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG forcurrent information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment arespecifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall notbe liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out ofaustriamicrosystems AG rendering of technical or other services.Contact InformationHeadquartersaustriamicrosystems AGTobelbaderstrasse 30A-8141 Unterpremstaetten, AustriaTel: +43 (0) 3136 500 0Fax: +43 (0) 3136 525 01For Sales Offices, Distributors and Representatives, please visit:http://www.austriamicrosystems.com/contactwww.austriamicrosystems.com/<strong>AS5215</strong> Revision 1.5 24 - 24

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