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CONTENTSJuly August 2013Volume 17, Number 4Chip Scale Review July - August 2013 Volume 17, Number 4 ChipScaleReview.comVolume 17, Number 4 July- August 2013Real-Time Dispatching forSemiconductor Package AssemblyP. 31• Thin-Wafer Handling• Integrating Diamond• Alpha Radiation Dynamics• Cu-Cu Direct Bonding for CTC Interconnect• 2.5D Interposers; Organics vs. Silicon vs. Glass• Packaging Solutions for Power Electronics• Wafer-Level Packaging for 3D Heterogeneous IntegrationThis photo demonstrates the wire bondingoperation in the chip assembly manufacturingprocess. The machine attaches lead wires tothe chip. It is commonly a constrainingstep in the assembly manufacturing process.Technologies such as Applied Materials'dispatching software determine whatchips are best to process next in real time.This has proven to increase throughput atmanufacturing bottleneck steps like wirebonding. Photo courtesy of Applied Materials.The International Magazine for Device and Wafer-level Test, Assembly, and PackagingAddressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS,MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.FEATURE ARTICLES2.5D Interposers; Organics vs. Silicon vs. GlassProf. Rao R. Tummala, 3D Systems Packaging Research Center, GeorgiaInstitute of TechnologyCu-Cu Direct Bonding for Ultra-high DensityChip-to-Chip InterconnectsEric Bersch, Chris Kim, Klaus Hummler, Brian Sapp, SEMATECHIntegrating Diamond to Maximize Chip Reliability and PerformanceRichard S. Balmer, Bruce Bolliger, Element SixReal-Time Dispatching for Semiconductor Package AssemblyShekar Krishnaswamy, David Hanny, Applied MaterialsAlpha Radiation Dynamics in Electronics Packaging StructuresBrett M. Clark, Derek Grove, Tora Unuvar, Honeywell Electronic MaterialsPRESENTING THEEVOLUTION OF THEFLIP CHIP BUMP1820263134From the diverse solder bumpingsolutions of the last decade to thelarge scale production of today’sfine pitch copper pillar bumps,Amkor will provide a solution foryour packaging challenges.Amkor remains at the forefrontof semiconductor packagingdevelopment and performance.ELIMINATE THE GUESSWORKand talk to us today about our extensiveoffering of next generation design,assembly, and test solutions.visit amkor technology online for locations andto view the most current product information.www.amkor.comChip Scale Review July/August 2013 [ChipScaleReview.com]1

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CONTENTSFEATURE ARTICLESAdvanced Wafer-Level Packaging Technology for 3D Heterogeneous IntegrationSeung Wook Yoon, Patrick Tang, Steve Anderson, Raj Pendse, STATS ChipPAC, Inc.Adapting an OmPP TM QFN for GaN Power DevicesBill Lawrence, Steve Swendrowski, Quik-Pak, Greg Klowak, GaN Systems, Andy Longford, PandA EuropeTaking Copper Wire into High-Volume ManufacturingUsman Chaudhry, Willmar Subido, Texas InstrumentsCost & Performance for Packaging at 28nm & BeyondBob Chylak, Ivy Qin, Patrick Desjardins, Horst Clauberg , Kulicke and Soffa Ind., Inc.Latest Insights in Thin Wafer Handling TechnologiesMargarete Zoberbier, Stefan Lutter, SUSS MicroTecDEPARTMENTSFrom the Publisher Planning for Success!Kim Newman, Chip Scale ReviewFrom the Boardroom Editorial Advisory Board UpdateDr. Andy Mackie3D Market Trends Interconnectology: A System-Level Approach to Semiconductor Device ManufacturingFrançoise von Trapp, 3D InCitesMEMS Market Trends: Automotive MEMS Packaging Enables Sensor FusionRussell Shumway, Adrian Arcedera, Amkor TechnologyPatents: First Inventor To File: The Race Is On!Jason Mirabito, Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C.Industry NewsChip Scale Review StaffProduct NewsChip Scale Review StaffAdvertiser Index, Advertising Sales384346505468101316586872Shrink. STAck. inTeGrATe.DiMenSionS in ScALe+SUSS MicroTec is a leading supplier ofequipment and process solutions formicrostructuring applications with morethan sixty years of engineering experience.Our portfolio covers a wide range of R & Dand high-volume production equipmentalong with excellent process and maintenancesupport to partner with you at anystage of your device development andmanufacturing cycle.Sign-up for theSUSS Technology Forum 2013at Semicon Westor visit our booth # 1707, South Hall+ Photomask equipment+ coating/Developing+ Mask Aligner + Projection Lithography+ Laser Processing+ nanoimprint Lithography+ Wafer BondingSÜSS MicroTec AG | Phone: +49 89 32007-0 | info@suss.com | www.SUSS.comChip Scale Review July/August 2013 [ChipScaleReview.com]5

Volume 17, Number 4The International Magazine for Device and Wafer-levelTest, Assembly, and Packaging AddressingHigh-density Interconnection of Microelectronic IC'sincluding 3D packages, MEMS, MOEMS,RF/Wireless, Optoelectronic and OtherWafer-fabricated Devices for the 21st Century.STAFFKim Newman Publisherknewman@chipscalereview.comLawrence Michaels Managing Directorlxm@chipscalereview.comDebra Vogler Senior Technical Editordvogler@chipscalereview.comDr. Thomas Di Stefano Contributing Editortom@centipedesystems.comJason Mirabito Contributing Legal Editormirabito@mintz.comPaul M. Sakamoto Contributing Editor Testpaul.sakamoto@comcast.netSandra Winkler Contributing Editorslwinkler@newventureresearch.comEDITORIAL ADVISORSDr. Andy Mackie (Chair) Indium CorporationRolf Aschenbrenner Fraunhofer InstituteDr. Thomas Di Stefano Centipede SystemsJoseph Fjelstad Verdant ElectronicsDr. Arun Gowda GE Global ResearchDr. John Lau Industrial Tech Research Institute (ITRI)Nick Leonardi Premier Semiconductor ServicesDr. Alan Rae Alfred Technology ResourcesDr. Ephraim Suhir ERS CompanyDr. Venky Sundaram Georgia Institute of Technology-3D Systems Packaging Research CenterFred Taber BiTS WorkshopFrancoise von Trapp 3D InCitesDr. C.P. Wong Georgia Institute of TechnologySUBSCRIPTION--INQUIRIESChip Scale ReviewT 408-429-8585F 408-429-8605subs@chipscalereview.comAdvertising Production Inquiries:Kim Newmanknewman@chipscalereview.comCopyright © 2013 Haley Publishing Inc.Chip Scale Review (ISSN 1526-1344) is a registered trademark ofHaley Publishing Inc. All rights reserved.Subscriptions in the U.S. are available without charge to qualifiedindividuals in the electronics industry. Subscriptions outside of theU.S. (6 issues) by airmail are $100 per year to Canada or $115 peryear to other countries. In the U.S. subscriptions by first class mailare $95 per year.Chip Scale Review, (ISSN 1526-1344), is published six times ayear with issues in January-February, March-April, May-June, July-August, September-October and November-December. Periodicalpostage paid at Los Angeles, Calif., and additional offices.POSTMASTER: Send address changes to Chip Scale Reviewmagazine, P.O. Box 9522, San Jose, CA 95157-0522Printed in the United StatesFROM THE PUBLISHERThere comes a point in time when proper planning begins to pay offwith forward momentum, which seems to push you to the next level ofsuccess. Over the course of several years, as publisher of Chip ScaleReview, I have been involved in the planning of every stage of thebusiness; from page layout to printing and web site development, from staffing toadvisory boards, from technical editorial content to corporate advertising, and fromindustry events to organizational relationships.Annual planning is typical for most companies. The CSR Editorial Calendaris revised annually and defines the upcoming editorial features scheduled for thepublication. Take a moment to review the Editorial Calendar posted on our websiteto determine which topics are most important to your business. Identifying keytopics for 2014 is already well underway. In this issue, our Editorial Advisory Boardchairperson, Dr. Andy Mackie of Indium Corporation, describes the charter of theBoard and some of the challenges of reporting the technologies that support theproliferation of new IC packages to meet the needs of both readers and advertisers.Contributed editorial from Element Six on incorporating CVD diamond in ICpackages for better thermal management and improved chip reliability, Honeywellon alpha-particle radiation concerns driven by shrinking device and packagegeometries, SUSS MicroTec on handling of thin wafers for wafer-to-wafer bonding,and Applied Materials on a software solution for real-time dispatching in IC packageassembly, cover a broad range of interesting topics. Specifically related to “3D” and“copper” are contributions from STATS ChipPAC on wafer-level packaging for 3Dintegration, Georgia Tech on 2.5D interposer material choices, both K&S and TexasInstruments on the adoption of copper wire bonding, and SEMATECH on copperto-copperdirect bonding without solder.When planning your advertising, pay attention to the show schedule column onour Editorial Calendar. CSR distributes the publication to the attendees of a numberof worldwide events throughout the year reaching readers beyond our subscriber list.For example, Chip Scale Review was again pleased to be the Official Media Sponsorfor ECTC 2013, the premier IEEE/CPMT technical conference and exhibition oncomponent-level packaging and assembly. Ron Molnar of AZ Tech Direct, and CSRstaff member, captures the highlights from this year’s event in this issue.Take the opportunity to contact a member of the CSR Staff or our EditorialAdvisory Board during one of the industry events, such as SEMICON West in July,or IWLPC in November, to share your industry perspectives and recommendationsfor our publication. I encourage our global industry colleagues and devoted readersto take full advantage of the planning efforts by our CSR Staff and Advisory Boardmembers to promote your companies through regular editorial contributions andadvertising as you plan for success!Kim NewmanPublisherPlanning for Success!6Chip Scale Review July/August 2013 [ChipScaleReview.com]

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FROM THE BOARDROOMEditorial Advisory Board UpdateBy Dr. Andy MackieWelcome to the SEMICONWest edition of ChipScale Review! Aschairperson of the Editorial AdvisoryBoard, I have been asked by publisher,Kim Newman, to write a few wordsabout the board: who we are, what wedo, and why we do it.The “why” part is probably easiestto explain; each board member isa technical or market expert in oneor more fields related to post-FEOLsemiconductor processes, and each ofus has a passion to share our knowledgeand experience with others.The board is tasked with guiding,and sometimes creating, the magazine’scontent. Our main goal is to keep themagazine relevant and interestingto a growing global audience ofengineers, materials scientists, andtechnical decision makers in the fieldof “semiconductor packaging.” It isno surprise that in reality, this termcovers a broad and expanding spectrumof activities. The board is made upof consultants, market experts, andtechnology luminaries around the world.For those of you who are newto semiconductor packaging (akasemiconductor assembly) ‐ in itsbroadest sense, it is all about protectinga semiconductor device (the ubiquitous“chip”) and allowing it to reliablycommunicate to the outside world fora well-characterized period of time.Twenty-five years ago, electronicspackaging referred to just die-attach.This was done mostly with wirebonding and a little flip-chip, followedby final encapsulation in a metal lid ora polymeric material of some kind. Italso included the testing and reliabilitythat go with ensuring device utilityand longevity.The essence of these processes stillremains, but the evolution of the fieldof semiconductors as a whole has meantthat CSR magazine now has to reach anaudience involved in the manufactureand testing of a huge array of deviceand package forms, from the tiniesttransient voltage suppressor (TVS) orsurface-mount zener diode (many ofwhich will fit on the head of a match),through discrete power devices and clipbondeddie in QFN format and insulatedgate bipolar transistor (IGBT) modulesthe size of a shoebox and operatingat 1700V. Although I left electricaland thermal considerations out of thisdescription, a thorough understandingof the materials and processes usedin semiconductor packaging isincreasingly important, even to thoseengineers involved in device modeling.The board meets bimonthly viaconference call, and we will have atleast one major face-to-face meetingthis year at SEMICON West. WeAnd the Winner Is...directly contribute written material toChip Scale Review, and we also seekout and encourage others to write fulllengthfeature articles or columnsfor publication. These articles mayappear in either hard copy or online atwww.chipscalereview.com.Although we try to avoid any biastowards one process, company, or topic,you can help us balance our content bycontacting one of the board members, orDebra Vogler (Senior Technical Editor),to contribute articles. We encourageauthors to discuss topics at the cuttingedge of chip-scale technology andpackaging, such as implantable medicaldevices and the seemingly-inevitableinterfacing of machine and man, whileremaining firmly rooted in the questionof “how are scientists and engineersgoing to make this work?”Starting with this issue, each boardmember will be asked to contributean editorial (as chairperson, I get firstdibs on this), and we hope that you willcontinue to find the magazine worthy ofyour time to read and for which to write.Cheers!AndyI would like to take this opportunity to congratulate members of theCSR Editorial Advisory Board for recognition by the IEEE - Components,Packaging and Manufacturing Technology Society (CPMT). Amongthe recipients are John Lau received the 2013 IEEE "Field Award"Components, Packaging and Manufacturing Technology Award and RolfAschenbrenner received the "David Feldman Outstanding ContributionAward." Both were recognized and presented with these awards at theCPMT Society luncheon by the Executive Committee at the 63rd ECTC.8Chip Scale Review July/August 2013 [ChipScaleReview.com]

educe soft errorsDeliver more density on your IC packages withoutsoft errors.Honeywell RadLo low alpha packaging materials help eliminate softerrors and single event upsets by reducing alpha emissions, a significantsource of these problems. This is becoming increasingly importantas chip dimensions and designs continue to miniaturize. Our leadershipand expertise in low alpha refining and metrology mean that Honeywell can help you meet criticalalpha emission levels.Honeywell reliability. Reliable low alpha. Make sure to ask your suppliers if they are usingHoneywell RadLo low alpha materials for their chip packaging processes.Find out more by visiting us at www.honeywell-radlo.comAlthough all statements and information contained herein are believed to be accurate and reliable, they are presented without guarantee or warranty of any kind, express or implied. Information provided herein does not relievethe user from the responsibility of carrying out its own tests and experiments, and the user assumes all risks and liability for use of the information and results obtained. Statements or suggestions concerning the use of materialsand processes are made without representation or warranty that any such use is free of patent infringement and are not recommendations to infringe any patent. The user should not assume that all toxicity data and safetyChip Scale Review July/August 2013 [ChipScaleReview.com]measures are indicated herein or that other measures may not be required. ©2012 Honeywell International Inc. All rights reserved.9

IBM first developed the PC architecture,it controlled the form factor for circuitryand devices, explains Feldman. “Nowthat we’re in a post-PC era, wherepeople are differentiating processes,we need different ICs and differentinterconnects to be part of the solutionto hit their value proposition,” he said.The real shift, notes Feldman,comes down to who is making thetechnology decisions. Designers nolonger have to settle for what packageis available. Interconnectology involvesthinking across the whole product,and the product designer will definesuch requirements, for example,putting six die of a certain size thatconsume a given amount of power. Aninterconnectologist has the skill set toput this all together.Does Interconnectology ReplacePackaging?“Traditional packaging steps stillremain,” says Jewler, “but there’s anew area emerging that is the valueaddand involves finer geometriesthat are integral to the functionalityof the device.” He says it reallygoes beyond nomenclature, and willgreatly impact the next five to tenyears in the semiconductor industry.Interconnectolgy creates opportunity forcompanies to integrate multiple IP andmultiple process technologies to createmore competitive products.Because packaging is fragmented,it’s the right space for grabbingdifferentiation, notes Arkalgud, butit can’t be done just by developingthe next clever package. “It has to bea holistic approach that says ‘here’swhat I’m offering from an interconnectperspective, and here’s how it interactsup and down the value chain. Thenyou have a shot at clearing a space foryourself,” he says.All This, From One New Word?“Interconnectology is a powerfulterm,” says Chris Scanlan, VPof Product Development, DecaTechnologies. “Interconnectologistshave to understand the electrical,thermal, and thermo-mechanicalissues—essentially all the constraintsthat go into designing a productinvolving electronic interconnect.Its more powerful than ‘advancedpackaging’ technologist.”But beyond the nomenclature, it’sthe opportunity that comes with theconcept. Coining a new term or termshelps to define what’s happening in theindustry. “You can’t just do thermal ortest engineering,” notes Feldman. “It allneeds to be interconnected across all thedisciplines and areas. We have to figureout how to put pieces from multiple placesin the supply chain together in ways thatdeliver against product requirements andthe value that’s needed.”Jeweler says he’s concerned thatfew young engineers are entering thepackaging space. “As an integral partof More than Moore, interconnect andinterconnectology needs smart youngcreative people to drive these solutions,”he says. “Improving the name makesrecruiting new college graduates moresuccessful.”Another area in whichinterconnectology can prove to beuseful is in driving roadmaps on whatthis needs to be, says Arkalgud, whichallows us to be more efficient anddeliver cost-saving solutions fast.According to Larry Furman, ofPlastronics, the most successfulrelationship his company, whichmanufactures test sockets for theadvanced packaging sector, has had iswhen there’s a strong co-relation withthe packaging engineers. He says thatuntil advanced packaging engineerscommunicate with back-end test inadvance to give them time to developthe infrastructure, products will get heldup. “When we’re looking at the backendinfrastructure up front, that’s whenwe can cut lead-times and deliverablesto end-users.” He further noted thatimplementing interconnectology acrossthe supply chain provides this systemlevelapproach to the ecosystem thateveryone is calling for, but don’t knowwhat to call it.The Poster Child for Interconnectology2.5D and 3D ICs represent theposter child for implementinginterconnectology. Simon McElrea,CEO, Invensas, says manufacturing2.5D and 3D devices requires moreknowledge than putting vias intosilicon and plating them. While the corecompetency to do this comes from thewafer processing industry, that’s only apiece of it. It doesn’t mean you’ll endup with a working product. There needsto be an understanding of how to put itall together, considering reliability andthermal issues at the same time. “Thejob for interconnectologists beginswith the TSV right up to the physicalconnector/module level,” says McElrea.“It’s more than just packaging. Itrequires sufficient wafer-level skillsoverlapping with packaging skills.”SummaryIn reality, it’s the lessons learned in thismarch toward 3D IC integration that hasbrought the most awareness to a systemlevelapproach across the ecosystem.Just think how much further we might bealong in commercialization of 3D ICs ifinterconnectology had been implementedfrom the beginning? Perhaps adoptingit as a manufacturing approach for thenext-generation of technologies – siliconphotonics, for example – we can help toimprove time-to-market and implementcost savings much earlier in the game.BiographyFrançoise von Trapp, Queen of 3D,writes about emerging 3D integrationtechnologies on 3D InCites, the onlinecontent source for 3D IC integrationand 3D packaging technologies. vonTrapp also contributes content andcommunications strategy development forImpress Labs clients in the SemiconductorLab. She serves on the editorial advisoryboard for Chip Scale Review.12Chip Scale Review July/August 2013 [ChipScaleReview.com]

MEMS MARKET TRENDSAutomotive MEMS Packaging EnablesSensor FusionBy Russell Shumway, Adrian Arcedera [Amkor Technology]MEMS sensors wereinitially adopted intothe commercial marketby way of automobiles. Mandated fuelefficiency laws first introduced manifoldand barometric pressure sensors. Thiswas followed by driver safety measuresadding accelerometers for crashdetection, and gyro sensors were lateradded for electronic stability control androll over detection. Applications havecontinued to evolve through furtherimplementations or combinations ofthese key sensor types. Newly addedsensors also address fuel efficiencies,driver and occupant safety, and morerecently, driver assistance in passive andactive sensor systems.Automotive pressure sensorpackages have always had the uniquerequirements of protecting the internaldevice and interconnect within a cavity,while also allowing external pressureto be measured through port holes intothe package. Protection of the internalcomponents can be difficult in harshautomotive mounting environmentswhere heat, moisture, and corrosivechemicals are present and can enterthrough the ports. The evolution of thededicated pressure packages has takenon many forms, from through-holelead frame dual inline packages (DIPs)to gull-wing leads on small outlineICs (SOICs) that are surface-mountsoldered, welded within modules, or actas connector push fit pins. True packagestandardization for this particular typeof sensor in the automotive space hasremained a challenge.The earliest examples of automotiveaccelerometer sensors requiredpackage-level hermetic sealing inceramic cavities to provide a low stressenvironment, control of transducerdamping rate often under vacuum,and protection from foreign particlecontamination that could physicallyhinder mechanical function of theexposed transducer elements. Theearliest packaging solutions ofautomotive inertial sensors were highgrade and more costly solutions thanused for common ICs. This was duein part to a developmental origin inaerospace, military or government,as well as the unique attributes andrequirements inherent to inertial MEMS.The advancement of cavity waferbonding technology over MEMStransducers was a major step forwardthat later allowed transducer protectionat the wafer level. This removed thesealing requirement from the packagedesign and allowed more common overmoldedsurface mountable packaging,such as SOICs, to quickly become acompatible and popular platform. Thesensors could then share in the highvolumemanufacturing efficienciesand maturity of standard IC packages.The gyrometer sensors that enteredautomotive applications following thisinnovation benefitted by being cappedand having compatibility with standard,but often lower stress, over-moldpackage options.The compatibility of MEMSwith standard IC packages was alsomade possible by intelligent designadvancements of the transducerelements themselves. Many MEMS diedesigns have become more tolerableto direct surface exposure of nonlinearthermo-mechanical stress couplingpresent in over molded IC packages.Devices with high accuracy needs,or particular sensitivities to moldingcompounds, have generally benefittedfrom low stress cavity options of a givenpackage type formed in the commonplatforms described above.Sensor Fusion in Today’sAutomobilesSensor fusion is a combination ofmultiple sensors working together toprovide greater performance or benefitthan the sum of the individual sensordevices. It is a system approach thatincludes both hardware and softwarepartitioning. A key benefit is theopportunity for error cancellationand output correction by analyzingmultiple sensor outputs of the samemeasured event. There is also decreasedsoftware complexity and reducedpower consumption for computationaldata processing [1]. One example ofautomotive sensor fusion being promotedis the advanced driver assistance system(ADAS). The ADAS system shownin Figure 1 enhances automobileintelligence through a combination ofultrasonic and radar sensors. The systemprovides awareness of objects smallor large around the entire perimeter ofa vehicle and increases safety throughpassive or active collision avoidancesoftware functions linked to the sensorydetection. The actual driver assistancefunctions and partitions will vary amongOEM manufacturers and vehicle models.There are examples in the marketof applying optical CCD camera, IR,or inertial-based fusion systems thatChip Scale Review July/August 2013 [ChipScaleReview.com]13

40 + years ofAnd now, the perfect nameTMQi • nex [kuh-nekts] 1. Over 40 years ofreliable burn-in and custom connections;2. Quality interconnects for nex-gen solutions.Introducing Qinex, thenew brand name forsuperior interconnectionsolutions from SensataTechnologies. Qinex, thenew word in perfectpitch.QUALITY. High-value interconnectionsolutions since 1970.• 24/7 global engineering• 24/7 global support teams• Local engineering and sales• Six Sigma quality management• Proven, reliable high-volumemanufacturing• Expert molding, design, andcustomizationINNOVATION. More I/O choices,smaller form factors, superiorperformance in less time.• Latest 3D design tools• On-site model shops• Rapid prototyping• Advanced thermal analysis• Design on demand• Broad range of innovativecontact designsPARTNERSHIP. In a fierce globalmarket, only Qinex reliably supportsthe innovation, reputation andcompetitiveness of your business.We’ll work with you to get it right,the first time.40+ years of perfect pitch.And now, the perfect name.WEB www.qinex.comEMAIL qinex@sensata.comCALL 1-508-236-1306Chip Scale Review July/August 2013 [ChipScaleReview.com]15

PATENTSFirst Inventor To File: The Race Is On!By Jason Mirabito [Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C.]In my last article in theNovember/December 2012issue of Chip Scale Review, Ifocused on largely post-grant proceduresavailable since the passage of the“America Invents Act,” known as theAIA. However, another set of changesbecame effective recently (March 16,2013) and made dramatic changes forthe U.S. Patent System even though, inactuality, the rest of the world had beenoperating on this system for many years.This change is a movement from a firstto invent (FTI) to a first inventor to file(FTF) system and affects all originalpatent applications filed after March 16,2013, and thus any original applicationfiled by the time readers perusethis article.Under the prior law, a second applicantfor patent who filed an application forthe same invention after a first applicantfiled might be entitled to the patent ifthe second applicant could prove thathe or she was the first inventor throughthe process of a somewhat complex,expensive proceeding known as aninterference. In such a proceeding, therespective applicant would be requiredto prove first person to conceive withadditional probing of reduction topractice of the invention as well as socalleddue diligence from the timeof invention to the time of filing or areduction to practice. These interferenceproceedings were battles fought withinthe U.S. Patent Office and have largelybeen eliminated with the new law, exceptas described below.Now, that is, for original applicationsfiled after March 16, 2013, the U.S. hasmoved to an FTF system. Under thissystem, there’s no need to prove the dateof invention. The interference procedureis replaced, in part, with a so-calledderivation procedure. The sole questionnow is who was the earliest filer atthe U.S. Patent and Trademark Office.Certainly, this is a simpler system butthere were, during the pendency of thelegislation that became the AIA, somegroups that were against adopting anFTF system, arguing that, among otherthings, the FTI system was “more fair”and that smaller companies would bedisadvantaged. Ultimately, the U.S.Congress determined that harmonizationwith the rest of world would prevail andFTF became part of the AIA.An exception to the first to file systemoccurs if the earlier-filed applicant canbe demonstrated to have “derived” theinvention from the later-filed applicant.It will be interesting to see how thesederivation procedures progress andwhether they become complex andexpensive, but the limited scope of thederivation procedure will likely temperthe expenses of this procedure.The “old” law also had a one year“grace period” to allow the inventorto delay filing after, for example,publishing the invention in an article ormaking the invention public (at a tradeshow, for example). However, evenunder the old law, public disclosure orpublication did and could cause problemswith filing outside the United Stateswhere, for the most part, there is no suchgrace period. This potential disabilityto file overseas remains under the newlaw as well since it does not and cannotobviously affect foreign countries’ socalledabsolute novelty statutes.Under the AIA, a limited form ofthe grace period is retained for theinventor’s disclosure for a period ofone year. This is not as broad as a priorart but, again, one must be cautionedthat even though one’s U.S. applicationmay be saved, the inventor may still beprohibited from filing outside the UnitedStates. Also under the AIA, the scope ofwhat is considered to be prior art that isapplicable to an application for patenthas dramatically changed and is of suchimportance that the next article in thisseries will be dedicated to the explanationof the revised prior art system.So what are the strategies thatcompanies might consider followingin dealing with these changes? Hereare several:1) Be the first to file: this seemssimple, but since you cannot rely onbeing the first to invent (and you reallydon’t know anyway) file as the old jokegoes by “voting early and often.”2) With the likelihood that youmay be filing more often, considerfiling provisional applications as soonas possible. There has been a lot ofcontroversy considering the benefitsand deficits of provisional applicationsand the simple fact that provisionalapplications do not get on the queue atthe U.S. Patent and Trademark Office.However, given the circumstances ofthe new FTF provisions, it may bewise to file provisional applicationsand then supplement those provisionalapplications as time goes on and asthe inventions develop and results ofexperimentation involved with theinvention become solidified.3) Review corporate guidelines:while in the past, the process fromconception of the invention to filingpotentially took many months involving:conceiving the invention, recording anddescribing the invention in an inventor’snotebook (more on this below),16Chip Scale Review July/August 2013 [ChipScaleReview.com]

contacting corporate resources, thencontracting client’s patent counsel to draftthe application, drafting the application,making revisions and finally filing. Oftenthis can take up to six months. However,at the time these were done, the inventorcould rely on the belief that he or shewas the first to invent and could prove,by notebooks and by counsel work, thatfrom the date of conception to the date offiling there was so-called due diligencein getting the application on file. Thatprocedure, as mentioned, is now gone.So it’s important to find and choosecounsel who can react quickly rather thanputting your application, “on the pile”for eventual drafting and filing. Set shorttime limits for filing and stick to it andif your counsel cannot make those dates,change counsel.4) Continue to use inventornotebooks: while some might think thatit is no longer important to maintaininventors’ notebooks given the first tofile system and the lack of necessityto show who was the first inventor,that is not entirely true consideringthe existence of the new derivationproceedings. Notebook entries may beimportant in demonstrating that the firstto file inventor derived the inventionfrom a disclosure he or she receivedfrom the real, second filed inventor,through a notebook entry recording thedisclosure to the first to file inventor.Also, the notebook entry can act as an“initiator” of the patent process as towhether to file an application quickly.From the foregoing, and my earlierarticle, it is clear that the AIA hasbrought many changes in the basicU.S. patent law, and like it or not, thesechanges are now with us. In some cases,such as the first to file system, somefundamental changes need to occur inthe way inventions are filed at the U.S.Patent Office. While some protestedthe transition to a first to file system,it is clear that the rest of the world hassomehow been able to cope fairly wellwith it without causing the collapse oftheir economies. Let us hope that thesame occurs here.Please look for upcoming articles onthe AIA in subsequent issues of ChipScale Review.BiographyJason Mirabito received his BSdegree in Engineering Physics from NewYork U., a JD from American U., andan LLM degree from Georgetown LawCenter. He is a registered patent attorneyand a member of Mintz, Levin, Cohn,Ferris, Glovsky and Popeo, P.C.; emailJMirabito@mintz.comŖoHSChip Scale Review July/August 2013 [ChipScaleReview.com]17

largely overcome recently, by GeorgiaTech and its industry partners, by atleast two processes ‐ laser and electricaldischarge ‐ each drilling more than1000 holes in a few seconds. Comparedto FR-4, which is viewed as being thecheapest package material, glass canactually be cheaper, as can be inferredfrom Figure 3. FR-4 requires fourdifferent materials and four differentprocesses to form one pre-preg, twoof them being high temperature glassymaterials, and the other two are resinand flame retardants. Glass requiresonly one material and one process, asdrawn by the latest fusion techniquesby Corning, and by similar processesby Asahi Glass and others. Glass,unlike FR-4, is isotropic which makesvia formation uniform across theentire panel.Figure 2: Potential extendibility of low TCE and high T g organic packages.Figure 3: Simplicity and low-cost nature of glass manufacture.Figure 4: Three interposer options and regimes in bump pitch.SummaryFigure 4 compares silicon, organicand glass packages for lithographicground rules, bump I/O pitch andrelative cost. The Figure shows that Siprovides the smallest bump I/O pitchusing wafer–based sub-micron BEOLprocesses, but at the highest cost.Additionally, it shows that organicsprovide the lowest cost at the highestbump I/O pitch using panel processes.It appears that the limits in bump pitchwith organic packages can readily andquickly be extended by increasing theglass content in low TCE organics from80% with fibers and fillers, to pure andultra thin glass at 100%. Glass is poised,therefore, to fill the gap between submicronwafer–based Si lithography and10µm panel-based organic packages.Glass can eventually be applied to both300 and 450mm wafers in fabs therebytaking advantage of its electricalsuperiority over Si, and in large panelform in package foundries providingboth cost and performance benefits.BiographyRao R. Tummala received his PhD inMaterials Science and Engineering atthe U. of Illinois, and is the Joseph M.Pettit Endowed Chair in Electrical andComputer Engineering and in MaterialsScience and Engineering. He is alsothe Director of the Packaging ResearchCenter (PRC) at the Georgia Institute ofTechnology. Prior to Georgia Tech, hewas an IBM Fellow at IBM Corp; emailrao.tummala@ece.gatech.eduChip Scale Review July/August 2013 [ChipScaleReview.com]19

Cu-Cu Direct Bonding for Ultra-high DensityChip-to-Chip InterconnectsBy Eric Bersch, Chris Kim, Klaus Hummler, Brian Sapp [SEMATECH]in at the CCI interface would wastespace, increase cost and compromiseperformance. Ultra-high density CCI(UHD-CCI) at 10µm pitch or less willbe needed for full area array CCI or forlocally dense interconnect buses. The2012 update to the ITRS Interconnectroadmap (www.itrs.net) predicts CCIpitches as low as 2-3µm for the 2015-2018 timeframe. In addition, the CCIapproach must support the thermal andmechanical requirements of the chip-tochipinterface.While scaling progress is beingmade to finer pitches of solder-basedCCI, it remains questionable if solderbasedCCI will scale below 10µm pitch.Alignment issues, extrusion of soldermaterial, thermal properties of therequired underfill, and reliability issuesrelated to the presence of inter-metalliccompounds will ultimately limit thescaling of solder-based CCI.Figure 1 shows CCI sizes andpitches published at major packagingIn recent years, a trend tointegrate more and more chipswithin one electronic packagehas emerged. This system-in-package(SiP) integration is motivated bylimitation in board-level integration withrespect to power, performance, cost, andspace. The drivers to integrate multiplechips within one package have alwaysbeen present and had previously resultedin a push towards multi-chip modules(MCMs). MCMs have been only mildlysuccessful for higher-end systems dueto cost and complexity issues. Lately,advances in packaging technology haveaccelerated the SiP trend by offeringmany innovative ways of integratingmultiple chips in closer vicinity andat lower cost (flip-chip, package-onpackage,wire-bonded chip stacks,embedded die packages, 2.5D and 3Dchip stacking, etc.). Any successful SIPintegration must solve the challengesin interconnect bandwidth, power, formfactor, and cost.Among all advances in packaging,through-silicon vias or throughsubstratevias (TSVs) have by farthe highest potential for improvedbandwidth, reduced latency, power andsize. By creating a local connectiondirectly through the substrate, TSVsprovide an inter-chip signal and powerpath with unbeatably short lengths andlow parasitics. Leading-edge TSVscan be manufactured at very tightpitches (10µm and below) and cantherefore provide off-chip interconnectsof superior parallelism. To take fulladvantage of the power, form factorand performance benefits of 3D chipstacking, the chip-to-chip interconnect(CCI) method of choice has to be able tokeep pace with the interconnect densityprovided by the TSVs. Fan-out and fanconferencesin 2011 and 2012. Keepin mind that these are mostly researchand development results, and notCCI dimensions qualified in highvolumemanufacturing (HVM). Thetransition from solder reflow, tothermocompression (TC) bonding withsolder, to Cu direct bonding withoutsolder is evident. In the research realm,the transition to solder-less bondingcurrently takes place at about 10µmpitch. The timeline and pitch limit forthe actual transition in HVM fromsolder-based interconnects to solderlessinterconnects is hard to predict,because it depends on many factorssuch as infrastructure, cost, reliability,application drivers, etc.Copper-Copper DirectThermocompression BondingOne approach to replacing solderbasedCCI at pitches of 10μm or lessis direct Cu-Cu thermocompressionbonding (CuDB) [1,2]. In this approach,Figure 1: CCI bump sizes and pitches published at major packaging conferences in 2011 and 2012.20Chip Scale Review July/August 2013 [ChipScaleReview.com]

copper bumps or pads from one chipare connected directly to matchingCu interconnects on another chip bythermocompression bonding. Othermaterials may be involved to facilitate orstrengthen the bond mechanically (hybridbonding), but electrically, a copper-onlyconnection is formed without any intermetalliccompounds. Achieving thebond at low temperatures (i.e., below200 o C) is imperative for good alignment,low warpage, high throughput andcompatibility with other materials likesolder or underfill already present in the3D chip stack at the time Cu-Cu directbonding is performed. Once a good bondis achieved, its mechanical and electricalproperties are virtually indistinguishablefrom bulk Cu properties.Successful CuDB bonding isprimarily a function of surfacepreparation, activation and cleaning.Methods resulting in sufficiently flatsurfaces are mostly wafer processingbased.Therefore, CuDB has beenpracticed primarily within wafer-towaferor die-to-wafer assembly flows.For a truly manufacturable process flow,additional steps like passivation anddepassivation have to be consideredto accommodate queue or shippingtimes and exposure to ambient betweensurface preparation and bonding.Alternatively, in situ surface preparationwithin the bond tool can be considered.Publications about CuDB havetypically focused on one or two of thesenecessary steps. Chemical mechanicalpolishing (CMP) [3, 4] and cuttingusing a diamond bit [5, 6] have beenreported as surface preparation methods.Benzotriazole (BTA), which is typicallypart of any CMP process, and selfassembledmonolayers [7] have beenused as surface passivation methods.Depassivation, cleaning and surfaceactivation have been performed in inertatmosphere, wet chemistry, forming gasand plasma chambers [8-11]. Ultimately,the target of these surface preparationmethods is to enable a short, lowtemperatureinitial bonding step thatfixes the two die surfaces in place andresults in a mechanically strong, voidfreeCu-Cu bond interface.The initial bonding step is oftenfollowed by longer batch anneals tostrengthen the bond and facilitatevacancy diffusion away from theinterface and Cu grain growth. Reportedbond temperatures, pressures andtimes for the initial bond step varywidely. Most bonds were performedat temperatures between 250 o Cand 400 o C. Due to concerns withalignment, warpage, throughput and* patents pendingYou can rely on our award-winning support network.Visit our website to contact your local office:USA | China | Europe | Japan | Korea | India | Singapore | TaiwanFind out more now: advancedjetting.comcompatibility with solder and underfill,bond temperatures below 200 o C shouldbe targeted. To achieve high-volumemanufacturing readiness, wafer-to-waferbond times of a couple of minutes areacceptable, but for die-based assemblyflows, times cannot exceed a fewseconds. Acceptable bond pressuresdepend on the mechanical stability of thejoined devices and must be kept as lowas possible, especially when ultra-low-kFaster,Easier,SmarterJettingThe NexJet ® System*featuring the one-pieceGenius Jet Cartridge*The Genius Jet Cartridge is the onlysystem part that contains fluid — theonly piece that needs tobe changed and cleaned.It is easily removed inseconds without tools.Built-in memory tracksand stores usage data,thereby increasing qualityand consistency in precisionmanufacturing applicationssuch as adhesive dispensing, precisecoating and underfill.Chip Scale Review July/August 2013 [ChipScaleReview.com]21

(ULK) dielectrics are involved. If weuse ULK-compatible CMP downforcesas a guide, bonding downforces onthe order of ~1kN for a 300mm waferwould have to be achieved.CuDB bonding methods generallyfall between two extremes of underlyingfundamental mechanisms. Even poorlyprepared Cu surfaces with significantroughness and some degree of oxidationor contamination can be joined at hightemperatures, high pressures and longbond times. The underlying mechanismsare plastic deformation and materialtransport by Cu and impurity diffusion.On the other end of the spectrum aremethods that result in an atomicallyflat surface, without any contaminationor surface passivation. Once broughtinto contact, we can expect such a pairof surfaces to bond spontaneously atroom temperature and with negligiblepressure, simply due to the overlap ofelectron orbitals. Pursuing the lattermechanism is more likely to achieve thelow temperatures, pressures and shorttimes required for HVM CuDB. In thisarticle, we report what role specificsurface preparation methods, impurities,depassivation steps, and cleans playtoward achieving a close to idealbond scenario. For fast screening ofprocesses, we performed most bondingstudies using blanket copper 300mmwafers, and evaluated results usingCSAM and 4-point bend measurements.Experimental DetailsOn top of the 300mm wafers, stacksof Cu/Ta/TaN/SiO 2 (from surfaceto substrate) were deposited in thecleanroom at the College of NanoscaleScience and Engineering in Albany.After electrochemical deposition ofthe Cu films, wafers were annealedbefore being subjected to CMP. Thenone of several cleaning procedures wasapplied before bonding. Most waferswere exposed to a forming gas anneal(FGA) for 6 cycles of a reference time(6 x ref). Another clean was a nitrogenanneal (NA), which was identical to theFGA but in a 100% N 2 environment.A third cleaning method was a wetchemical (WC) clean, where the waferswere immersed in a proprietary cleaningsolution and then given a spin drybefore bonding. The fourth and finalcleaning method was to expose thewafers to formic acid vapor for a timeof 6 x ref before bonding.Surface Contamination (XPS, CSAM)To study the conditions of thesurfaces of the wafers after cleaning,we performed X-ray photoelectronspectroscopy (XPS) on blanket Cu filmsthat were cleaned by a forming gasanneal (FGA), a nitrogen anneal (NA),immersion in the plating chemistry(WC), or left in the CMP-last condition.The wafers that received the FGA andNA were cleaved into pieces and placedin the XPS vacuum chamber 30 minutesafter cleaning. Cu 2p 3/2 spectra froma sample cleaned by a FGA, a samplecleaned by a nitrogen anneal (NA) anda CMP-last sample are shown in Figure2a. The spectra have been normalizedwith respect to each other. The mainpeak of these spectra, centered at~932.6eV, is primarily due to metallicCu. Peaks due to Cu 2 O and CuO arealso a part of this main peak, as theirbinding energies are not far from thoseof metallic Cu (932.6eV and 933.6eV,respectively) [12], and thus they aredifficult to resolve. It can be observedin Figure 2 that there is a broad featureon the high binding energy side of thespectrum from the CMP-last samplethat is not present in the spectra fromthe samples that received the FGA andNA. This peak is due to Cu(OH) 2 and/orCuCO 3 (accepted values for these peaksare 934.6eV and 935.1eV, respectively)[12]. Thus, the FGA and NA removedthe Cu(OH) 2 and/or CuCO 3 from theCu surfaces.Figure 2b shows the O 1s spectrafrom the FGA, NA, and CMP-lastsamples, where the spectra are plotted incounts per second (c/s). In these spectra,the main peaks for the spectra fromthe FGA and NA samples occur at abinding energy of ~530.2eV. This peakis primarily due to O in Cu 2 O and CuO,which have accepted binding energiesof 530.4eV and 529.6eV, respectively[12]. In the spectrum from the CMPlastsample, the main peak is centered at~531.2eV. This peak has contributionsfrom O in Cu 2 O and CuO, as well asfrom O in Cu(OH) 2 and CuCO 3 , whichhave accepted binding energies of531.5eV [12].An important difference betweenthe O 1s spectra from the FGA andNA samples is that the peak intensityfrom the NA sample is greater. Thiscan be interpreted to show that theFGA treatment was more effective atremoving the Cu 2 O and CuO from theCu surface than the NA treatment.Figure 2c shows the N 1s spectrafrom the FGA, NA and CMP-last andWC samples, where the spectra areplotted in c/s. The N 1s peak on thesesamples is an indication of benzotriazole(BTA) on the surface. The BTA (5methyl-1H-benzotriazole: C 7 H 7 N 3 ) wasa constituent of the slurry used to polishthe wafers after Cu deposition and wasthus deposited on the Cu surface as aresult of the CMP. As the WC samplewas measured two weeks after the WCprocess, the Cu 2p 3/2 and O 1s spectrawere not suitable for the time dependentcomparisons shown in Figures 2aand 2b, but it was included in thecomparison of N 1s spectra, which istime independent. It can be observedthat the N 1s peaks from the FGA,NA and CMP-last samples are verysimilar in magnitude, showing, to a firstapproximation, that the FGA and NAanneals did not strongly remove BTAFigure 2: a) Cu 2p3/2, b) O 1s, and c) N 1s spectra from FGA, NA and CMP-last samples.22Chip Scale Review July/August 2013 [ChipScaleReview.com]

Figure 3: CSAM images from a) FGA-, b) NA- and c) WC-cleaned bonded wafers. CSAM images fromCu films grown by tool/chemistry d) 1, e) 2 and f) 3. CSAM images of wafers annealed to g) 150 o C andh) 350 o C. CSAM images from wafers a) cleaned with an FGA of 4X the reference value, b) bonded for 2minutes with a downforce of 10kN, c)bonded at 180 o C, and d) cleaned with a formic acid vapor treatment.from the surface.A closer look at these peaks showsthat the area under the curve of the peakfrom the NA sample is 6% greater thanthat from the CMP-last sample. Thiscan be explained by the hypothesisthat the NA does nothing to removethe BTA on the surface, and that thereis a thicker atmospheric contaminationlayer on the CMP-last sample than theNA sample, thus attenuating the N 1ssignal from the CMP-last sample morestrongly. In contrast, the area under thecurve from the FGA sample is 12% lessthan that from the CMP-last sample.This suggests that the FGA removed aportion of the BTA. The area under thepeak from the WC sample was 60%less than that from the CMP sample,showing that the WC was more effectivethan the FGA for BTA removal.Figure 3 shows C-mode scanningacoustic microscope (CSAM) imagesfrom the FGA, NA and WC samples,where black within-the-wafercircumference indicates good bondingand grey indicates voiding. It is clearthat the wafers cleaned by the NA didnot bond well, but that those cleanedby the FGA did. It should be notedthat there is a small, pin-hole void inthe CSAM image for the FGA-cleanedwafers, but bonds with a small numberof these voids are still considered to besuccessful. As the FGA treatment wasshown to be more effective in removingthe Cu 2 O and CuO, we attribute lessCu 2 O and CuO on the FGA-cleanedwafers to the better bonding of thesewafers than the NA-cleaned wafers.We also note that good bonding canbe achieved with only a slight (12%)decrease in the amount of BTA on thesurface, as was the case with the FGAwafers. Relatively good bonding wasalso achieved with the wafers giventhe WC clean, though there is someslight voiding near the edge. This goodbonding for the WC cleaned is likelyan indication that this treatment waseffective at removing Cu 2 O and CuOfrom the Cu surface. Since the WCprocess takes less time than the FGAprocess, it is a promising method forhigher throughput Cu-Cu direct bonding.Impurity Concentration (TOF-SIMS,CSAM)Two other factors that may play a rolein Cu-Cu direct bonding are the impurityconcentrations at the surface and in thebulk of the Cu films. We used time offlight secondary ion mass spectrometry(TOF-SIMS) to measure depth profilesfor S and Cl for Cu films grown by threedifferent tool/chemistry combinations.Representative S and Cl depth profilesfrom Cu films grown by each of thesetool/chemistry combinations are shownin Figure 4, where concentration isplotted on a log scale. In these depthprofiles, it can be observed that theS and Cl concentrations decreasedsharply over the top ~10nm of thesefilms, and then were relatively constantthroughout the bulks of the films. Toobtain bulk values for the S and Clconcentrations, we averaged the S andCl concentrations over depths between50-350nm. The S and Cl surfaceconcentrations ranged from S surfacereference and Cl surface reference toFigure 4: TOF-SIMS depth profile of tool/chemistry1, 2 and 3.4.4 x S surface reference and 9.4 x Clsurface reference, respectively, and theS and Cl bulk concentrations rangedfrom S bulk reference and Cl bulkreference to 72 x S bulk reference and134 x Cl bulk reference, respectively.Despite these ranges of S and Cl surfaceand bulk concentrations, good bondswere obtained for Cu films deposited byall three tool/chemistry combinations, ascan be seen in the CSAM images shownin Figures 3d, 3e and 3f.Grain Size (EBSD, CSAM). In thediffusion-based model of Cu-Cu directbonding, Cu diffusion takes place alonggrain boundaries [13]. By this model, aCu film with smaller grains, which hasa higher density of grain boundariesthan a Cu film with larger grains, wouldbond more effectively. To investigatethis effect, we prepared a Cu film withsmaller grains and one with largergrains by annealing them at 150 o C and350 o C, respectively. We performedelectron backscattered diffraction(EBSD) to map the grains in the Cufilms. EBSD grain maps from the 150 o Cand 350 o C annealed Cu films are shownin Figure 5, which had average grainsizes of 1.9μm and 2.6μm, respectively.Despite these differences in averagegrain sizes, wafers that were annealed to150 o C and wafers that were annealed at350 o C were both observed to bond well.Chip Scale Review July/August 2013 [ChipScaleReview.com]23

(a)(b)Figure 5: EBSD images from Cu films annealed at 150 o C and 350 o Cbefore CMP. The average grain sizes for these films were 1.9μm and2.6μm, respectively.CSAM images for wafers pairs annealedto 150 o C and 350 o C before CMP areshown in Figure 3g and 3h.TEM/Four–Point Bend. In addition toCSAM imaging, we used transmissionelectron microscopy (TEM) and fourpointbend testing to evaluate the qualityof the Cu-Cu bonds. TEM imagesfrom wafers bonded at 195 o C and400 o C are shown in Figures 6a and 6b,respectively. In both of these images,the Cu-Cu interface appears to be freefrom voids and is primarily a straightline. A more jagged Cu-Cu interface orone that has disappeared entirely dueto grain growth is indicative of goodbond strength [13], but our four-pointbend results demonstrate that it is not anecessary requirement for a strong Cu-Cu bond.We performed four-point bend testson wafers where the CSAM imagesindicated defect-free bonding. Arepresentative force vs. displacementcurve from a wafer pair bonded at 195 o Cis shown in Figure 6c. The criticalrelease energy extracted from this curvewas 8J/m 2 , which is comparable to othercritical release energiesfrom Cu-Cu bondsreported in the literature[14]. In addition, weobserved that the failureduring this four-pointbend and nearly all othersthat we performed didnot occur at the Cu-Cuinterface, but rather at oneof the other interfaces.This was determinedby performing energydispersive spectroscopy(EDS) on the delaminated surfaces andobserving that Cu was only present onone of the surfaces. This suggests thata clean, void-free, straight line Cu-Cu interface after the initial bond canprovide sufficient strength and stabilityfor 3D interconnect structures.Varying Cleaning and BondingConditions. As the time involved inthe typical FGA we performed is notconducive to high throughput, wetried reducing this time and observedthat an FGA of 4X the reference valuecould also produce a void-free bond, asshown in the CSAM image in Figure3i. Due to the desirability of reducingthe bonding time, temperature anddownforce, we investigated how farthese parameters could be minimizedwhile still achieving a successful bond.We observed that a void-free bond couldbe achieved with a bonding time of 2minutes and a downforce of 10kN, asshown in Figure 3j. When we reducedthe bonding temperature to 180 o C,however, we observed edge voidingin the CSAM, as shown in Figure 3k.Finally, as an alternative to the FGA, weFigure 6: TEM images of Cu-Cu bonded films bonded at a) 195 o C and b) 400 o C; b) Four-point bend testforce vs. displacement curve.cleaned wafers with formic acid vapor,as described above. The CSAM forwafers cleaned with formic acid beforebonding, shown in Figure 3l indicatesthat this clean was not successful inproducing a void-free bond.SummaryThis work shows that, with the rightsurface preparation, high-quality Cu-Cu bonding of 300mm wafers can beachieved at a temperature of 195 o C,downforce of 10kN, and bond time of 2minutes. These bonding conditions areclose to targets compatible with highvolumemanufacturing. The choiceof surface cleaning and depassivationmethods is a major factor, with FGAand WC cleans shown to be mosteffective in removing copper oxides andBTA. Larger Cu grain sizes (fewer grainboundaries) and S or Cl impurities don’tseem to inhibit successful bonding.TEM and four-point bend analysesconfirm that grain growth across thebond interface is not a necessarycondition for a strong bond. All thesefindings indicate that the fundamentalsof our bonding method are close to aregime of a spontaneous bond formationby overlapping atomic states ratherthan relying on Cu plastic deformationand Cu transport by diffusion. Thissuggests that it should be possible tofurther extend bonding conditions toeven lower temperatures, pressuresand durations, resulting in a highlymanufacturable process.AcknowledgementsThe authors acknowledge RobertEdgeworth and Alison Gracias forwork on the four-point bend and postdelaminationEDS measurements. Theauthors also acknowledge Junghyun Choand Shijun Yu for useful discussions onthe XPS and EBSD measurements.References1. L. Peng, et al., “Fabrication andCharacterization of Bump-less Cu-Cu Bonding by Wafer-on-WaferStacking for 3D IC,” ElectronicsPackaging Technology Conference(EPTC), 787-790, (2010).24Chip Scale Review July/August 2013 [ChipScaleReview.com]

2. C. Sanders, “Continued Adoptionof Low Temperature Direct BondTechnology for High Volume 3DCommercial Applications,” 3-DArchitectures for SemiconductorIntegration and Packaging(3D-ASIP) (2012).3. L. Peng, et al., “Ultrafine Pitch(6μm) Evolution of Cu-Cu BondedInterconnects in 3D Wafer-on-Wafer Stacking,” IITC (2012).4. L.Di Cioccio, et al., “An Overviewof Patterned Metal/DielectricSurface Bonding: Mechanism,Alignment and Characterization,”J. Electrochem. Soc. 158 (6), pp.81-86 (2011).5. W. Ruythooren, et al., “Cu-Cu Bonding Alternative toSolder based Micro-Bumping,”EPTC (2007)6. T. Sakai, et al., “Cu-CuThermocompression BondingUsing Ultra Precision Cuttingof Cu Bumps for 3D-SIC,”DPC (2011).7. L. Peng, et al., “ThermalReliability of Fine Pitch Cu-CuBonding with Self AssembledMonolayer (SAM) Passivation forWafer-on-Wafer 3D-Stacking,”ECTC (2011).8. W.H. Teh, et al., “Recent Advancesin Submicron Alignment300 mm Copper-CopperThermocompressive Face-to-Face Wafer-to-Wafer Bonding andIntegrated Infrared, High-SpeedFIB Metrology,” IITC (2010).9. C.S.Tan, et al., “Cu-Cu DiffusionBonding Enhancement atLow Temperature by SurfacePassivation Using Self-AssembledMonolayer of Alkane-thiol,” Appl.Phys. Lett. 95, 192108 (2009).10. T. Sakai, et al., “Hybrid BondingMethods Using Ultra PrescisionCutting for 3D-SIC,” DPC (2012).11. P. Enquist, et al., “Low Costof-OwnershipScalable CopperDirect Bond Interconnect 3D ICTechology for Three DimensionalIntegrated Circuit Applications,”3DIC (2009).12. B. Vincent Crist, Handbooks ofMonochromatic XPS Spectra,Volume 1: The Elements andNative Oxides, Wiley, 1999.13. Y.-S. Tang, et al., “Wafer-LevelCu-Cu Bonding Technology,”Microelectronics Reliability 52,312 (2012).14. J.-W. Kim, et al., “The Effect ofPlasma Pre-cleaning on DirectBonding for 3D Chip Stacking,”Physical and Failure analysis ofIncrease throughput andprevent component waste withSPLICING TOOLSCall us to learn aboutour 1 week splicingkit loaner program!800.608.8273 tapesplice.comIntegrated Circuits ConferenceProceedings, p.1 (2011).BiographyEric Bersch received his PhD inphysics from Rutgers U. and workedas a postdoctoral student at the Collegeof Nanoscale Science and Engineering;he is a Thin Films Characterization andMetrology Engineer at SEMATECH;eric.bersch@sematech.orgTAPE EXTENDERSSPLICING KITChip Scale Review July/August 2013 [ChipScaleReview.com]25

Integrating Diamond to Maximize Chip Reliabilityand PerformanceBy Richard S. Balmer, Bruce Bolliger [Element Six]As semiconductors continueto follow Moore’s Law,with technology nodes inmass production below 20nm, devicepower densities are on a trajectoryto be well above 100W/cm 2 at 14nm(ITRS Roadmap). When combined withthe need for higher power solid-stateswitching devices for power convertersand high frequency components forcellular and satellite communications, theneed to manage higher power densitiesand associated heat is an issue spanningall major segments of the industry.Such power densities, using incumbentthermal interface and heat sink materials,will result in heat sinks scaling inverselyto channel length as device densitiesincrease. Naturally, this will impact theability of device manufacturers to reducedevice size, or enable higher degrees ofintegration and it may force designers tocompromise on performance, or reducetheir design thermal margins, impactingproduct reliability.When determining the reliability of apackaged chip, most failure processesfollow a temperature-dependentbehavior. Like all Arrhenius processes,reaction rates increase with temperature.The same holds true for chip lifetime,hence every 10°C increase in junctiontemperature represents a 2x decrease indevice lifetime. In fact, more than halfof failures in today’s electronic systemsare due to temperature (Figure 1).The quest for improved heatextraction includes higher conductivitymaterials compared to incumbentmaterials such as copper. Syntheticdiamond is an interesting materialfor thermal management includingsemiconductor packaging, especiallyFigure 1: Failure modes in electronic systems.for today’s advanced electronicsystems driving towards higher andhigher power density, as it combinesexceptionally high thermal conductivitywith electrical isolation. In addition,for mobile and aerospace applications,diamond has the advantage of lowdensity (3.52g/cm 3 ) combined withits high thermal conductivity, whichenables small heat spreader dimensionsand makes diamond a very low-weightthermal management solution. Forrugged applications, the high Young’smodulus of diamond (1000 to 1100GPa)helps increase the reliability of theentire package or module. However, tomaximize the effectiveness of syntheticdiamond’s exceptionally high thermalconductivity for thermal managementof packaged chips, careful design of itsintegration into the package is required,particularly at the bonding interfaces.Why CVD DiamondFor over 50 years, synthetic diamondmanufactured using high pressure andhigh temperature techniques (HPHT)has been used for abrasive applications,exploiting its extreme hardness and wearresistance. Over the last 20 years, newmethods of growth based on chemicalvapor deposition (CVD) have beencommercialized to allow for the costeffectivegrowth of single crystal andpolycrystalline diamond. The highestpurity synthetic diamond is manufacturedby microwave assisted CVD.Material purity is important insynthetic diamond where heat istransmitted via phonon (vibrations inthe crystal lattice) transport. In contrast,metals like copper transmit heat via freeelectrons that are also responsible forits electrical conductivity. In diamond,impurities act as scattering centers thathinder the transport of phonons andreduce the thermal conductivity of thematerial. An added benefit of microwaveassisted CVD is that it is a scalabletechnology that deposits diamond overlarge areas (10–30cm in diameter)(Figure 2a, inset), at a cost similarto semi-insulating SiC wafers. Thethermal conductivity of CVD diamondcan be tailored to the applicationrequirements (and budget), and with aroom temperature conductivity that canexceed 2,000W/mK (Figure 2a), is 5xgreater than copper (400W/mK).Many segments of the semiconductormarket, for example power convertorsand solid-state RF power amplifiers, aredriving towards higher power densities,increasing the burden on local thermalmanagement. CVD diamond, whichcombines extreme properties such ashigh thermal conductivity, robustness,low mass and electrical isolation, isuniquely positioned to address thisneed. Application examples wheresynthetic diamond is integrated intochip packages (Figure 2b) as part of athermal management solution include:1) An RF package consisting of discrete26Chip Scale Review July/August 2013 [ChipScaleReview.com]

Figure 2a: Thermal conductivity of commercially available thermalgrades (TM) of CVD diamond compared with alternative materials.Inset is a photograph of a 140mm CVD diamond wafer.RF devices attached to a diamond heatspreader mounted on a CuW flange,where the diamond replaced a 1mmthick beryllium oxide (~200W/mK) heatspreader resulting in a 30% decreasein thermal resistance; 2) A laser diodearray with an emitted output powerof 100W from a 200W input power,where 100W is dumped as heat intothe diamond heat spreader upon whichthe laser diode array in mounted; 3) Anembedded CPU board with a processorflip-chip generating 45W of power, withthe diamond mounted between the topof the flip-chip and the heat frame; and4) A photonic integrated circuit as aheat spreader that also uses its insulatorcharacteristics to enable two chipswithin the package to be close togetherfor better performance.The effectiveness of CVD diamondas a heat spreader in electronicpackages depends very much on howit is integrated into the package. CVDdiamond can be integrated in thefollowing two different ways: 1) Freestanding,individual CVD diamondunits bonded usingconventional metallizationand soldering techniques;and 2) Prefabricatedwafers to hold multipledevices allowing waferscaleprocessing at devicemanufacturers (includingmetallization and mounting),followed by singulationof wafers to produceindividual subcomponents.Integration of CVDDiamond Heat SpreadersOf course, the thermal conductivityalone is not the whole story. To obtaina truly compelling case for usingCVD diamond in electronic packagingthermal management solutions whendesigning a sub-mount, the thermalengineer must consider carefully: 1)The system requirements, i.e., packagesize, operating temperatures andallowable fluctuations, assembly design,provision for heat extraction (radiation,conduction, convection sometimescombined with water or forced aircooling; 2) The device requirements.For example, does the device requirea DC or RF drive signal? What are thecurrent requirements (i.e., a laser diodearray may require 50-100A)? Is the heatFigure 2b: Schematic diagram showing a typical sub-mount architecture incorporation of a chip (or die) anda heat spreader.uniformly distributed across the device(such as in a IGBT), or are there localhot-spots (as in the case of a GaN RFHEMT)? The mounting and interconnecttechnology (i.e., via holes, wirebonding, ribbon connectors, etc.); 3) Theheat spreader characteristics includingthermal conductivity, electricalconductivity or isolation, coefficientof thermal expansion, density (weightis important for mobile, airborne andspace applications), and flatness; and 4)The average bulk thermal conductivity(of the heat spreader and thermalinterface materials) and the thermalbarrier resistance, which contributes tothe overall thermal resistance in the heatpath. These characteristics are key tointegration of CVD diamond into a submountpackage.Thermal Expansion of CVD DiamondWhen calculating the actuallength change of a material from onetemperature to another, it is mostconvenient to use the average expansioncoefficient from a reference temperatureto the final temperature. In other words,the linear expansion coefficient is thegradient of the change in length at aspecific temperature, while the averageexpansion is the gradient of a straightline from the reference temperature.Figure 3 shows a comparison ofaverage expansion coefficient for typeIIa natural diamond and silicon [1] withElement Six measurements of 32.5mmlong bars of polycrystalline CVDdiamond over the temperature range 25to 1300°C.The thermal expansion must beconsidered for a number of crucialreasons. While the use of CVD diamondas a heat spreader is fundamentallyto lower the operating temperature ofelectronic and opto-electronic devices,it can also enable a higher operatingoutput power for the same junctiontemperature. In either case, changes intemperature result in changes in lengthof materials bonded in a stack, whichresults in thermo-mechanical stressin the device. The magnitude of thesestresses depends on the size/geometryof the device and the change inChip Scale Review July/August 2013 [ChipScaleReview.com]27

adhesion. Any deviation of the surfacesmust be accommodated by the bondingmaterial. If the surfaces are not flat, agreater thickness of bonding material isnecessary, thus increasing the thermalresistance. CVD diamond is processedusing a combination of lapidary andpolishing techniques to planarize,control thickness, and apply a surfacefinish to the material. The averagesurface roughness can be controlled toR a

GaN-on-diamond as an integratedthermal solution has been developedin the US by Group4 Labs [8], inJapan by researchers at NTT [9] and inEurope under the European Framework7 MORGaN program [10]. Thisfield continues to advance under USgovernment-funded programs. A furtherdevelopment under the MORGaNprogram was the demonstration of a160W power amplifier with optimizedthermal management incorporatingCVD diamond [11]. This reportdescribes the fabrication of a microwavepower amplifier that operates at2GHz using InAlN/GaN/SiC HEMTtechnology. With a gate periphery of36mm, the power chip reached anoutput power of 160W in pulsed mode,and 105W in continuous wave (CW)mode, due to the optimized thermalmanagement. Two architectures werecompared, the case with the HEMT on a400µm SiC substrate, and the case withthe SiC thinned to 100µm and solderedto a 250µm thick CVD diamond heatspreader. During CW operation, thepower chip dissipates 140W, which in thefirst case results in a maximum junctiontemperature of around 260°C. With thecombination of thinner SiC, and the CVDdiamond heat spreader in the secondcase, maximum junction temperature isonly 200°C, as shown in Figure 4.Figure 4: Optical and thermal image of InAlN/GaN/SiC power chip with a) 100µm SiC and TM180 CVDdiamond heat spreader, and b) 400µm SiC.SummaryWith power densities increasingtoward 100W/cm 2 , the need forthermal management is acceleratingacross much of the semiconductorindustry. High power RF chips andlaser diodes are good examples ofapplications requiring careful thermalmanagement. CVD diamond, with itsvery high thermal conductivity, 5x thatof copper, combined with its insulatingproperty, low density, and high stiffnesscharacteristics, is an attractive thermalmanagement solution in many of thesevery high power density applications.However, careful design of the CVDdiamond heat spreader’s integration intothe semiconductor package is requiredto optimize its thermal managementeffectiveness. With appropriate attentionto differences in thermal expansion,design of the bonding interfaces, andmetallization and joining processes,CVD diamond can significantly lowerjunction temperatures, thereby enablingmuch longer chip lifetime and/orhigher performance.AcknowledgmentTM100, 150, 180, and 200 areTrademarks of Element Six Ltd.References1. G.A. Slack, S.F. Bartram. Journalof Applied Physics, 46, pp.89-98 (1975).2. S. Heinemann, F. Dorsch,R. Dohle, D. Lorenzen,F. Daiminger, DE PatentSpecification 196 44 941 (1998).3. J. D. Albrecht, P. P. Ruden, S.C. Binari, M.G. Ancona, IEEETrans. on Electron Devices, 47, p.2031 (2000).4. E. Reese, D. Allen, C. Lee, T.Nguyen, IEEE IMS, (2010).5. Y. F. Wu, A. Saxler, M. Moore,R. P. Smith, S. Sheppard, P.M. Chavakar, et al., IEEEElectron Device Letters, 25, pp.117-119, (2004).6. M. Garven, J. P. Calame, IEEETrans. on Components andPackaging Technologies, 32, pp.63-72, (2009).7. A.B-. Cohen, J.D. Albrecht, J.J.Maurer, IEEE 2011 CompoundSemiconductor Integrated CircuitSymposium (CSICS), DigitalObject Identifier: 10.1109/CSICS.2011.6062454, (2011).8. J. Cho, Z. Li, E. Bozorg-Grayeli, T. Kodama, D.Francis, F. Ejeckam, F Faili, M.Asheghi, K.E. Goodson, IEEETransactions on Components,Packaging and ManufacturingTechnology, Volume: 3 , Issue:1 Digital Object Identifier:10.1109/TCPMT.2012.2223818,pp. 79 – 85 (2013).9. K. Hirama, M. Kasu, Y. Taniyasu,IEEE Electron Device Letters,33, pp. 513-515, (2012).10. M. Alomari, A. Dussaigne,D. Martin, N. Grandjean, C.Gaquiere, E. Kohn, IEEEElectronics Letters, 46, pp. 299-301, (2010).11. S. Piotrowicz, O. Jardel, J.-C. Jacquet, D. Lancereau, R.Aubry, E. Morvan, N. Sarazin,J. Dufraisse, C. Dua, M.Oualli, E. Chartier, M.A.D.-F.Poisson, C. Gaquière, S.L.Delage, IEEE 2012 CompoundSemiconductor Integrated CircuitSymposium (CSICS), DigitalObject Identifier: 10.1109/CSICS.2012.6340059, (2012).This work was supported bythe European Union projectMORGaN project no. 214610 inthe FP7 framework.BiographiesRichard Balmer received his BEng(hons) from the U. of Liverpool andhis PhD in Physics from the U. ofNottingham; he is a Chartered Physicistwith the Institute of Physics and aMember of the Institute of Engineeringand Technology and is a PrincipalScientist at Element Six Innovation.Bruce Bolliger received his BSEEfrom Washington U. in St. Louis andhis MBA from Harvard U.; he is Sr.Director, Semiconductor Business,at Element Six Technologies; emailbruce.bolliger@e6.com30Chip Scale Review July/August 2013 [ChipScaleReview.com]

Real-Time Dispatching for Semiconductor PackageAssemblyBy Shekar Krishnaswamy, David Hanny [Applied Materials]In semiconductor packageassembly, the wire-bondoperation is a significantstep. Any medium to large-size factoryincludes hundreds to thousands ofwire bond machines. Because of theincreasing complexity of packageswith increasing lead and wire counts,a product lot spends more processingtime in wire bond than other assemblyoperations. This typically drives wirebonding equipment to be an assemblymanufacturing bottleneck [1].The continuous evolution of productsand the migration from integrateddevice manufacturers (IDMs) tooutsourced assembly and test services(OSATs) requires that numerouspackaging technologies co-exist in thesame factory. This requirement createsadditional operational complexitiesthat impact equipment and factoryproductivity. More importantly, it oftenadversely impacts customer deliveryperformance. In the past, the product,technology, equipment, and customermatrix was simple enough for humandecision making to manage and operatethe wire bond process. These challenges,coupled with the growing need toprovide and use suitable data, dictatetimely, accurate, consistent, and scalableoperational decision-making to ensurehigh customer delivery performance.Additional Package AssemblyChallengesAs assembly factories have undergonemajor advancements, the evolution ofsemiconductor products has led to anexplosive number of product and parttypes. This evolution has spawnednumerous challenges associated withcapability imbalances, setups, anddata management.Managing Imbalances in Capability.First, with more factories beingconsolidated into larger factories,the diversity of equipment models,particularly in wire bond, has increasedconsiderably. This diversity is in areassuch as: 1) Degree of automation(manual, semi-automated, andautomated); 2) Product type capability;3) Wire/pad pitch capability; and 4)Wire type and size capability.Even among machines with a similarcapability for these characteristics,disparities exist in reliability, processingspeed, and quality. If not comprehendedaccurately, this inherent imbalancein capability causes problems intactical planning.The next challenge is the executionof the plan at the shop floor level. Amajor IDM has reported a drop in wirebond tool utilization by about 13%(68% actual utilization vs. 81% plannedutilization) [2].Managing Setups. A secondchallenge is managing setups or productchangeovers. The wire bond setupoperation is complex, tedious, anditerative. Although the objective offactories is to achieve a successful firstpass setup, success often follows onlyafter a few iterations. This constraintcauses long setup durations (typicallyin hours) that require a significantamount of technician time. The result islost product because time and units areconsumed during the setup operation.Typically, the planning processassumes a certain number of setups permachine per week. What is commonlymissed during the planning processis that certain setups are sequencedependentand will positively ornegatively impact the productive timeon the machine. As a result, the plannednumber of setups or the planned setuptime is often exceeded. Product prioritychanges, quality problems, unscheduledequipment downtime, improper productrouting, and so forth can cause moresetups to the machines than the planrecommends. Such changes require twowaycommunication—manufacturingknowing the setup quota from planningand planning obtaining feedback whenthis quota has been exceeded so thatfuture plans can be adjusted accordingly.Managing Data. The third challengerelates with data complexity. Typically,data sources in manufacturing arediverse and include factory systemssuch as: 1) Manufacturing executionsystems (MES); 2) Engineering systemsfor product specifications and equipmentcapabilities; 3) Industrial engineeringsystems for processing times andequipment setup times; and 4) Enterpriseresource planning (ERP) systems forproduct demand and supply volumes.With this diversity, it is becomingmore challenging to quickly gatherall needed data for timely decisions.Shortcuts include using stale dataor examining data on processingequipment less frequently and usinghighly aggregated data. Such shortcutsimpact the ability to deliver the rightquantity of product on time to end users.Managing Changes in Assumptions.Finally, the influence of factorydynamics cannot be understated. Evenif good plans are developed, goodexecution mechanisms are in place,and data is aggregated from multipleChip Scale Review July/August 2013 [ChipScaleReview.com]31

sources, the process breaks when changesin assumptions are not understood andoperational adjustments are not properlyexecuted. Example scenarios includeproduct holds, equipment downs, productpriority changes, non-availability ofperipheral resources like paddles/clamps,and so forth.Dispatching Requirements forPackage AssemblyThe complexities of packageassembly have increased significantlyover the years; achieving high end usersatisfaction with on-time delivery andcost competitive products is a primaryobjective. Manufacturing schedulingand dispatching are proven systemsthat contribute towards meetingthese objectives. However, currentmethodologies of manual planning andexecution will not achieve these goals.The effects of factory and customerdynamics are so large that manualmethods characterized by data latency,human latency, human variability,Your Best Testing PartnerAddress: 101 Metro Dr.#540 San Jose, CA 95110Tel: 1-408-452-7680Fax: 1-408-452-7689and errors cannot compete for long.Moreover, such manual methods donot scale in a cost efficient mannerwith changes in product mix, volume,technology, and factory sizes.Solutions are therefore neededthat enable factories to be nimblewith fast decision making. Solutionsmust not only be accurate, but mustexecute quickly and seamlessly.Obtaining real-time data aggregatedfrom manufacturing, engineering,and planning systems is a necessity.In addition, solutions must easilycapture business rules and provideuseful information to all manufacturingstakeholders. Mission criticalrequirements include:Reporting and Business RulesRepresentation. A successful planningand scheduling solution mustprovide data management and datatransformation functions so that plannerscan create weekly, daily, or even pershift plans. The data managementfunctions must have access to real-timeKYECHuge test capacities● HQ in Taiwan & Worldwide Offices, covering USA, Japan, Europe, China and Singapore● Over 2000 sets of test systems and growing● Powerful test capabilities and efficient production logisticsKYEC is a leading providerof testing services andsolutions to the IC industryWide range of test capabilities● Professional testing services, covering Wafer probe, Final test, Pre-Assembly, Burn-in, Backend● Complete testing Solutions and equipment, such as Memory, Logic, SOC, RF, CIS, MEMS● Customized test accessories service● Strong R&D team and advance test technologywww.kyec.comdata so that operational changes can bemade as needed.Dispatching and SchedulingExecution. After a good plan is created,a mechanism to execute to plan mustbe provided. The solution’s executionmechanism must be systematic and notprone to variability in human latency.This means that it must be integratedwith factory MES transactions.The results of material processingdecisions must align with the planwhere the same business logic usedto generate the plan are used in thedispatching and scheduling function.In addition, shop floor and equipmentspecific considerations must beincorporated so that overall factoryobjectives are balanced with practicaloperating constraints.Real-time Data Access andRepresentation. Because the factoryfloor is dynamic, real-time data mustbe used in the decision-making. Thelack of real-time data renders decisionsineffective and makes the planning andscheduling functions less credible. Thispromotes circumventing system logic byhumans leading to higher manufacturingvariability. In addition, real-timefeedback is necessary to the ERP andplanning functions for better planning.Change Management. A successfulplanning and scheduling solutionmust be implemented with minimalimpact on business processes and shopfloor end users. Many good systemsfail because they are implemented asadd-on functions to existing businessprocesses. Other important aspects aremanaging changes in business logic andthe availability of data sources. Suchchanges must be implemented withminimal reliance on complex coding andthe expertise of additional IT personnel.Compliance monitoring. A systemis effective only to its degree of use.A planning and scheduling solutionmust therefore enable usage to bemonitored for effectiveness. Thissupports consistent system executionand reduction in variability. If operatorsdon’t follow dispatch decisions, it mayindicate inherent flaws in businesslogic. Such measurement of operator32Chip Scale Review July/August 2013 [ChipScaleReview.com]

Alpha Radiation Dynamics in Electronics PackagingStructuresBy Brett M. Clark, Derek Grove, Tora Unuvar [Honeywell Electronic Materials]Alpha radiation emissionsfrom IC packagingmaterials have becomea greater concern as device geometriescontinue to decrease, design complexityincreases, and critical charge Q cthresholds become lower. Thetrend towards flip-chip and 3D–ICarchitecture, in particular, has increasedthe need for packaging materials withalpha radiation levels several orders ofmagnitude below ambient. Packagingstructures, including wafer-level solderbumps and copper pillar solder caps, arebeing placed in closer proximity relativeto device transistors. This, coupledwith continuously increasing transistordensities, potentially increases devicevulnerability to alpha emissions fromthese features and can lead to increasedsoft error upset (SEU) rates.The transition to Pb-free, Sn-basedinterconnect solder materials for manyapplications has not eliminated thepossibility of significant levels of alphaemission from tin. Recent literaturereports substantial alpha emission fromhigh purity Sn solder bumps, indicatingthat high purity lead-free materials donot necessarily meet demanding alphaemission specifications [1]. Additionalresearch at Honeywell confirmed theobservation of alpha emission fromsome high purity tin significantly abovethe current industry specification of2 α•khr -1 •cm -2 [2]. The cause of theemission was identified as the tracecontaminate 210 Pb, which is present inconcentrations less than 10 -18 g/g. 210 Pbbeta decays to form 210 Po, which decaysby the emission of a 5.3MeV alphawith a half life of 138 days. Removingimpurities at this level represents asignificant challenge, in part due to thedifficulty of measuring the species ofinterest. Contaminates in this attogram/gram concentration regime are beyondanalytical instrument capabilities, andcan only be measured by specializedlow background radiation counters.Recently, diffusion of 210 Po throughhigh purity tin was documented for thefirst time. Experiments measured theincrease of surface 210 Po alpha emissionas a function of time and temperature,and demonstrated that diffusion at200°C was a factor of ~240 greaterthan at room temperature. The mobilityof this element and the possibility toaccumulate at interfaces presents anentirely new list of questions regardingthe true radiation dose to which sensitivenodes are exposed and the change ofthat dose with respect to temperatureand time. These data challengeassumptions regarding the static natureof radiation sources and suggest thatfurther investigation into potentialimpacts on SEU is warranted. In thisarticle, we propose potential changes inalpha radiation exposure experienced byICs due to these mechanisms.Packaging Overview andApplicationsElectronics packaging strategieshave evolved with the IC technologytrends to support increasinglydemanding interconnect challenges.Those challenges include increasinginterconnect count while decreasinggeometry, and changing from leadcontainingsolders to lead-free solders.Future demands include increasing trendstoward flip chip configurations andimplementation of 2.5 and 3D packagingrequired by device miniaturization.These trends, coupled with theinexorable march of Moore’s Lawpushing transistor density higher, have apotential dual impact on reliability. First,the increasing number of transistors perunit area (and the associated decrease inQ c ) increases the number of targets foremitted alpha particles to strike. Second,the proximity of the sensitive nodeswith respect to the sources of alphaemitters in general decreases with eachtechnology iteration. The dual effect ofincreasing the number of targets anddecreasing the range between the sourceand targets increases the probability ofalpha-induced SEU events.Microsegregation Effects on AlphaDistributionRecent research reported evidence ofnon uniform distribution of trace alphaemitters in tin [2]. This observationis consistent with the phenomenon ofmicrosegregation. Microsegregationoccurs in solid/liquid systems wheretrace element solutes partition betweenliquid and solid phases according to thepartition coefficient K. As solidificationoccurs, trace elements, for which K

and reflow processes, will be subjectto microsegregation. The result is thattrace alpha emitting species will beconcentrated on the interior of a volume.The alpha particle will not escape withsufficient energy to cause a soft errorif the position of the emitters insidea structure is deeper than the alphaparticle range (16µm in tin for a 5.3MeValpha particle). The converse of thisstatement is that the alpha particles willnot be initially detected in the material,and any direct measurements willunderestimate the true concentration ofalpha emitting species in the material.This would be an acceptable risk, andeven be advantageous, if the emitterposition was static, and thus wasshielded inside the structure.If a concentration gradient is present,however, polonium will diffuse tominimize the gradient. This diffusionin tin has been documented to occur ata rate estimated to be 2x10 -25 mol•m -2 •s -1 at 293K, and 4.5x10 -23 mol•m -2 •s -1 at473K [2]. The result will be a uniformconcentration across the volume,but will also effectively increasethe alpha emission from the volumeby transporting emitters previouslyshielded to a depth less than 16µmfrom which they can escape. Theactual emission from the structure willdepend on the specific geometry aswell as the concentration and degree ofmicrosegregation in the material.Figure 1 displays this theoreticaldistribution pictorially. Initially, thelead and polonium distribution isconcentrated on the interior volumeby microsegregation. The initial alphaemission will be relatively small due toself-shielding effects. The 210 Pb parentconcentration will be 160x the 210 Pocontent. In addition, Pb does not exhibitthe same mobility as Po, and maintainsits initial distribution while poloniumbegins to diffuse. The result is a Pbreservoir inside a structure that willcontinuously generate Po, which willproceed to diffuse uniformly across thestructure. This will result in an increasein the number of alpha emitters withinthe escape volume at steady state,and a corresponding increase in alphaFigure 1: Microsegregation and diffusion effects on Pb and Podistribution in a solder sphere.particles escaping from the solder.Since diffusion is a function oftemperature, device temperature willimpact the diffusion rate. For devicesLEADERS INMICRO DISPENSINGTECHNOLOGYSMALL REPEATABLE VOLUMES AREA CHALLENGE, BUT NOT IMPOSSIBLEIF YOU HAVE BEEN CREATINGTHEM AS LONG AS WE HAVE.at ambient temperature,application of power tothe device/chip will resultin a temperature increase,which will in turn increasethe diffusion rate of Posequestered inside astructure to a volume. In this scenario,there is a possible linkage betweenthe alpha emission and SEU rate withchanges in operating temperature.TO DO IT WELL,WE PROVIDE THREE THINGS:Dispensing Expertise in a variety of microelectronicpackaging applications.Feasibility Testing & Process Verification basedon years of product engineering, material flow testingand software control.Product Development for patented valves,dispensing cartridges, needles and accessories.Our Micro Dispensing product line is proven and trusted bymanufacturers in semiconductor, electronics assembly, medicaldevice and electro-mechanical assembly the world over.DL Technology216 River Street, Haverhill, MA 01832P: 978.374.6451 | F: 978.372.4889info@dltechnology.comdltechnology.comChip Scale Review July/August 2013 [ChipScaleReview.com]35

alpha emissions from solder structuresthat exceed the initial emissivity byan order of magnitude. Polonium hasbeen shown to be agile within tinsolder materials, and further researchis being directed to ascertain dynamicsin more complex systems. The mostdirect solution is to utilize consistentlylow alpha solder materials to removethe root cause. Given the risk posedby microsegregation to disguising thetrue activity of the solder material,care is recommended in performingalpha measurements and evaluatingresultant data.Theoretical situations proposed couldresult in increased alpha-induced singleeventtransients, particularly with largergeometry packages. In addition, amechanism for the temperature-inducedincrease in alpha emissivity has beenproposed. While the impacts on specificarchitectures are expected to varywidely, this discussion is directed tostimulate thought on potential additionalfactors relating to SEU causes.DisclaimerAlthough all statements andinformation contained herein arebelieved to be accurate and reliable,they are presented without guaranteeor warranty of any kind, express orimplied. Information provided hereindoes not relieve the user from theresponsibility of carrying out its owntests and experiments, and the userassumes all risks and liability for useof the information and results obtained.Statements or suggestions concerning theuse of materials and processes are madewithout representation or warranty thatany such use is free of patent infringementand are not recommendations to infringeany patent. The user should not assumethat all toxicity data and safety measuresare indicated herein or that othermeasures may not be required.References1. M. S. Gordon, K. P. Rodbell, D.F. Heidel, C. E. Murray, H. H.K. Tang, B. Dwyer-McNally, W.K. Warburton, “Alpha ParticleEmission Energy Spectra fromMaterials Used for SolderBumps,” IEEE Trans. on NuclearScience, Vol. 57, No. 6, pp. 3252-3256, Dec., 2010.2. B. M. Clark, “The Distributionand Transport of Alpha Activity inTin,” Jour. of Microelectronics andElectronic Packaging, at press.BiographiesBrett M. Clark received his MS andPhD degrees in Analytical Chemistry fromBrigham Young U. and is a Senior R&DScientist at Honeywell Electronic Materials;email brett.clark@honeywell.comDerek Grove received his BS degreein Metallurgical Engineering from theU. of Idaho and is a Senior SupplierQuality Engineer at HoneywellElectronic Materials.Tora Unuvar received his BS and MSdegrees in Materials Science from DukeU. and is a Product Line Manager atHoneywell Electronic Materials.eWLBA new path for 3DintegrationUnique multi-die 2.5/3D integrationwith a quantum leapin density and form factor3D below 6mmMulti-Chip2.5D2Dbelow 4mmstatschippac.com/eWLBChip Scale Review July/August 2013 [ChipScaleReview.com]37

Advanced Wafer-Level Packaging Technology for 3DHeterogeneous IntegrationBy Seung Wook Yoon, Patrick Tang, Steve Anderson, Raj Pendse [STATS ChipPAC, Inc.]Three-dimensional (3D)integration is an emergingtechnology that can formhighly integrated systemsby vertically stacking and connectingvarious materials, technologies andfunctional components together into asingle device. This approach is expectedto effect an industry paradigm shiftbecause of its tremendous benefits.3D applications will soon begin toappear in portable memory devicesand high-performance computers, andwill quickly extend to a variety ofelectronic markets such as informationtechnology, nanotechnology andbiotech and medical applications,which will benefit from the highdensity,multifunctional heterogeneousintegration that 3D technology canoffer. The market for portable andmobile data access devices connectedto a virtual cloud will continue to driveincreased functional convergence, aswell as increased packaging complexityand sophistication. Depending on theapproach, the potential benefits of 3Dintegration can vary, including multifunctionality,increased performance,reduced power, small form factor,reduced packaging, increased yieldand reliability, flexible heterogeneousintegration, and reduced overall costs.This article will discuss the roleof advanced wafer-level technologyrelated to fan-in/fan-out (FI/FO) waferlevelpackaging (WLP), copper column,integrated passive devices (IPD) and2.5D/3D through-silicon via (TSV)technology in the development ofintegrated 3D packaging solutions.Advanced wafer-level technology israpidly developing into a versatileplatform for the semiconductorindustry’s evolution from 2D packagedesigns to 2.5D interposers and 3D ICintegration, and is moving to a largerscale panel manufacturing approach tofurther maximize yield, throughput andcost-effectiveness. This article will alsohighlight recent advancements in designand characterization of highly integratedwafer-level solutions, such as extendeddie/flip-chip embedded wafer-level ballgrid array (eWLB) and 3D FO-WLP.2.5D and 3D Packaging EvolutionIncreasing demand for more advanced,smaller and lighter mobile products withsuperior functionality and lower overallcost has driven the development ofinnovative and sophisticated packagingtechnologies. One of the excitingelectronic market trends is the growingavailability of mobile devices, such assmartphones, tablets and Ultrabooks,that fully realize the dream of computingand communication convergence, withadequate bandwidth and speed to providea rich user experience. It is particularlyimportant that the next generation ofWLP meets the increasing demand forhigher bandwidth, improved thermaldissipation and enhanced reliabilityin cost-effective, scalable solutions tosatisfy the growing mobile market.The need for higher levels ofintegration, improved electricalperformance/reduction of timing delaysand shorter vertical interconnects isdriving a shift from 2D to 2.5D and3D package designs. 3D integration isproceeding on three fronts: moving frompackage level (die and package stacking)to wafer level (especially FO-WLP),and, more recently, to the silicon (Si)level with TSV and interposers. Today’snew lightweight mobile computersare innovative devices providing trueconvergence with powerful computingfunctions, high-speed communicationsand visual, sensing, and imagingtechnologies. This convergence ispushing traditional packaging wellbeyond its typical limits in the areas ofform factor, reliability and performance.Choosing the Right SolutionWhile the need to combine moremobile functions in an efficient andlow profile solution is fueling the shifttowards 3D packaging, challengesstill remain in the areas of design, test,mass production, cost, and materialscompatibility. Given that system-inpackage(SiP), package-on-package(PoP), and 2.5D interposer technologieshave become more mature andwidespread, the further deploymentof FO-WLP and TSV will continueto enable the migration to advancedfab technology.Driving forces behind wafer-leveland silicon-based technologies includesmaller footprint, increased functionalintegration, increased I/O density,improved electrical and thermalperformance, and lower cost due tobatch processing. Examples of waferlevelsolutions that address these keyrequirements are: 1) FI-WLP with tighterpitches for shorter signal lengths; 2)FO-WLP solutions with integration;3) High speed memory and processorapplications with high bandwidthinterconnect using 2.5D TSV interposertechnology; and 4) Full implementationof TSV 3D packaging technology formobile products.Fan-out Flip-Chip eWLB Driving2.5D SystemsThe growth of low-power mobiledevice applications, today’s highestgrowth segments for advanced38Chip Scale Review July/August 2013 [ChipScaleReview.com]

packaging, is driven by the need forincreased bandwidth and speed. Thisdrive to put a level of computingperformance and networking capabilityinto consumer and lower cost businesssystems that were once considered highendis driving a more aggressive pushtowards advanced WLP solutions and3D packaging, given the limited formfactors and space required for portability.Wafer-level technologies such aseWLB are leading the way to the nextlevel of thin packaging capability.eWLB provides a robust packagingplatform that can support very denseinterconnection and routing of multipledie in extremely reliable, low-warpage2.5D and 3D solutions.The use of these embedded FO-WLP packages in a side-by-sideconfiguration to replace a stackedpackage configuration or to serve asthe base for a 3D TSV configuration iscritical in enabling a more cost effectivemobile market capability (Figure 1).eWLB has the capability to supportstructures containing multiple die,multiple redistribution layers (RDL)as well as line-width/line-space (LW/LS) ratios of less than 10µm/10µm. Inaddition, technical advancements haveenabled eWLB integration of differentcomponents such as Si devices,integrated passive devices (IPDs),discrete, MEMS or glass-based devicesin a single package.Flip-chip eWLB provides a fan-outarea that features a larger pad pitch andRDL [1, 2]. The I/O reconfigurationminimizes substrate layer numbers,while optimizing electrical performancesuch as combined power and ground.Flip-chip eWLB has the option tointegrate a decoupling capacitor andplace it closer to the device for betterelectrical performance. With eWLB’ssuperior electrical performance, it ispossible to reduce the number of layersin the organic substrate. As shown inFigure 1, a 10-layer flip-chip substratecould be replaced by a 6-layer substrateusing flip-chip eWLB technology.There are many variables in a flipchipsubstrate design, including coppertrace line width/spacing, substrateFigure 1: Extended die/fan-out flip-chip packagingapproach with fewer layers of organic substrate [1, 2].thickness, via pad and via hole size,as well as flip-chip/solder ball pitch.Designs that are converted to eWLBshould be approached utilizingmore actual data to meet electricalperformance and signal integrity.eWLB RDL designs provide optimizedand efficient signal integrity ininterconnection routing that has a coarsebumping pitch (Figure 2). Employinga flip-chip eWLB approach in a designwith a coarse bump pitch should requirea lower cost organic substrate with largepad pitch and reduced number of metallayers. In addition, 3D FO-WLP enablesunique applications for mobile devices,such as the 3D eWLB, eWLB-PoP [3-5]and 3D FO-WLP face-to-face (F-t-F) [6].As shown in Figure 3c, 3D FO-WLPF-t-F methodology is the result of directchip attach using eWLB as an interposerbetween logic and memory componentsfor high-speed data transfer, low signalpath and improved signal integrity.This can be combined with other 3Dpackages (Figure 3a, b) for a highlyintegrated packaging solution.TSV TechnologyPortability and data-on-demand isforcing increased packaging density anda) b)Figure 2: Extended die/flip-chip eWLB packaging technology designoptimization of a) 2-layer RDL in eWLB and b) 6-layer organic substrate fora 10-layer flip-chip substrate.a)b)c)Figure 3: 3D FO-WLP solutions: a) 3D eWLB, b)eWLB-PoP [3-5], and c) 3D FO-WLP F-t-F [6].more cost-effective 3D solutions. Whilecurrent PoP technologies are effectivefor integrating functions in a smallpackage, they lack the high bandwidthand low profile increasingly needed bythe new generation of thin tablets andmore powerful mobile processors.Technical and manufacturing issuesare the key challenges for 3D stacks.These include issues of testability andyield, scalability, thermal performance,and standardized IC interfaces. 3D TSVpackages are being developed to provideheterogeneous integration of memory,logic, graphics, and power functions thatcannot be integrated into single die, andto offer improved electrical performancebelow 28nm from very short and highdensityinterconnects between thestacked ICs.TSV technology is being propelledby the need for much faster processingspeeds and memory width in order tomanage all of the advanced functionsrequired in highperformanceproducts.For successful marketpenetration, the TSVecosystem comprisedof IDMs, OEMs,OSATs, foundries,design houses, andPCB suppliers must beproperly enabled. Theadvantages of the TSVpackaging approachover system-on-chipChip Scale Review July/August 2013 [ChipScaleReview.com]39

(SoC) are many,including higherbandwidth due toshorter interconnects,power reduction,lower cost, greaterminiaturization andgreater modularityand flexibility.Mid-end-of-Line (MEOL).The mid-end TSVprocess flow occursbetween the waferfabrication andback-end assemblyprocess, and supportsthe advancedmanufacturingrequirements of 2.5D and 3D packaging,including wafer-level, flip-chip andembedded die technologies. MEOLassembly includes micro-bumping (abumping technology that offers bumppitches of less than 50µm), temporarybonding/debonding, wafer thinningand planarization, backside via reveal,isolation, and metallization (Figure 4).Back-end-of-Line (BEOL). BEOLassembly includes chip-to-chip (C2C)and chip-to-wafer (C2W) assembly,high-density micro-bump capabilities inboth solder and copper column, ultrafinepitch micro-bump bonding, thindie handling, wafer-level underfill,thin wafer dicing, and micro-bumpsfor flip-chip interconnection. Microbumpbonding technology is critical tothe delivery of fine-pitch, low-profilesolutions for high-performance devices,as illustrated in Figure 5. Figure 6shows a 3D stacked 3D TSV IC package.a) b)c) d)3D Heterogeneous IntegrationIncreasing interconnect densityis driving smaller bond pad pitches,stacked die, mixed interconnect suchas flip-chip and wire bond in thesame package, as well as advancedinterconnect technologies such asinterposers and TSV. For mobile andhandheld applications, portability isa critical factor for product selection.A thinner package can provide betterboard-level reliability as well as a lighterFigure 4: Micrographs of the TSV MEOL process: a) Cu column micro-bump,b) and c) backside via revealed TSV, and d) bump landing pad on TSV.and thinner profile at the system level.This trend is transforming customer ballpatterns to manage the escape routingand costs for system boards.Overall package performance isheavily influenced by electrical andthermal performance. The modelingand management of these functionsFigure 5: SEM micrograph showing cross-sectionof a 3D TSV IC stacked package.is becoming even more critical asexpanded functionality is absorbed infewer packages in these heterogeneous3D packaging structures. This alsomeans that system performance canbe increased and improved if theproper 3D packaging elements can besuccessfully implemented.Increasingly recognized as the nextindustry thrust, 3D WLP SiP (Figure 7)addresses a potentially large need inthe market, including heterogeneousfunctional integration, miniaturization,system performance, system flexibility(die/component sourcing, integration),and testability.Figure 6: X-ray images of a 3D TSV assembledpackage.3D FO-WLP (eWLB) F-t-FA F-t-F configuration [6] is achievedthrough direct chip attach on theBGA side of a standard single sidedeWLB package using direct verticalinterconnects between an applicationprocessor die and a memory diethrough the eWLB layers to enable ahigh bandwidth memory interface withnear-zero parasitics. This FO-WLPapproach is shown in Figure 8 [6]. Suchinterconnection is uniquely enabledby eWLB technology by virtue of thevery fine via pitch (sub-50µm range)for vertical interconnects made possibleby the thin-film structure of the eWLBpackage, which is not feasible usingtraditional build-up substrate technology.There is a need for miniaturizationat the IC, module (or sub-system),and system levels. At the IC level,scaling continues as it has overthe last four decades according toMoore's Law. Additionally, 3D chipstacking technology utilizing TSVshas garnered much attention recentlyFigure 7: 3D SiP wafer-level integration withembedded passives, IPD and discrete components.40Chip Scale Review July/August 2013 [ChipScaleReview.com]

WLP platforms - such as eWLB, areenabling these advances, leading tofurther exciting developments in the3D evolution.AcknowledgementsThe authors would like to thankDr. Han Byung Joon, K.M. Chong,L. Lavin, H. Garonzik, S. Wofford, T.McNaughton, J. Yang, D. Pricolo, T.Strothmann, and the Wafer Level ProductTechnology Marketing and TechnologyDevelopment Team, and CorporateManagement at STATS ChipPAC fortheir support and fruitful discussion.Ultrabook is a trademark of IntelCorporation in the U.S. and/orother countries.References1. S. W. Yoon, et al., “Fan OutFlip Chip eWLB (embeddedWafer-Level Ball Grid Array)Technology as 2.5D PackagingSolutions,” Proc. IEEEElectronics and ComponentsTech. Conf. (ECTC), 2013.2. R. Pendse, “SemiconductorDevice and Method of FormingExtended Semiconductor Devicewith Fan-out InterconnectStructure to Reduce Complexityof Substrate,” US PatentPending, 2011.3. Y. Lin, US Pat.No. 7,642,128, “SemiconductorDevice and Method of Forminga Vertical Interconnect Structurefor 3-D FO-WLCSP.”3. I. K. Shim, et. al., US Pat. No.7,923,295, “Semiconductor Deviceand Method of Forming theDevice Using Sacrificial Carrier.”4. S. W. Yoon, et al., “AdvancedLow Profile PoP Solution withEmbedded Wafer-level PoP(eWLB-PoP) Technology,”Proc. IEEE Electronics andComponents Tech. Conf.(ECTC), 2012.5. R. Pendse, “Thin 3D Fan-outEmbedded Wafer-level Package(eWLB) for Application Processorand Memory Integration,” USPatent Pending, 2012.BiographiesSeung Wook Yoon received his PhDin Material Science and Engineeringfrom KAIST, Korea and an MBAfrom NTU, Singapore and is DeputyDirector, Product Technology Marketingat STATS ChipPAC, Inc.; emailseungwook.yoon@statschippac.com.Patrick Tang received his MBA fromthe U. of San Francisco and is a licensedProfessional Chemical Engineer inthe State of California; he is DeputyDirector, Product Technology Marketingat STATS ChipPAC, Inc.Steve Anderson received his BSEEfrom the U. of North Dakota, and isSenior Director, Product TechnologyMarketing at STATS ChipPAC, Inc.Raj Pendse received his PhD inMaterials Science from the U. of California,Berkeley, a BS in Materials Sciencefrom IIT, Bombay, and is VP and ChiefMarketing Officer at STATS ChipPAC, Inc.42Chip Scale Review July/August 2013 [ChipScaleReview.com]

(SAC) solder tipped copper pillarsthat are nominally 115µm +/-5% tall.The CMOS controller die had soldermask defined attach pads that enableattachment without bridging. Thecopper pillars and the ability to placeinterconnects on a grid across the totalface of the die create a multiplicity ofparallel connections that provide a verylow impedance interconnection scheme.The flip-chip attach conditions used inthe manufacturing process were standardsettings for an SAC solder reflow withnominal placement accuracy.The die stack was then underfilledand the flip-chip die-to-die was attachedto the custom pre-molded open cavityplastic package (OmPP). The CMOSdriver die was attached to the packagedie flag using either a conductive silverfilledepoxy or SAC solder attach.Gold thermosonic ball bonding of theCMOS die was the next step requiredto connect the control pins and improvethe ground connection from the die tothe die attach pad. For ease of assembly,a 1.0 mil gold wire was used, but ribbonbonding could have been used for theground connections.Once the bonding was completed,the assembly was partially molded tostabilize and protect the wire bondsprior to attachment of the thermal heatspreader. The copper heat spreaderwas pre-formed into the desired shapeand attached with solder or superconductive epoxy-filled paste. The finalstep was molding the part to the finalpackage dimensions. So the fabricationprocess flow for the package consistedof selecting the package, attaching thedie stack, curing, wire bonding, clipattach, reflow, fill, cure, and marking.Figure 1 shows a cross sectional viewof the custom PQFN that was designedand fabricated; Figure 3 is the unfilledPQFN, while Figure 4 is a diagram of thefinished product. This completed part hasa 10mm x 10mm footprint and complieswith the JEDEC MO-220 specification.The packaged device closelymatched the simulated and calculatedfigure of merit (FOM) numbers shownin the graph in Figure 5. This wasaccomplished by keeping the packageimpedances at a minimum in two ways.First, the source contact has 3 groups of28 wire bonds connected to the 200µmthicklead frame to reduce unwantedFigure 3: Unfilled PQFN.source inductance and resistance,which could de-bias a high speedGaN transistor. Second, was the lowimpedance copper pillar interconnectthat directly attaches to the integrateddriver on the CMOS side of the device.To manage the thermal requirementsof the package, double-sided coolingwas used to allow the CMOS device onthe bottom to be cooled by thermal viasin the PCB and the GaN transistor to becooled via a heat sink attached to the topside of the package. It was determinedthat with 25 thermal vias under thepackaged device with 1oz copper layersin a standard double-sided FR4 PCB,the CMOS device could dissipateenough heat under all typicaloperating conditions.The thermal decoupling thatthe copper posts between theGaN and the CMOS devicescreated and the top heat spreaderclip enabled a 2-D coolingscheme. There are two thermalpaths and thus two thermal caseto-junctionresistance parameters.Both paths have a thermalresistance less than 1 o C/W andallow for dual cooling pathsfor the drive components andpower transistor. To ensure goodthermal transfer, the die and clipattach adhesive used had thermalconductivity of 60W/m K andgood electrical properties.a)b)Figure 4: package a) before, and b) after, finalmolding.SummaryThis customized GaN packageoffers the significant advantage of aform factor half the size of typicalpower transistor devices allowing fora decrease of the associated printedcircuit board real estate. The electricaland thermal performance, as indicatedon the FOM graph, demonstrates theimportance of the package design andconstruction on overall performance. Theresulting custom PQFN with segmentedlead frame and 2-D thermal dissipationproved to be an excellent package optionfor these power semiconductors.Contact authorBill Lawrence is the East Coast andEurope Technical Sales Manager atQuik-Pak; email bill@icproto.com.Figure 5: Figure of merit (FOM).44Chip Scale Review July/August 2013 [ChipScaleReview.com]

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Taking Copper Wire into High-Volume ManufacturingBy Usman Chaudhry, Willmar Subido [Texas Instruments]The use of copper wirebonding in semiconductorpackages has seen asteady evolution in recent years. Thistechnology offers better performance,is more economical than traditionalgold wire bonding, delivers provenperformance, reliability, quality andcost advantages across analog andembedded processing products, andis gaining broader acceptance in thesemiconductor industry.Developing a robust manufacturablecopper wire bonding process requiresjoint collaboration with wire suppliers,wire bond equipment manufacturers,and tool suppliers. Copper wire hasa narrower process window andchallenges associated with that canbe overcome by developing portablewire bonding parameters across thewire bonder fleet and should result inequivalent productivity and yields togold wire.Copper Versus GoldCopper has normally been the metalof choice for the wires used for powerand communications because it providesexcellent conductivity, durability andductility at an economic cost. Copperhas also been used in recent years for theinterconnections between the transistorson integrated circuits. However, forthe ultra-fine pitch, thin wiring thatconnects an integrated circuit’s die padswith its package leads, chip makers havetraditionally used gold because it is easyto work with in manufacturing. Goldis relatively soft, non-reactive (exceptwith aluminum), and offers sufficientelectrical conductivity for manyapplications, though less than copper.However, high electrical performancedepends on excellent conductivity or,in other words, low resistance. Sincecopper has less electrical resistancethan gold, its conductivity is up to 40%higher, which translates into importantperformance benefits. As a result, coppercan provide significant advantages inhigh-performance communications,computing, industrial equipment andother areas.Copper’s improved thermalconductivity pulls heat awayfrom the die better than gold,leading to better performanceat elevated temperatures andwith greater reliability. Thisperformance advantage isparticularly evident when copperwire is bonded on die pads platedwith thick copper and nickelpalladium finish in analog andpower products where support forhigh currents is essential. In thiscase, the metal joint formed is a solidsolutionweld that is extremely stableat high temperatures. In addition, themetal’s hardness means that bonds staymore stable mechanically in stressedoperating environments. Overall,copper wire bonding is technicallymore challenging than gold, but onceachieved, the wiring is more resilientand performs better, especially in highcurrentanalog products.Copper Wire Bonding ChallengesDespite the cost, performance,quality and reliability benefits, thereare technical challenges in developingcopper as the choice interconnectmaterial for chip-to-package thinwiring. One formidable challengeof using copper is its reactivity withoxygen in the surrounding air. Wirebonders equipped with speciallydesigned copper conversion kits providean inert atmospheric envelope by aforming gas that surrounds the wire tip,thus preventing oxidation throughoutthe bonding process and enablingstronger bonds (Figure 1). Oxidationbuild-up on the wire during the freeair ball formation process can result ina poor and unreliable bond and causewire bonder errors. Forming gas flowrate is controlled within specificationsFigure 1: An overview of a copper wire bonding process thatuses forming gas.and free air ball formation parametersare optimized to eliminate this risk.Forming gas is also used over the entirebonding area to allow continuous wirebonding and prevent any oxidationduring the bonding steps.Another important technical issuehas to do with copper’s hardnessand brittleness relative to gold. Thisimpacts both first and second bondquality and productivity. Semiconductormanufacturers have worked closelywith wire material suppliers to drivedevelopment of new, softer copper wirematerial compositions to enable a highlyreliable process across entire silicon andpackage portfolios. Specifications havebeen put in place around manufacturingfloor life and shelf life for the wire tomaintain the highest levels of quality.It is necessary to handle copperwires very carefully in order toeliminate the risk of damaging bondpads and underlying circuitry duringfirst bond and to form robust stitchesduring second bond without impactingthroughput. New generation wire46Chip Scale Review July/August 2013 [ChipScaleReview.com]

onders are designed to bond copperwires more precisely on circuit pads andlead frames/substrates, with more finelytuned force, heat, and ultrasonic energyapplied to create the bond.Modifications to the bonding wirecapillary design are critical to reducingstress on the silicon. Changes tocapillary surface finish are needed toimprove second bond quality. Becausegold wire is much softer than copperwire, the same capillary cannot be used.For copper wire bonding, a capillarywith a granulated rough tip is neededfor better gripping between wire andcapillary and for better formation ofstitch bond and significant reduction inmachine stoppages.The new bonding techniques forcopper require careful development andthorough testing, with characterizationunder a variety of differentmanufacturing and environmentalconditions, including those designedto be worse than anticipated in actualproduction. In production, maintainingyield and quality levels equivalent orbetter than gold wire is always a majorconcern. Manufacturers must overcomethis challenge by running extensivedesign of experiments (DOEs) earlyin the product development cycle toestablish wide process windows fora high-volume production process.Keeping package type, bonding wirediameter, silicon technology, factory andassembly/test sites in mind, generatingdetailed risk assessments and runningseveral DOEs to establish and qualifyrobust first and second bond processwindows are required. Next, one mustverify the developed process windowsacross multiple bonders to address anybonder to bonder variation and achievea process that is portable over the entirebonder fleet.Once a process has been developedand verified, it is necessary to conductextensive reliability testing at bothlow and high ends of the processwindow to simulate any process drift inproduction and ensure there will be noimpact on product reliability throughextended life cycles. Novel quicktesting techniques should be used toassess reliability impact of any processchanges very early without having torun full qualification. These techniques,combined with regular equipmentmaintenance, calibration and toolingmodifications such as improved leadframe clamping and heater-block designspecifically for copper wire allowachievement of desired productivitylevels in high-volume production.Moving from gold to copper wirebonding requires a slow and carefuladaptation of the technology in orderto gain significant benefits. Becauseof the metals’ different characteristics,the transition is not a simple switch ofmaterials, but a carefully monitoredre-engineering effort that involvesimprovements in packaging materials,silicon chip design rules, manufacturingequipment, environment, andmaintenance in order to provide thenecessary quality and reliability in theChip Scale Review July/August 2013 [ChipScaleReview.com]47

shipped product. Like every stage in ICmanufacturing, the processes of selecting,forming and bonding chip-to-packagewires have to be extremely precise.Packaging materials will need to bemodified for copper wire compatibility.This includes qualifying halogen-freemold compounds with reduced chlorinecontent to eliminate any corrosion riskof intermetallics formed after copperwire bonding. Also to be considered isimproving compatibility and increasingproduct performance with copperwire through enhanced silicon designrules and fan-out across multiplesilicon technologies. It is necessaryto characterize silicon stack-ups andunderlying structures in detail throughwire bonding and reliability testing andput in place design rules to promotethe most manufacturable and reliableproduction process without any impacton device requirements. To preventreliability concerns, it is important toachieve the highest standards of qualityand design, and maintain specificmanufacturing equipment and toolingsfor copper wire, while improvingthe manufacturing environment andquality controls.Prepping the copper wire bondingprocess requires detailed preliminarystudies and experiments and extensivetesting and process qualification sothat customers can have confidencein the performance and reliabilityadvantages of copper wire bonds. As theprocess moves from development intomanufacturing, success with differenttypes of products can drive the learningcurve for assembly.Analog power ICs, where copperwires are bonded to thick copper nickelpalladium plated pads (Figure 2) onthe chip require a stable operation withhigh currents in order to provide a safeelectrical environment for the deviceand the rest of the system. On the otherhand, embedded processing devicesdemand the assembly and operationalspecifications that are characteristic ofhigh-volume digital products, includingprecise, secure bonding of copper wiresto aluminum pads. Additionally, theseproduct areas make use of various typesFigure 2: Copper wire on thick Cu/Ni/Pd bond pads.of leaded packages and ball grid arrays,requiring accommodation of wiringtechniques to different physical layouts.Mastering the challenges involved incopper wire bonding across this widerange of products have resulted in newdevices now being designed from thebeginning with copper wire (Figure 3).The Future of Copper WireCopper wire bonding is here tostay and the semiconductor industryis making tremendous innovativeadvancements in overcoming theremaining technical challenges in areaswhere copper wire could not be used.This includes areas such as automotiveand high-reliability applications, dieto-diebonding at high productivity andyield levels, multi-tier low loop wirebonding, and bonding of unique siliconstack-ups.Improvements in quality across theentire supply chain and manufacturingenvironment, methodical developmentof bonding processes, reliabilitytesting across process windows, anddetailed upfront characterization hasallowed devices in automotive andhigh-reliability applications to startproduction with copper wire.Historically, the die-to-die bondingprocess that uses the stand-off stitch bond(SSB) wire bonding technique avoidsthe use of copper wire due to impacton productivity and yield (Figure 4).Die-to-die interconnect is necessaryto enable multi-chip semiconductorpackages. Wire bonding challenges canbe addressed by running detailed DOEsand characterization and optimizing thewire bond process parameters and tools.Figure 4: Copper wire bonds in a multi-chippackage using SSB bonding.As copper wire is harder comparedto gold wire, multi-tier low loopwire bonding (Figure 5) has been achallenge. This type of bonding isneeded for stacked-die and thin packagesto provide the maximum performanceadvantage with the smallest possibleform factor. Unique wire bondingtechniques, bonding parameters, andcapillary designs can help overcome thisFigure 3: Example of TI’s timeline of copper wire bonding research, development, qualification andproduction ramp.48Chip Scale Review July/August 2013 [ChipScaleReview.com]

Figure 5: Multi-tier low-loop bonding usingcopper wires.challenge and allow such devices to beproduced in high volume with quality,productivity and yields equivalent to, orbetter, than gold wire.SummaryCopper wire has differentcharacteristics as compared to goldwire, which requires any new silicontechnology to have copper wire specificcharacterization done for packageassembly readiness to address anychallenges such as silicon damage dueto wire bonding. These challenges maybe overcome using bonding parameteroptimization, capillary design changesand wire bonder setups. However, it isrecommended that silicon design rulesshould be developed specifically forcopper wire through early wire bondprocess characterization on any newsilicon technology.Copper wire bonding brings greaterreliability, quality and performancein the semiconductor devices thatare designed into a growing rangeof applications. In manufacturingoperations, using copper for wiringprovides a hedge on rising prices thatcan affect the supply of gold availablefor industrial uses. Thus, copper helpsensure a steady supply of componentsthat can support business growth. As thematerials, equipment and tools continueto mature, the semiconductor industrywill realize major benefits with themove to copper wire.Companies must continue to innovate.In the past decade, copper wire bondinghas become one of the most significantinnovations in semiconductor packagingand an important competitive advantage.In an industry where packaging is seenas an integral part of the design processand a strategic product differentiator,a transition to copper wire bondingrepresents an important step in theevolution of packaging technology thatbenefits customers today and in the future.BiographiesUsman Chaudhry received hisBachelor’s in Mechanical Engineeringfrom Georgia Tech and Master’s inMechanical Engineering from SouthernMethodist U.; he is Manager of theWirebond Packaging group withinthe Technology and ManufacturingGroup at Texas Instruments; email:usman@ti.comWillmar Subido received hisBachelor’s in Electronic Engineeringfrom the Technological U. of thePhilippines; he is a Senior WirebondEngineer at Texas Instruments.Compression, SMT, &Thru-Hole PCB MountingLead pitches as low as 0.4mm, up to 125,000 insertions.QuickOn/Off LidFully automated or manually operatedsolutions to test any lead pitch & IC packageQuick TurnLow NRECustom Test FixturesEasy Screw - Lidremoved to show detail.Easy KnobconfigurationMulti-Cavity SocketsSignificantly reduce your socket& labor costs with these multipleIC test and burn-in solutions.1-800-232-7837EMULATIONTECHNOLOGY, INCwww.emulation.comChip Scale Review July/August 2013 [ChipScaleReview.com]49

Cost & Performance for Packaging at 28nm & BeyondBy Bob Chylak, Ivy Qin, Patrick Desjardins, Horst Clauberg [Kulicke and Soffa Ind., Inc.]Advancements in electronicpackaging performance andcost have historically beendriven by higher integration primarilyprovided by wafer fab node shrinks thathave followed the well-known Moore’slaw. However, the tremendouslyincreasing cost of building new fabswill soon cause the performance/costimprovements achieved by moving tosmaller technology nodes to becomenegative [1]. This has initiated the ideaof More-than-Moore and vigorousR&D for greater performance throughpackaging. Substantial performanceimprovements have been realizedthrough wire bonded stacked dieand stacked package-on-packagetechnologies. On the cost side, the recentrevolution in the use of copper wirebonding to replace gold has significantlyreduced packaging costs. Now newhighly integrated heterogeneous 2.5Dpackages with interposers and 3Dpackages containing through-siliconvias have been developed, couplingmemory and logic more closely. Thisenables bandwidth gains at reducedpower by reducing package impedance.While these configurations greatlyimprove performance at lower power,the cost has not yet been addressedadequately. Cost control will beessential for successful mass adoption.Controlling CostWe as consumers have an insatiableappetite for features that requireperformance at low power, but only ifthey come at a low cost. Performancedrives increased chip complexity,which leads to rising design costs,few new market entrants and industryconsolidation. The need for innovativesolutions and the complexity of thesolutions results in rising cost forR&D. Increasingly R&D partnershipsand collaborations are formed tospread these costs. Greater packagecomplexity also results in increasedmanufacturing costs, which lead tocontinued progression of manufacturingoutsourcing. This is all in the contextof the volatile global economy thatsuggests careful inventory managementto control cost.Copper wire bonding will continueto be the lowest cost packaging option.Major subcontractors such as ASEhave copper wire bond roadmaps thatextend to the 20nm node [2]. Cu wirebonding will always be less costlythan existing alternative interconnecttechnologies for advanced packages –for example flip-chip, or TSV. This isdue to the extra process steps, materialscosts, and poor assembly throughputsfor 2.5 and 3D packages. Today, manyof the fundamental technical hurdlesof creating these advanced packageshave been solved; next, cost reduction,productivity and yield improvementsare coming into focus.Advances in Cu Wire BondingCu wire is about one-tenth the costof Au wire. In a cost comparison of thethree leading interconnect technologiesAu wire bonding, Cu wire bonding andflip-chip, Au wire bonding becomesmore expensive than flip-chip fordevices with 1024 I/Os and more. If Cuwire is used, the cost is lower with wirebonding than flip-chip for packages upto 2000 I/O count [3]. For a 48 leadQFN, a 25% reduction in assembly costwas achieved [4] when switching fromAu to Cu wire bonding. Other benefitsof Cu wire include better electricalconductivity and mechanical strength.The enormous cost advantage of Cuwire bonding makes it a very attractivesolution. However, there are severalmajor challenges with Cu wire bonding.First is the requirement of a cover gasdelivery system to prevent Cu oxidationduring free air ball formation. Themost advanced flow system designs,guided by computational fluid dynamicssimulations and flow visualization,enable lower levels of oxygen withreduced amounts of inert gas flow [5].Figure 1 shows the flow simulation forone of the latest gas delivery systems.The second challenge has to do withthe increased energy required to formgood bonds between a Cu ball and aFigure 1: CFD model of IConn ProCu gas deliverysystem.pad. Cu balls are about 40% harderthan Au balls and also work-hardenmore. These factors increase the riskof dielectric layer crack and Al splashcompared to Au wire and result in asmaller first bond process window.Process window is defined as a rangeof parameter settings that can meet thetarget specifications. In a study done in[6], the Cu first bond ultrasonic currentwindow is only half that of a similar Auprocess. A narrower process windowalso exists for the second bond due to50Chip Scale Review July/August 2013 [ChipScaleReview.com]

the increased hardness of the materialand lower bondability of the wire. Whilea single level of force and ultrasoniccurrent are often used for Au processes,a good Cu process often requiresmultiple levels of force and ultrasoniccurrent and sometimes also table scrubin different stages. Process optimizationbecomes a very challenging task.New ProCu TM processes enable faster,better process recipe optimization andachieve wider process windows [5].Additionally, these processes are modeldriven processes, in which defaultbonding parameters such as ultrasoniccurrent and bonding force are calculatedbased on desired bonded ball diameter,which is a user input – K&S refers tothis as “response-based parameter”input. A set of adjustments are availableto account for material variations. Thisapproach enables faster, better processrecipe optimization and can achieve aprocess with a wider process window[5]. These new processes have beenwidely implemented in production forthe most challenging devices today.The third major challenge is passinghumidity-related reliability tests suchas the highly accelerated stress test(HAST), because Cu/Al intermetalliccompounds are more easily corrodedthan Au/Al intermetallic compounds [7].Passing HAST reliability testing wasenabled by the development of moldingcompounds formulated for Cu wire [7].Pd-coated Cu wire has better corrosionresistance and can pass HAST testsmore easily [8]. Optimized wire bondingprocesses with good IMC coverage alsohelp to ensure reliability [9].There are two main types of Cuwire – Pd-coated Cu wire (PCC) andbare Cu wire. The main advantagesfor PCC wire are its better reliabilityperformances and better second bondcapability. Because of these advantages,PCC wire is more popular than bareCu wire in fine pitch production(< 1mil wire diameter) today. The maindisadvantage of PCC wire is that it isabout twice the cost of bare Cu wire.Other cost reduction in wirebonding interconnect comes from newdevelopments in substrates and leadframes. New technology such as preplatedframes (PPF) and uPPF for QFPand QFN reduce the plating materialcost. PPF reduces cost by eliminatingthe wet processing steps in assembly,including deflash and tin plating. Oneof the issues with some of these newpackages is second bond bondability.Due to the thin plating, secondbondability is often reduced resultingin a narrow process window. Reducedcapillary life is also seen with thesetypes of packages. One advancementin capillary technology was thedevelopment of roughened surfaces.Figure 2 shows a “granular surface”capillary that can provide an increasedgrip to the wire and can provide moreeffective bonding. A wider processwindow and longer capillary life isoften found in this type of capillary.Over the past decade, the industry’sEVG ® LowTempDebonding PlatformEVG ® 850 XT Frame HVM TB/DB Production SystemMultiple adhesives supply chainHigh throughput production systemsIntegrated metrology for process controlGET IN TOUCH To Discuss Your Manufacturing Needswww.EVGroup.comChip Scale Review July/August 2013 [ChipScaleReview.com]51

Figure 2: A “granular surface” capillary helpssecond bond strength and process window.fundamental R&D in copper wirebonding has resulted in improvedknowledge of Cu wire bonding andmany improvements in bondingequipment, processes and materials. Theimproved technology and productioncontrol enabled the successful Cu wirebonding transition to high-volumemanufacturing. 0.7 mil and 0.8 mil wireare widely used in production and 0.6milwire bonding has been demonstrated inproduction environment on advancednodes such as the 28nm technology node[2]. Today, Cu wire bonding makes upover 30% of total wire bonding [2]. Dueto its low cost, flexibility, demonstratedcapability at advanced nodes, and largeinstalled base, wire bonding is here tostay and grow. Future advancementswill come from the further proliferationof Cu wire bonding, increased share ofbare Cu wire, low cost packages suchas QFN, PPF, and uPPF, as well as finepitchbonding to advanced nodes.Controlling Costs inThermocompression BondingWhile wire bonding remains themost cost-effective interconnecttechnology and will remain so for sometime to come, advanced packaging isemerging as the highest performancepackaging technology. However, anywidespread adoption in consumerelectronics will require a dramaticdecrease in manufacturing cost.Improvements in equipment cost-ofownership(CoO) will be the mainpathway toward reducing overall costsfor this technology. Throughput as afunction of cost for the bonder is onecomponent of this equation. But as hasrecently been pointed out in detail [10],controlling yield in multi-chip packagesis equally important for controlling cost.Next-generation thermocompressionbonders will play a vital role in bothimproved throughput-per-cost and yieldimprovement. We believe that the bestcost-performance in a high-volumemanufacturing environment can only beachieved by highly function-specific,rather than highly versatile multi-use,assembly equipment.Productivity and ControlK&S is developing the nextgenerationthermocompression bonderto provide a much improved cost andperformance solution. Our emphasisis on higher throughput and yields bybringing greater control over the processand providing integrated process qualitycontrol features. The greater control isrendered by better force accuracy, submicronposition control and thermalstability and thermal uniformity at thetool during ultra-rapid heating andcooling. Many current bonders fall shortin these capabilities and have to tradeoff speed for process robustness.Better control with higher speed isachieved through state-of-the-art motioncontrol, motor designs, thermally stabledesigns with advanced materials, andsensors that reflect true position and truetemperature at the die being placed. Thecommonly used method of measuringaccuracy using glass scales insteadof a real bonding process neglectspotential shifts from the temperatureramps and flexing under high pressure.Improved metrics for measuringaccuracy are needed. Many currentbonders do not have sophisticatedservo-controlled linear motors and donot control temperature at the die andZ-position adequately. Figure 3a showsan example of a good joint made withour precise temperature and motioncontrols. In contrast, Figure 3b showsjoints with over squashed solders madeby a current bonder, which could lead topotential yield losses.One effective way to develop betterdynamic motion and temperature controlis through computer modeling. Figure 4compares the finite element modelFigure 3: Thermocompression bond made by K&Swith 50µm pitch Cu pillar test device on Cu-OSPtraces showing good solder flow; b) Cross section ofa commercial device produced on a current bonder.of the temperature distribution of thebonding tool during a rapid temperatureramp typical of a thermocompressionbonding process to that measured witha thermal camera. The close correlationof the two images confirms the accuracyof the model, and the model providesmuch more fundamental insight into thebehavior of the system and how it mightbe improved.To achieve cost effective bondingprocesses, equipment and materialsneed to be designed hand-in-handcollaboratively, not independently. Thisis analogous to our cooperation withmolding compound manufacturers thatwas essential in getting Cu wire bondinginto high-volume manufacturing.To achieve the fastest processes, theproperties of non-conductive paste(NCP) underfill as a function of time andtemperature need to be understood ingreat detail. This can only be achievedthrough collaboration between equipment,materials suppliers, and end users.Yield EnhancementNext-generation bonders will needbetter on-bonder inspection capabilitiesto improve yields. One of the assemblyyield issues is ultra-thin die crack (withTSVs) during dicing or die picking.Figure 4: a) Thermal FEA model, and b) actualthermal image of a place tool during a fasttemperature ramp. The dotted rectangle in b) showsthe approximate location for a 15 x 15mm die.52Chip Scale Review July/August 2013 [ChipScaleReview.com]

We are improving die picking and alsoadding the ability to detect crackeddie before they are assembled andexpensive packages are lost. At a costof more than $1/cm 2 for an interposer,and more than $7 for a typical 10 x10mm die [10], placing a crackeddie onto a good package can be veryexpensive. Other yield enhancement weare developing include new sensors forbetter control of the dispense processand accuracy inspection capability for40µm pitch pillars.SummarySemiconductor packaging isresponding aggressively to provide lowercost and higher performance solutionsin the face of a slowdown in front-end(Moore’s Law) advances. Tried-andtruewire bonding has responded byenabling much lower cost copper wireto replace gold wire, and new advancedinterconnect technologies are enteringthe market. Optimization of the assemblyequipment, materials and processes foradvanced packaging is still needed tomake it a true commercial success.References1. H. Jones, “Feature DimensionReduction Slowdown,”International Business Strategies,Inc.; www.embedded.com/discussion/other/4238315/Feature-dimension-reductionslowdown,March 2012.2. R. Rice, “Wire BondInterconnect: Will It Stand theTest of Time in Era of ShrinkingTechnology Nodes and IncreasingTechnology Complexity?”IMAPS Workshop, Jan., 2013.3. C. A. Palesko, E. Jan Vardaman,“Cost Comparison for Flip Chip,Gold Wire Bond, and CopperWire Bond Packaging,” 60thECTC, 2010, pp. 10-13.4. L. C. Mathew, “Developments inCopper Wire Bonding,” IMAPSWorkshop, May, 2011.5. B. Chylak et al., “Copper High-Volume Manufacturing R&D toProduction,” 13th EPTC, 2011.6. I. Qin, et al., “Ball Bond ProcessOptimization with Cu and Pd-Coated Cu Wire,” CSTIC 2012,pp. 891-902.7. H. Abe, et al., “Cu Wire and Pd-Cu Wire Package Reliability andMolding Compounds,” Proc.62nd ECTC, May 2012, pp.1117-1123.8. T. Uno, et al., “Surface-enhancedCopper Bonding Wire for LSI,”Proc. 59th ECTC, 2009, pp.1486-1495.9. I. Singh et al., “Pd-coatedCu Wire Bonding ReliabilityRequirement for Device Design,Process Optimization andTesting,” IMAPS Conference,Sept., 2012.10. C. Palesko, et al., “Cost DriversFor 2.5D and 3D Applications,”9th Inter. Conf. and Exhibitionon Device Packaging, IMAPS,March 2013.PRELUDE 200/300SOUTH HALL 2041VORTEX WAFER PACKING SYSTEM* For 8”~12”, 50 to 800 µm wafers; warped, bumped or perforated* Non-contact vortex end effector equipped with Quartet’s proprietary SoftTouch mechanism that ensures safe handling of wafers without damage,shift, or rotation* Quartet’s advanced air management system automatically establishesoptimal air flow based on target requirementsFor datasheet, please contact inquiry@quartetmechanics.com | www.quartetmechanics.comP +1.408.200.8345 | F +1.408.200.8341 | 2343 Bering Drive, San Jose, CA 95131, USAChip Scale Review July/August 2013 [ChipScaleReview.com]53

Latest Insights in Thin Wafer Handling TechnologiesBy Margarete Zoberbier, Stefan Lutter [SUSS MicroTec]The demand for furtherimprovement of semiconductordevice performance, suchas processing speed, lower powerconsumption, and smaller form factor,has made 3D integration technologyemploying through-silicon viatechnology (TSV) increasingly moreattractive. Thin-wafer handling (ortemporary bonding/debonding) andpermanent wafer bonding are the keyenabling technologies for 3D integration.After attaching the device wafer to asolid carrier, it can be thinned to exposeTSV nails, handled through the backsideredistribution layer (RDL) steps andmicro-bumping. Eventually, thin die canbe stacked using permanent bondingmethods. For reliable thin-waferprocessing, the selection of a suitabletemporary bonding adhesive is crucial.Distinct adhesive properties, such asthermal stability, chemical resistance,and mechanical strength are required forthe actual production processes.To meet the tight requirementsfor recent new applications, roomtemperaturemechanical debondingmethods have been improved over thelast few years and tailored for specificapplications. Mechanical debondingat room temperature induces littleor no mechanical or thermal stresson the device wafer, and thereforeovercomes the major drawbacksthat have been described with otherdebonding methods.This article highlights the latestinsights in thin-wafer handling, ortemporary bonding and debonding,especially room temperature mechanicalrelease methods and laser-assistedroom-temperature debonding, whichhave both gone through significanttechnical evolution.Temporary Bonding and DebondingRequirementsForecasts for the demise of Moore’sLaw are fairly common. There is alimit to making smaller features wherecost and complexity issues becomeprohibitive. The semiconductor industryhas established, rather quickly, a newpath forward focused around 3D stackingof integrated circuits. Adding a thirddimension to an integrated circuit packsmore transistors into the same smallfootprint without the need to shrinkthe features of the circuit. The layersare stacked like floors in a skyscraper,effectively allowing Moore’s law tocontinue, albeit, down a slightly differentpath. 3D integration, or vertically stackedchips or wafers, requires new technologyand new equipment, specifically newadhesives and 300mm wafer bonders, asthe newest technology is focused on thelarger more efficient 300mm wafer size.Just as chemical mechanical polishing(CMP) became the enabling technologyfor the industry years ago, temporarywafer bonding has been identified as itsnext enabling technology. Temporarywafer bonding and debonding haveemerged as challenging processesnecessary for most 3D integrationschemes. The selection of a suitabletemporary adhesive is the key to success.TSV processing places significantlyhigher technical demands on theadhesive system compared to MEMSor GaAs processing on smaller wafers.The adhesive must be able to withstandtemperatures of up to 300°C or more,while at the same time be easily removedat room temperature. It must be resistantto a wide range of semiconductorchemicals that it will contact, fromsolvents and acids, to plating solutionsand cleaning agents. Finally, it musthave a very gentle debond processimparting the least amount of stress ona fragile wafer thinner than a strand ofhuman hair.Thin wafers ‐ those for which thefinal device wafer thickness is typically30–100µm ‐ need to be processed andalso need to be mechanically stiffenedby temporary carriers, which can bereleased easily after the processing isfinished. There are a lot of requirementsthat temporary carrier solutions need tofulfill based on the variety of differentconditions in process type, wafer type andthe final device application. Figure 1 showsthe general process flow for temporarybonding and mechanical debonding.Today’s requirements for temporarywafer bonding adhesives and processingequipment are characterized by thefollow-on processes, like bump reflow,plasma-enhanced chemical vapordeposition (PECVD), lithographyprocesses, chemical mechanicalpolishing (CMP), etc. Therefore, nooutgassing, e.g., for PECVD processes,is desired, whichmeans, in general,vacuum processcompatibility.Temperaturestability is alsoone of the keyrequirements.Thermal stabilityof 250°C to 350°Cis required, forexample, in bumpreflow steps. Dueto lithography,CMP, and recessprocesses,Figure 1: General process flow for temporary bonding and mechanical debonding.54Chip Scale Review July/August 2013 [ChipScaleReview.com]

the chemical compatibility is of keyimportance as well. The system needsto be easy to debond, as thermal ormechanical stress can reduce theyield. It needs to be easy to clean(no chemical stress). The adhesivesused for temporary bonding needto have a wide range of thicknessesbecause of the different applications(see Table 1). The ranges of therequired TTVs vary between 2 and5µm and are dependent on the typeof topography that is embedded inthe adhesive. Finally, the possibilityto reuse or recycle the carriers is animportant aspect.LatestInsightsinThinWaferHandling FINAL 052113 p. 5List of figures and tables:Table 1: Overview about TTV requirements depending on the application/topographytype.Figure 1: General process flow for temporary bonding and mechanical debonding.Figure 2: Principle workflow of laser assisted debonding.Figure 3: Debonding method: carrier vs. device release.Figure 4: Setup of laser debonding with a 248nm UV excimer laser and x-y movingstage.Table 1.Table 1: Overview about TTV requirements dependingon the application/topography type.2.5D/3D-IC Process Compatibilityand Debond MethodsThe different debond methodsare solvent or laser release, thermalslide, and mechanical debonding atroom temperature. These debondingtechnologies need to meet a number ofdifferent requirements, which are: highthroughput capability, low cost carriermaterial (standard silicon or glass), andin some applications, silicon carriersare preferred, and finally, it is requiredthat there be no mechanical, thermal orlaser-induced stress on the device waferduring debonding. Having a closer lookat these requirements shows clearlythat not all the available methods aresuitable for 2.5D/3D-IC applications.Solvent release is a time-consumingprocess, while thermal slide debondinginduces mechanical and thermal stress.Only mechanical debonding at roomtemperature meets the conditionsmentioned above. Nevertheless,excimer laser-assisted release methodsare promising candidates too, as thesemethods fulfill all requirements exceptthe need for compatibility with asilicon carrier.Laser-Assisted Room-TemperatureDebondingAnother alternative besidesmechanical debonding is a laserassistedroom temperature process,which uses glass carriers with sufficienttransmission at the wavelength used fordebonding. The laser release is achievedthrough irradiation using a 248nm or308nm excimer laser. In contrast to asolid-state laser, which leaves a thermalfootprint, the excimer laser breaks thechemical bonds in the adhesive closeto the glass carrier interface. Whileachieving very high throughput, excimerlaser debonding does not produceany thermal or mechanical stress onthe device wafer. Figure 2 shows aprinciple workflow of laser-assisteddebonding. What makes it so interestingis the advantage over the other methodsin process time. For selected adhesives,a 200mm temporary wafer stack can bedebonded in 30s with an appropriatelysized laser system as shown in thedescribed test run below.Temporary Wafer Bonding Services forAdvanced IC Packaging.Syagrus Systems is the premier supplier partner forproviding temporary wafer bonding and ultra thinwafer processing services, including wafer thinning,dicing, inspection and pick and place. Whether yourneeds are at the prototype or production level, youcan get it to market faster with Syagrus Systems.• Temporary Wafer Bonding Using 3M Wafer Support System• Ultra Thin Backgrind to 25µmWafer is supported on the entire face and the edges.• Automated Wafer DicingBackgrindLineWafer• Automated Wafer InspectionUV-Cured Liquid Adhesive• Automated Pick and PlaceLTHCReleaseLayerGlass Carrier651.209.65154370 West Round Lake RoadArden Hills, MN 55112www.syagrussystems.com©2012, Syagrus Systems, LLCChip Scale Review July/August 2013 [ChipScaleReview.com]55

Figure 2: Principle workflow of laser-assisted debonding.Debonding of the glass carrier wafer can be obtained byirradiation of the adhesive bond layer through the glass waferusing a 248nm excimer laser. In the following discussion ofthe test run, some results with DuPont HD3007 adhesive aredescribed. The absorption spectrum of the adhesive layershows that wavelengths

In the case where the release layer is on the device wafer(Figure 3, device release), the adhesive layer will stickto the carrier after debonding from where it needs to besolvent cleaned or ashed. Device wafer cleaning is typicallya very short process as the release layer residue is very thincompared to the adhesive that is left on the carrier.SummaryTemporary wafer bonding has an important role in 3D-IC applications. Wafer bonding and debonding are essentialrequirements and the only viable means to achieve costeffective chips. The selection of temporary bonding materialsis governed by a comprehensive review of the thinned waferprocessing steps. The physical and chemical requirements ofthese processes are well known and involve standard CMOSfabrication methods. The temporary carrier in essence isthe facilitator that allows for the thin wafer to continue instandardized equipment steps. Bonding temporary adhesivesis straight forward and uses bonding equipment that is verysimilar to what has been widely used in other industries, theMEMS industry for example, for nearly twenty years.Debonding methods can be tailored to the applicationwith respect to device wafer compatibility. Thermal, solvent,mechanical and laser release can be chosen, dependingon the nature of the process flows. More importantly,the variety of materials and carrier combinations enableend users to balance all considerations and arrive atvolume manufacturing cost targets that are in line withmarket expectations.References1. K. Zoschke, T. Fischer, M. Toepper, T. Fritzsch,H. Oppermann, T. Braun, et al.,“Polyimide BasedTemporary Wafer Bonding Technology for HighTemperature Compliant TSV Backside Processing andThin Device Handling,” ECTC 2012, 29.5.-1.6.2012,San Diego, CA USA.2. J. Hermanowski, “Thin Wafer Handling – Study ofTemporary Wafer Bonding Materials and Processes,”http://www.suss.com/fileadmin/user_upload/technical_publications/thin_wafer_handling_temporary_wafer_bonding.pdfBiographiesMaggie Zoberbier received her degree in Mechatronics/Precision Engineering from the Georg Simon Ohm U.of Applied Sciences in Nuremberg and is a BusinessDevelopment Manager at SUSS MicroTec LithographyGmbH; email margarete.zoberbier@suss.comStefan Lutter received a degree in MicrosystemsEngineering from the U. of Applied Sciences in Regensburg,Germany, as well as a Master of Business and Engineering(MBE®) degree from Steinbeis U. in Berlin. He is theInternational Product Manager for temporary bondingsystems at SUSS MicroTec Lithography GmbH.ZoneBOND ® TechnologyThe Versatile Solution forThin Wafer HandlingMaterialsProcessesequiPMentVisit us atSEMICON TaiwanBooth 539www.brewerscience.comChip Scale Review July/August 2013 [ChipScaleReview.com]57

INDUSTRY NEWSIWLPC Keynote AnnouncedThe Origins of Silicon Valley: Whyand How It Happened HerePaul Wesling,CPMT SocietyDistinguishedLecturer, a CPMTSociety DistinguishedLecturer, will givean exciting andcolorful history of device technologydevelopment and innovation that beganin San Francisco and Palo Alto, moveddown the Peninsula (seeking lower costsand better housing), and ended up in theSanta Clara Valley during and followingWorld War II. You'll meet some of thecolorful characters – Lee DeForest,Bill Eitel, Charles Litton, Fred Terman,David Packard, Bill Hewlett and others–who came to define the worldwideelectronics industries through theirinventions and process development.The 10th Annual International Wafer-Level Packaging Conference bringstogether the semiconductor industry'smost respected authorities addressingall aspects of wafer-level, 3D, TSV, andMEMS device packaging. This yearthe conference and tabletop exhibitionwill be held November 5-7, 2013 atthe DoubleTree by Hilton Hotel in SanJose, California.Conference sessions will exploreleading-edge design, material, andprocess technologies focused on waferlevelpackaging (WLP) applications.Special emphasis will be placed onthe numerous device and end productapplications (RF/wireless, sensors,mixed technology, optoelectronics) thatdemand WLP solutions for integration,cost, and performance requirements.Exhibit space is limited but thereare still tabletop spaces available.Please contact Emmy Garner,emmy@smta.org at SMTA or CSRsales representative Ron Molnar atrmolnar@chipscalereview.com withquestions or for more information aboutthe exhibition.Sponsors UpdateACM Research has accepted theGold Sponsorship.Based in Shanghai, ACM Researchmanufactures innovative tools andnovel processes for advanced copperinterconnect technologies includingelectroplating, TSV cleaning and stressfreepolishing. ACM has an IP portfolioof over 100 patents filed internationally,of which over 60 have been granted.ACM is committed to providingtheir customers with advanced andaffordable solutions, world-class qualityproducts,and excellent service.Applied Materials is the 10thAnniversary Reception Sponsor.Applied Materials, Inc. (Nasdaq:AMAT)is the global leader in providinginnovative equipment, services andsoftware to enable the manufacture ofadvanced semiconductor, flat paneldisplay and solar photovoltaic products.Applied Materials technologies helpmake innovations like smartphones,flat screen TVs and solar panels moreaffordable and accessible to consumersand businesses around the world.Brewer Science has taken the HotelKeycard sponsorship.Brewer Scienceis a global leader inthe development andmanufacturing of specialty materials,integrated processes, and laboratoryscalewafer processing equipment forreliable fabrication of semiconductors,compound semiconductors, advancedmicroelectronic packaging and 3-D ICs,MEMS, sensors, displays, LEDs, andprinted electronics.Watch electronics. for the full program to beannounced soon! Contact Patti HvidhyldVisit http://www.iwlpc.com for more information.at 952-920-7682 or patti@smta.orgregarding the conference. www.iwlpc.comContact Patti Hvidhyld at 952-920-7682 or patti@smta.org with qAdvantest Ranks as TopSemiconductor Test EquipmentSupplier For 25 YearsSemiconductor test equipmentsupplier Advantest Corporation hasearned a place on the VLSIresearchlist of the 10 Best Suppliers for 2013.For the 25th consecutive year, ratingsfrom the world’s leading IDMs, OSATsand fabless companies have securedAdvantest a position on the timehonoredsurvey conducted by theindustry-analyst firm, VLSIresearch Inc.of Santa Clara, CA.The annual customer satisfactionsurvey collects feedback from morethan 98% of the worldwide chip market.Participants are asked to rate equipmentsuppliers among fifteen categoriesbased on three key factors: supplierperformance, customer service, andproduct performance. In total, over70,000 responses were tallied intothe results. The annual VLSIresearchCustomer Satisfaction Survey on ChipAdvantest Ranks as Top Semiconductor Test Equipment SuppSemiconductor test equipment supplier Advantest Corporation haon the VLSIresearch list of the 10 Best Suppliers for 2013. For theyear, ratings from the world’s leading IDMs, OSATs and fabless comsecured Advantest a position on the time-honored survey conductindustry-analyst firm, VLSIresearch Inc. of Santa Clara, CA.The annual customer satisfaction survey collects feedback from mthe worldwide chip market. Participants are asked to rate equipmamong fifteen categories based on three key factors: supplier perfcustomer service, and product performance. In total, over 70,000tallied into the results. The annual VLSIresearch Customer SatisfacChip Making Equipment is the only publicly available opportunitychip manufacturers to provide feedback on their suppliers.Advantest reports that the specific areas in which their customersgreatest degree of satisfaction with the company’s performance in58Chip Scale Review July/August 2013 [ChipScaleReview.com]

Making Equipment is the only publiclyavailable opportunity since 1988 forchip manufacturers to provide feedbackon their suppliers.Advantest reports that the specificareas in which their customers expressedthe greatest degree of satisfaction withthe company’s performance includedtrust in supplier, product performance,quality of results, partnering, andtechnical leadership. ReportedlyAdvantest won the highest rating inthe industry in the categories of trust,partnering, field engineering support,commitment, and support after sales.“Advantest takes pride in the highstandards it sets for its products andservices and we are gratified that ourcommitment to excellence is so highlyrecognized by the world’s leadingsemiconductor manufacturers,” statedHaruo Matsuno, president and CEOof Advantest Corporation. “We aregrateful to our customers for the trust andconfidence they place in our capabilitiesand we remain steadfastly focused on theirsuccess and to delivering the industry’shighest performing test solutions.”Mouser and Advanced ThermalSolutions, Inc. (ATS) Sign GlobalDistribution AgreementAdvanced Thermal Solutions, Inc.(ATS) announced a new global agreementwith Mouser Electronics, Inc. to distributeheat sinks and cooling solutions.Mouser Electronics maintainsa worldwide distributorship fordesign engineers and buyers, with 19global support locations, reportedlyfeaturing the latest semiconductors andelectronic components.The agreement with ATS givesMouser Electronics customers access toa wide range of heat sinks available inthousands of shapes and sizes. “We lookforward to providing thermal solutions toMouser’s customers around the world,”said Sharon Koss, VP of Operations andBusiness Development of ATS.ATS heat sinks are designed for usein many applications including telecom,datacom, LED, automotive, medical,and aerospace. Their maxiFLOWheat sinks feature a low profile spreadfin array and are available withthermal tape, push pin or its patentedmaxiGRIP attachment methodology,which permits attachment to BGAs, flipchips and other hot components on aPCB without needing to drill holes in theboard. Both the spring and frame clip inthe assembly can be removed, allowingthe heat sink to be detached and reattachedwithout damaging the device,surrounding components or PCB.A lot moreof what you need...MORE PERFORMANCEHigh-frequency (>40 GHz) sockets with a variety of materials to meet diverse testingrequirements from Bench Characterization to Fully Automatic Handlers (>500k cycles)delivering what you need.MORE CHOICESIndustry’s widest available DUT interfaces – Spring Probes, Microstrip Contacts and two types ofConductive Elastomers.LESS COSTAll DUT interface materials available in off-the-shelf molded plastic for a fraction of other’smachined housing cost.LESS WAITAries can deliver the exact sockets you need in four weeks or less! So why settle?The Evolution ofInterconnect Innovation...a lot lessof what you don’t!Bristol, PA 19007-6810Tel 215-781-9956 • Fax 215-781-9845Email: info@arieselec.comwww.AriesElec.com7582.indd 15/22/13 10:08 PMChip Scale Review July/August 2013 [ChipScaleReview.com] 59

ATS heat sinks are designed for use in many applications including telecom,datacom, LED, automotive, medical, and aerospace. Their maxiFLOW heat sinksfeature a low profile spread fin array and are available with thermal tape, push pinor its patented maxiGRIP attachment methodology, which permits attachment toBGAs, flip chips and other hot components on a PCB without needing to drill holes inthe board. Both the spring and frame clip in the assembly can be removed, allowingthe heat sink to be detached and re-attached without damaging the device,surrounding components or PCB.Aledia Welcomes New Board MemberAledia WelcomesNew Board MemberAledia, developerof microwire-based3D LED technology,announced that solidstatelighting (SSL)industry veteran Bernhard Stapp, Ph.Dhas joined its board of directors.Stapp brings more than a dozenyears of executive experience in LEDlighting technologies to Aledia, mostrecently in senior management positionsat OSRAM, a global leader in SSLmanufacturing and marketing, wherehe was responsible for the company’sprofessional LED and OLED businessand oversaw launch of the world’s firstOLED lighting products.“Aledia’s technology is, quitesimply, a breakthrough for the entireLED sector,” said Stapp. “It can meetthe industry’s critical requirement forcost-reduction, while using far simplerproduction processes and much lessmaterial than conventional approaches.I am very excited about the opportunityto join this team.”“Bernhard has been a key player atthe heart of the global LED industrysince its inception, and also has anoutstanding technical background,” saidGiorgio Anania, co-founder, presidentand CEO of Aledia “ His uniqueperspective on this industry’s future willbe invaluable as Aledia moves into thenext stage of its evolution.”SV Probe Establishes Repair Centerin ItalySV Probe (“SV”) announced that ithas signed a contract with K314 srl, anelectronics service company in Vimercate,Italy, to perform probe card repairSockets, Contactors & Adaptersfor Prototype Development & Test• Compatible with virtually any footprint• Probe-pin & Elastomer solutions• Pitch range from 0.30mm to 2.54mm• Pin counts up to 2000• Bandwidth to 40GHz• SMT, thru-hole & solderless options• Several socket closure styles available• Custom requirements are welcome• Competitive pricing• Expedited deliveryFor further information visit www.e-tec.comor contact us directly for immediate attentionE-Tec Interconnect Ltd, USA Marketing & SalesE-mail: info-US@E-tec.com, Telephone: +1 408.746.2800(www.e-tec.com)work. Probe cards are essential tools forelectrical testing of semiconductor wafersbefore they are diced, packaged, andassembled in electronic products suchas tablets, smart phones, computers anddigital media players.According to the two companies,this collaboration will not only provideEuropean customers with efficient andtimely repair solutions, but bolster SV’sglobal expansion of support facilities.“The establishment of this repaircenter demonstrates SV’s commitment toour customers in the European region,”explained Karen Lynch, Senior VP ofsales and marketing, SV Probe. “At thesame time, it further strengthens SV’sworldwide infrastructure offering ourcustomers faster and more cost-effectiveprobe card services.”“The K314 team is very pleasedto join SV Probe in supporting theirEuropean clientele.” added CristianaMolina, CEO, K314. “Combining K314’selectronic assembly and design strengthswith SV’s innovative test solutions willprovide our European customers withturnkey solutions to meet their time-tomarketneeds.”imec and GLOBALFOUNDRIESAnnounce Collaborationimec and GLOBALFOUNDRIEShave expanded joint developmentefforts to advance spin-transfer torquemagnetoresistive random accessmemory technology (STT-MRAM)—a promising high-density alternativeto existing memory technologies, likeSRAM and DRAM.“Innovation in next-generationmemory is required to give chipdesigners new options to continue todeliver leading-edge products withhigher performance, lower powerconsumption,and better bandwidth”explained Gregg Bartlett, CTO,GLOBALFOUNDRIES.The first IC manufacturer to join imec’sR&D program on emerging memorytechnologies, GLOBALFOUNDRIES60Chip Scale Review July/August 2013 [ChipScaleReview.com]

completes the value chain of imec’s research platform, which fuelsindustry collaboration from technology up to the system level.“Our unique research environment harnesses the collectiveexpertise and knowledge of the entire value chain, bringingtogether foundries, IDMs, fabless and fablite companies,packaging and assembly companies, and equipment andmaterial suppliers to drive innovation and the development ofnew, competitive products,”said Luc Van den hove, presidentand CEO, imec, of the collaboration.GLOBALFOUNDRIES is joining a team that includesQualcomm and several worldwide equipment suppliers toprovide the complete infrastructure necessary for R&D onSTT-MRAM. Together, imec and the program members aim toexplore the potential of STT-MRAM, including performancebelow 1ns and scalability beyond 10nm for embedded andstandalone applications.“We are elated to intensify our collaboration withGLOBALFOUNDRIES and the other program members onadvanced memory technologies,” Van den hove continued.Bartlett added, “This new partnership with imec will enableclose collaboration with customers, partners, and the suppliercommunity to help reduce the risk in bringing this newmemory technology to market.”Mentor Graphics and Tezzaron Collaborate on 3D ICsMentor Graphics Corp and Tezzaron Semiconductor Corpare teaming up to integrate Mentor’s Calibre® 3DSTACKproduct into Tezzaron’s 3D-IC offerings.Tezzaron works with industry academia and governmentto create advanced 3D-ICs. It offers both wafer and diestacking technology with TSVs, built in self-test and repair(Bi-STAR®) circuitry for continuous error detection andrecovery, and memory devices for both standalone andstacked applications.“Tezzaron specializes in 3D wafer stacking and TSVprocesses,” explained Robert Patti, CTO and VP of designengineering at Tezzaron Semiconductor. “We work withdozens of customers to create custom 3D-ICs for prototypingand commercialization, including recent 3D-ICs in 40 nm and65 nm;the first at these small nodes.”Mentor Graphics’ contribution to the collaboration isit’s Calibre 3DSTACK signoff solution, which reportedlyprovides DRC, LVS, and parasitic extraction (PEX)capabilities. It verifies physical offset, rotation, and scalingat the die interfaces and enables connectivity tracing andextraction of interface parasitic elements needed for multi-dieperformance simulation. Additionally, it supports dies basedon different technologies or process nodes.By integrating these capabilities, the companies expect toprovide fast, automated verification of die-to-die interactions in2.5D and 3D stacked die configurations by verifying individualChip Scale Review July/August 2013 [ChipScaleReview.com]Chip Scale Ad'13-Final.indd 1616/3/2013 12:00:09 PM

dies in the usual manner, while verifyingdie-to-die interfaces in a separateprocedure with specialized automationfeatures. The two companies plan toextend their collaboration to includedevelopment of solutions for the siliconphotonics market.“Over the last two years, therelationship between Mentor Graphicsand Tezzaron has really blossomedas we work together to bring volume3D-IC applications to the IC industrymainstream,” said Michael Buehler-Garcia, senior director of marketingfor Calibre Design Solutions at MentorGraphics. “Combining flexibility, easeof-use,and interoperability provides thehighest value for our mutual customers,and will help make the adoption of 3D-ICdesign techniques successful.”“By collaborating with MentorGraphics, we can offer our mutualcustomers a comprehensive designverification solution. It creates the highestvalue for them with the least disruption totheir existing flows, ” added Robert Patti.XILINX Achieves PCI ExpressCompliance Across 28nmProgrammable Device FamilyXilinx announced that its AllProgrammable 7 series FPGAs andZynq®-7000 All Programmable SoCsare now in full compliance with PCIExpress® and were added to the PCI-SIG integrator's list. All of Xilinx's28nm devices passed rigorous electrical,protocol and interoperability tests atthe latest PCI-SIG event held on April15, 2013. This marked PCI-SIG's firstofficial PCI Express Gen3 complianceand interoperability testing since theintroduction of the specification.According to the company, thisachievement is significant becauseit will allow designers to meet highsystem bandwidth and programmablesystems integration requirementsneeded in a variety of markets,including communications, storage, andserver applications. The device familiesare said to enable design productivityindustrial and automotive applications.HELIOS Program a Success: GoodNews for EuropeAs a result of the success of therecently completed HELIOS program,CEA-Leti reports that Europe ispositioned to design and manufacturevolume silicon photonics device design.Launched by the Europeancommission in 2008, HELIOS focusedon developing essential building blockslike efficient optical sources (siliconbasedand heterogeneous integration ofIII-V on silicon), integrated lasers, highspeedmodulators, and photo-detectors.The €8.5M, 20-member projectcombined and packaged these buildingblocks to demonstrate complex functionsthat address a variety of industry needs.It developed a complete design andfabrication supply chain for integrating aphotonic layer with a CMOS circuit usingmicroelectronics fabrication processes.Most recently, Leti’s HELIOS programreportedly demonstrated a completedesign flow, integrating both siliconphotonics device design and electronic/photonic system design in an EDAcompatibleframework.“It is strategically importantfor Europe to maintain photonicchip-design and chip-integratingfunctions to compete with othercountries and to encourageinnovation by Europeanmicroelectronics companies,”said Laurent Malier, CEO, Leti.“HELIOS’ success in creatingthe essential building blocks forintegrating photonics with CMOScircuits and making the processavailable to a variety of usersunderscores the key role that broadEuropean technological cooperationplays in a very competitive globalbusiness environment.”Thomans Skordas, head of theEC’s photonics unit, said HELIOSshows a variety of potentialapplications for silicon photonics, suchas applications in data communications.“The technology roadmap ofsilicon photonics becomes clearernow. Europe will have to move fastto become competitive in this newfield,” said Skordas. “Strategies for theindustrialization of silicon photonicsare currently being discussed in thecontext of Horizon 2020—the EU’s newframework program for research andinnovation for 2014-2020.”According to Leti, due to the costadvantages of integrating photonic andelectronic functions on the same chip,silicon photonics is key to developingoptical telecommunications or foroptical interconnects in microelectroniccircuits. The company also reports thatCMOS photonics may lead to low-costsolutions for a range of applicationssuch as optical communications,optical interconnections betweensemiconductor chips and circuit boards,optical signal processing, opticalsensing, and biological applications.SPTS Ships 1000TH DRIE ModuleSemiconductor equipment and62Chip Scale Review July/August 2013 [ChipScaleReview.com]

the precision and control that is required for ever more sensitive and functionaldevices. We continue to develop our DRIE technology for future generations ofMEMS and related chip-sets.”SPTS was the original licensee of the Bosch process, a patented process fundamentalto the DRIE, and shipped its first commercial system in 1995. Since that time, DRIEprocess capability has continuously improved to the point where etch rates inproduction exceed 30µm/min, aspect ratios can exceed 90:1 and device features of

include glass interposers, panels ofany shape and size, and standard andreconstituted wafers from 300mm tonext-generation 450mm.What does this mean for RudolphTechnologies? Paul F. McLaughlin,chairman and chief executive officerof the company noted that this isgood news, calling it a “milestone.”He also discussed how the sale ofthe JetStep system is “validating thecommercialization of our innovative 2Xstepper total lithography.”“Advanced packaging is in the earlystages of dynamic growth and is acritical driver of mobile connectivityand, therefore, a critical driver forRudolph. Consumer device demandis driving the need for new packagingtechnologies for 2.5D and 3D multidieintegration. These and otheradvanced wafer-level packages now indevelopment at leading IDMs, foundriesand OSATs require a more sophisticatedstepper lithography solution.,” notedMcLaughlin, “The Rudolph JetStep2X Solution is positioned not only fortoday’s leading edge packages, butalso for future advanced packagingtechnology needs.”Tonka Bay Acquires CorwilTechnology Corp.Tonka Bay Equity Partners LLCannounced the acquisition of CorwilTechnology Corporation, whichwas founded in 1990 as a providerof assembly and test services forintegrated circuits (ICs). The companysubsequently grew to become a strategicmanufacturing partner in high-costof-failureand high-reliability marketsegments, including medical devices,and military and aerospace industries.In a recapitalization transaction,Tonka Bay partnered with Corwil’scurrent management, includingcofounders Rob Corrao and FinnWilhelmsen. The aquisition is TonkaBay’s fifth investment in its thirdfund, which had $150M in capitalunder management.“Corwil is poised for significantgrowth,” said Matt Bergeron, presidentand board member. “We have anunparalleled assembly and test offeringand our customers truly see us asmanufacturing partners.”Stephen Soderling, Principalof Tonka Bay and Corwil Boardmember, explained that the companyholds a defendable niche in onshoreassembly and test marketplace,thanks to unique capabilities and deepcustomer relationships.11-13 February 2014Big Island of HawaiiThe Pan Pacific Microelectronics Symposium focuses on critical market, managementand technology issues in the design, packaging, interconnection, assembly and test ofelectronics micro-systems and advanced technology products.Digital Health;Facts, Fiction &Future!Featured Keynote SpeakersTime Bombs inElectronic & PhotonicSystems!Green TechnologyIlluminates theFutureMatthew HudesDeloitte & ToucheNihal SinnaduraiATTACwww.smta.org/panpacRicky Shi Wei Lee, Ph.D.Hong Kong University64Chip Scale Review July/August 2013 [ChipScaleReview.com]

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ECTC column with DV edits 060613 p. 1generation packages. On Wednesdayevening, the 2013 ECTC PlenarySession on “Packaging ChallengesAcross the Wireless Market” was alsowell-received with over 200 attendees.ECTC 2013 Confirms Traction GainsLou Nicholls of Amkor Technologyin 2.5D ECTC and 3D Integration 2013 Confirms Traction Gains in 2.5D and 3D Integrationbrought together panelists from Nokia,The Chip 63rd Scale annual Review Electronic StaffQualcomm, RFMD, Amkor, andComponents and TechnologySEMCO, and all agreed we need toConference (ECTC) The 63convened rd annual at Electronic the Components and Technology Conference overcome the (ECTC) thermal challenges convened in theCosmopolitan Hotel and Casino on Mayat the Cosmopolitan Hotel and ECTC Casino Technical on Team: May Wolfgang 28 – Sauter, June IBM, 1, 2013. handheld By all market. measures, The Cosmopolitan the event, of28 – June 1, 2013. By all measures,the event, considered considered by by many many to to be be the63rdpremierECTC GeneralinternationalChair, David McCann,conference on Las IC Vegas packaging, was a new components,venue for ECTCGLOBALFOUNDRIES, Jr. Past General Chair, Beth that turned out to be an excellent fit andthe premier and microelectronic international conference systems technology, Keser, Qualcomm was Technologies, an outstanding Program Chair, Alan success and lived up to its stellarwe look forward to returning in 2016.”on IC reputation. packaging, components, and Huffman, RTI International, Assistant Program Chairmicroelectronic It’s systems clear that technology, 2.5D and Comments 3D research from took Wolfgang center Sauter, stage at the Highlights conference of the and Conference is gainingwas an traction. outstanding Perhaps success Dave and lived McCann, up 63rd 63 rd ECTC ECTC General Sponsorship Chair Chair, summed Over it 330 up best registrants when he attended said, 16to its stellar reputation.This year's conference was a huge“At the conference, we saw the discussion turning from the promise Professional and inevitability Development of 2.5D Courses andIt’s clear that 2.5D and 3D research success. From abstract submissions,3D, to solving the challengestook center stage at the conference conference of implementing attendance, 2.5D industry and support 3D, including (PDCs) to low kick cost off the interposer conference.The PDC program included four newand is technologies, gaining traction. memory Perhaps Dave supply, and and exhibit the need interest for bare - ECTC die 2013 stack probe, microbump reliability,courses plus two significantly updatedMcCann, power 63rd distribution ECTC Sponsorship through TSVs, set and new driving records cost in just down about and every yield up to enable implementation.”offerings this year. The five themesChair, summed Although it up best highly when acclaimed he metric for we the know quality how of to its measure. 377 original were technical Reliability, presentations Modeling, (up TSV &said, “At from the 347 conference, in 2012), we the saw event the has Semiconductor steadily increased packaging the continues size of its 3D, exhibition Polymers, area and as Electrical. well. The Thediscussion turning from the promise and to receive more and more recognitionTechnology Corner exhibition area was “sold out” again this year most as it popular grew to PDC 95 was exhibitors “TSV andinevitability of 2.5D and 3D, to solving as the solution to solving tomorrow'sfrom 81 last year (a 17% increase)! Both figures are new ECTC records. Other Enabling Technologies for 3Dthe challenges of implementing 2.5D bandwidth, cost and yield problems.As a strong sign that theand 3D, including low cost interposer We semiconductor have successfully market transitioned segment has IC Integration,” fully recovered led by from John the Lau ofIndustrial Technology Research Institute.technologies, 2009 economic memory downturn, supply, and the from conference concepts has with grown process-by-process from 550 attendees in 2009, to more thanAt least 25% of the 36 technicalthe need 1,300 for attendees bare die in stack 2013, probe, representing capability, 31 to states being and a critical 26 countries. factor in This sessions year’s dealt attendance with various also aspects set a of 3Dmicrobump new reliability, record – power surpassing distribution the 50 the anniversary IC architecture ECTC and design held with in 2000. fullypackaging technology. The most popularthrough TSVs, and driving cost down integrated capabilities and solutions.technical session was Session 7 titledand yield >“Interposers,” followed closely by SessionAlthough highly acclaimed for the Comments from Beth Keser, 63rd 1 entitled “3D Assembly and Reliability.”quality of its 377 original technical ECTC Program ChairThe annual ECTC Luncheon onpresentations Comments (up from 347 from in 2012), Wolfgang the 2013 Sauter, was an 63 outstanding rd ECTC year General for the ChairWednesday featured a stimulatingevent has steadily increased the size of its technical program of ECTC. In additionkeynote speech by Dr. Chris Welty,exhibition area as This well. year's The Technology conference to was the 36 a technical huge success. sessions From and five abstract Research submissions, Scientist at conferenceIBM T.J. WatsonCorner attendance, exhibition area industry was “sold support out” andposterexhibitsessions,interestthere-wereECTCfive2013Tuesdayset new records in just about everyagain this year as it grew to 95 exhibitors and evening sessions that were verymetric we know how to measure. Semiconductor packaging continues to receive more and morefrom 81 last year (a 17% increase)! Both well received. On Tuesday, over 200recognition as the solution to solvingfigures are new ECTC records.people attended tomorrow's the Special bandwidth, Session cost and yield problems. We haveAs successfully a strong sign transitioned that the from on concepts “The Role with of Wafer process-by-process Foundries in capability, to being a criticalsemiconductor factor in the market IC architecture segment and Next design Generation with fully Packaging,” integrated hosted capabilities and solutions.has fully recovered from the 2009 by Sam Karikalan of Broadcomeconomic downturn, the conference Corporation. Presentations by TSMC,Comments from Beth Keser, 63 rd ECTC Program Chairhas grown from 550 attendees in 2009, SMIC, GLOBALFOUNDRIES,to more than 1,300 attendees in 2013, IBM, and UMC kicked-off ECTC’srepresenting 312013 states was and 26 an countries. outstanding technical year for program. the technical The message program was of Dr. ECTC. Chris Welty, In Research addition Scientist to at the the IBM 36 T.J.This year’s technical attendance sessions also and set a five new poster collaboration sessions, between there wafer were foundries, five Tuesday Watson and Research evening Center, sessions gave the keynote that to overrecord – surpassing the 50th anniversary OSATs, and the materials and tooling 1000 attendees on the development of Watson, thewere very well received. On Tuesday, over 200 people attendedIBMthecomputerSpecialthat defeatedSessionthe bestonplayers“Theon theECTC held in 2000.suppliers is key to the success of next-Role of Wafer Foundries in Next Generation Packaging,” hosted by American Sam Karikalan game show Jeopardy. of BroadcomCorporation. Presentations by TSMC, SMIC, GLOBALFOUNDRIES, IBM, and UMC kicked-66 Chip Scale Review July/August 2013 [ChipScaleReview.com]

Research Center, on “EngineeringChallenges in Building Watson.” Hedescribed the analysis factors developedfor “cognitive computing” software andthe challenges of hypothesis scoringof text-based knowledge as was usedfor the IBM computer, named Watson,that defeated the best players of theAmerican game show, Jeopardy.Five poster sessions held in theTechnology Corner exhibit area,including one student poster session,covered 121 different interactivepresentations (up from 95 last year).Five special sessions addressed 1)papers. In addition, a number ofindividuals were honored by the IEEECPMT Society for their service tothe industry. Receiving the highesthonor, the 2013 Field Award, wasJohn H. Lau for contributions to theliterature in advanced solder materials,manufacturing for highly reliableelectronic products, and education inadvanced packaging.Teledyne Microelectronic Technologies, HarryKellzi, Sharon FletcherAt the Gala Reception, Prof CP Wong, LawrenceMichaels, Prof James J.Q. LuInteractive presentationsthe role of wafer foundries in nextgenerationpackaging, 2) LED for solidstatelighting, 3) packaging challengesacross the wireless market supplychain, 4) advanced low-loss dielectricmaterials for high frequency andhigh bandwidth applications, and 5)modeling and simulation challenges in3D systems.A number of ECTC and CPMTawards were announced for the best2012 session, poster, and studentTechnology Corner ExhibitsFrom the Technology Cornerexhibition area.NTK Technologies Inc. Hirohito (Hugh) Hashimoto,Mariel Stoops, Bill Moody, Kim Newman, RonMolnarSTATS ChipPAC, Patrick Tang, Heather GaronzikIMAT, Michael Danylchuk, Yoshi OnoProf. John H. Lau of ITRI, Taiwan (at center) wasthe recipient of 2013 IEEE CPMT Award, also in thepicture (second from the right) is Prof. Ricky Lee,President of IEEE CPMT society.Corwil Technology Corp, Brian Riley, Matt HansenMark your Calendar for the 64thECTCPlanning is already underway for the64th ECTC, which will be held May27 – 30, 2014 at the Walt Disney WorldSwan and Dolphin Hotel in Lake BuenaVista, FL. The first Call-for-Papershas been issued and abstracts must bereceived by October 14, 2013.Chip Scale Review July/August 2013 [ChipScaleReview.com]67

Product NewsEV Group Rolls Out Next-GenerationAutomated Resist ProcessingSystemEVG®120 Automated Resist Processing SystemSemiconductor equipment supplierEV Group (EVG) introduced the latestversion of its EVG®120 automatedresist processing system at SEMICONSingapore 2013. This next-generationtool features enhancements that wereoriginally developed for 300mmequipment platforms such as newerrobots and handling systems for fasterthroughput. The result is a 200mmtool targeted for the intricacies ofhandling microelectromechanicalsystem (MEMS) wafers in high-volumemanufacturing (HVM).Dr. Thomas Glinsner, head ofproduct management for EV Group,credits 15 years of experience in theprocess for these tool enhancements.“In independent surveys, our customersconsistently attribute the highest scoresto EVG's lithography equipment, andwe've listened to their feedback to createa more optimized system,” he said.In addition to MEMS, the EVG120system reportedly supports coatingand developing applications foradvanced packaging and compoundsemiconductors. The tool can beconfigured with combined spin andspray coating modules–a unique featurethat is said to maximize productivityand optimizes cost of ownership (CoO).The automated resist processingsystem features a newrobot with dual arms forfast wafer swapping andadditional processingchambers. It runs the sameEVG CIM Frameworksoftware as the company’shigh-end XT Frame systemsand offers full softwareintegration with SECS/GEM standards. Twocustomizable wet processingbowls are complementedby 10 stacked modules forvapor prime, soft and hardbake, and chill processes.Like its predecessor, theEVG120 system canaccommodate wafers up to 200 mmin diameter.Coventor’s SEMulator3D 2013Addresses 3D Fab Era RequirementsExpanding the value of virtualfabrication to the semiconductorEcosystem by reducing learning cyclesand subsequently cost, Coventor®, Inc.announced that its SEMulator3D® 2013software platform is now available.Targeting semiconductor device andMEMS design, this platform reportedlybrings physical accuracy and predictivemodeling capabilities to processdevelopment and integration.This simulation software platformcomes at time when semiconductorcompanies are grappling with thecomplexities of integrated 3D front-endof-line(FEOL) manufacturing processessuch as Tri-Gate and High-k/MetalGate logic, as well as advanced 3Dmemory technologies. Fabless designteams also face challenges migratingtheir intellectual property (IP) into thesenew technologies. SEMulator3D 2013reportedly responds to such evolvingrequirements with a virtual fabricationplatform that makes it possible forfoundry and fabless development teamsto effectively collaborate at the physicalprocess level.According to the company, the coreof this platform is a physics-drivenmodeling paradigm for addressingphysical process behavior that makesvirtual fabrication more predictive andprovides new opportunities for replacingactual silicon learning cycles with faster,less costly virtual cycles. In addition,virtual metrology innovations andthe automation of virtual experimentsenable process developers to performvirtual fabrication operations in hours ordays instead of the months required foractual silicon learning cycles.“With new silicon architecturesramping quickly, IBM is introducingnew manufacturing technologies thatwill keep us on the cutting edge of chipmakingfor server microprocessors,systems-on-chips and specialtysilicon for consumer applications,”said Gary Patton, Vice President,IBM Semiconductor Research &Development Center. He credits toolssuch as Coventor's virtual fabricationplatform with speeding up end-to-endtechnology development in 22nm andbeyond, enabling a faster time to marketfor customers.Hesse Mechatronics Offers NewService for Bondjet BJ939Hesse Mechatronics, Inc. introducesapplication development, prototypingand pre-production services on anewly installed BONDJET BJ939Fully Automatic Heavy Wire Bonderin addition to demonstrations. Theyare offering these services at thecompany’s west coast demonstrationand applications lab, located atlong-time company manufacturer’srepresentative Chalman Technologies inAnaheim, California. Additionally, at itsdemonstration labs in Tempe, AZ andClinton, MA, the company will offerexpanded services for heavy wire andribbon along with thin wire applications.68Chip Scale Review July/August 2013 [ChipScaleReview.com]

www.iwlpc.com10 th anniversarySAN JOSE, CALIFORNIAN O V E M B E R 5 - 7, 2 01 310th Annual International Wafer-Level Packaging ConferenceExhibitor OpportunitiesNovember 5-7, 2013DoubleTree Hotel, San Jose, CAIWLPC Conference: November 5-7 IWLPC Exhibit: November 6-7WHAT IS THE CoST To ExHIbIT?• One tabletop booth space for $1,250• Additional $50 for electricity in boothSPoNSorSHIP oPPorTuNITIESCommand the attention of the IC Packaging Industry!Several levels of Sponsorships are available:WHAT IS INCLuDED• Full Pipe and Draped Booths, 8’x10’ and8’x8’ Sizes Available (See Floor Plan Online)• Lunch and Coffee Breaks Each day• Exhibitor Cocktail Reception• Two 10th Anniversary Celebration Tickets• Attendee List• Show Directory Listing• Company Sign• IWLPC Proceedings on Flash Drive• One Conference Pass (a $650 value)SMTASurface Mount Technology Associationandare proud to present the event of the year for buyers,specifiers and producers of chip-scale and wafer-levelpackaging equipment, materials and services.NoWAvAILAbLEPremium SPonSorShiP LeveLSPlatinum Sponsor$4,400 SoLd out!Gold Sponsor$2,750 SoLd out!Silver Sponsor$1,650 one Left!10 th YeAr AnniverSArY SPonSor $5,200AdditionAL oPPortunitieSFlash Drive Sponsor$2,000 SoLd out!Keynote Sponsor $2,000Luggage Tag Sponsor $1,750Hotel Key Card Sponsor $1,750Lunch Sponsorship $1,500WiFi Sponsor $1,000Refreshment Sponsor $900 one Left!Show Directory Advertising range from $200-$400 per AdFor exhibitor/sponsor sales, please contact:Kim Newman at Chip Scale Review: 408-429-8585 or info@chipscalereview.comRon Molnar at Chip Scale Review: 480-215-2654 or rmolnar@chipscalereview.comFor general inFormation, please contact:Seana Wall at SMTA: 952-920-7682 or seana@smta.orgChip Scale Review July/August 2013 [ChipScaleReview.com]69

Hesse Mechatronics -BONDJET BJ939 Heavy Wire BonderAccording to Hesse Mechatronics,the BONDJET BJ939 heavy wirebonder is used for power electronicsand automotive device applications.The tool can now work with heavy wireand ribbon on a single platform. Thenew application bonds both aluminum,gold, silver, or ribbon wire. It can workwith 3 mil to 20 milwire and .075mmby .075 mm to .3mm by 2 mm on thesame machine. Hesse also reports thebonder can place up to 3 wires a second,can complete and integrated pull test,and comes with a large travel table.Additionally, the bonderfeatures E-Box opticaltool adjustment. ProcessintegratedQuality Control(PiQC) is said tomeasures true bond qualityin real time and the inaircut feature eliminatesmarking on die. [www.hesse-mechatronics.com]Essemtec DebutsHigh Speed Jetter atSEMICON WestFor the first time in NorthAmerica, Essemtec, a Swissmanufacturer of productionsystems for electronicassembly and packaging,will unveil its Scorpion highspeedjetter at SEMICONWest this July.The Scorpion is afully automatic jettingsystem in dispensingtechnology that is saidto improve overallequipment efficiency.Absolute throughputis maximized withpiezo jetting valvesthat enable the jettingof fluids over a widerange of viscositywith speeds of upto 800 Hz. Materialuse is reduced due toa fluid box with capacity less than 50nanoliters, thereby reducing waste.Thefluid box is connected to the jet valvewithout tubing, which helps to minimizemessy cleaning and maintenanceoperations are minimized. eDIS softwareprovides context sensitive help. Pointand touch features are intuitive to learn,and programming of dots, lines orvarious shapes is supported along withCAD import.The Scorpion can be equipped withup to four valves or pumps, includingjet valves, Archimedian screw valves,Essemtec - Scorpion High Speed Jettertime pressure valves and slider valvesto accommodate applications such asencapsulation, dam-and-fill, underfill,LED cavity, conductive adhesive,solder paste, phosphor silicon cavity filland more.Dow Corning and SÜSS MicroTecReport New Temporary BondingSolution for 2.5D and 3D ICPackagingThe semiconductor industry’s marchtoward broader 3D IC integrationmarked an important milestone with thereport of an advanced new temporarybonding solution for 3D Through SiliconVia (TSV) semiconductor packaging.The breakthrough was unveiled duringECTC 2013, in a paper co-authoredby Dow Corning and SÜSS MicroTec,a leading supplier of semiconductorprocessing equipment, and presented byRanjith John, materials development &integration engineer at Dow Corning.The paper, titled Low Cost, RoomTemperature Debondable Spin onTemporary Bonding Solution: A KeyEnabler for 2.5D/3D IC Packaging,details the development of a bi-layerspin-on temporary bonding solutionthat eliminates the need for specializedequipment for wafer pretreatment toenable bonding or wafer post-treatmentfor debonding. The solution is said toimprove the throughput of the temporarybonding/debonding process to helplower the total cost of ownership (CoO).“This advance underscores why DowCorning values collaborative innovation.Combining our advanced siliconeexpertise with SÜSS MicroTec’sknowledgeable leadership in processingequipment, we were able to develop atemporary bonding solution that met allcritical performance criteria for TSVfabrication processes. Importantly, thespin coat-bond-debond process wedetailed in our co-authored paper takesless than 15 minutes, with room forfurther improvement,” said John. “Basedon these results, we are confident that70Chip Scale Review July/August 2013 [ChipScaleReview.com]

important milestone with the report of an advanced new temporary bonding solution for3D Through Silicon Via (TSV) semiconductor packaging. The breakthrough wasunveiled during ECTC 2013, in a paper co-authored by Dow Corning and SÜSSMicroTec, a leading supplier of semiconductor processing equipment, and presented byRanjith John, materials development & integration engineer at Dow Corning.The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary BondingSolution: A Key Enabler for 2.5D/3D IC Packaging, details the development of a bilayerspin-on temporary bonding solution that eliminates the need for specializedequipment for wafer pretreatment to enable bonding or wafer post-treatment fordebonding. The solution is said to improve the throughput of the temporarybonding/debonding process to help lower the total cost of ownership (CoO).“This advance underscores why Dow Corning values collaborative innovation.Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeableleadership in processing equipment, we were able to develop a temporary bondingsolution that met all critical performance criteria for TSV fabrication processes.Importantly, the spin coat-bond-debond process we detailed in our co-authored papertakes less than 15 minutes, with room for further improvement,” said John. “Based onthese results, we are confident that this technology contributes an important step towardhigh-volume manufacturing of 2.5D and 3D IC stacking.”Dow Corning and SÜSS MicroTec - Temporary BondingSolution for 2.5D and 3D IC Packagingthis technology contributes an importantstep toward high-volume manufacturingof 2.5D and 3D IC stacking.”Cost-effective temporary bondingsolutions are a key enabler for 2.5and 3D IC technology. However, inorder to be competitive, candidatetemporary bonding solutions mustdeliver a uniformly thickadhesive coat, and be ableto withstand the mechanical,thermal and chemical processesof TSV fabrication. In addition,they must subsequently debondthe active and carrier waferswithout damaging the high-valuefabricated devices.Through their collaboration,Dow Corning and SÜSSMicroTec were able to developa temporary bonding solutionthat met all of these applicationrequirements. Comprising an adhesiveand release layer, Dow Corning’ssilicon-based material is optimized forsimple processing with a bi-layer spincoating and bonding process. Combinedwith SÜSS MicroTec equipment,the total solution offers the benefitsof simple bonding using standardmanufacturing methods. In their copublishedpaper, the collaborators reporta solution exhibiting a total thicknessvariation of less than 2 µm for spincoatedfilms on either 200 or 300mmwafers. The bonding material exhibitedstrong chemical stability when exposedto phosphoric acid, nitric acid, organicsolvents and other chemicals familiarto TSV fabrication. In addition, thebonding solution and paired wafersshowed good thermal stability whenexposed to the 300°C temperaturescommon to the TSV process.Assembléon to present its HybridSolution at SEMICON WestFor many the existence of PCBassembly machines in the backendmarket is still unknown or consideredstrange. Rapid technology changes andminiaturization have caused an equallyChip Scale Review July/August 2013 [ChipScaleReview.com]71

ADVERTISER-INDEXAmicra Microtechnologies www.amicra.com ............... 28&29Amkor Technology Inc. www.amkor.com ........................... 1Applied Materials www.amat.com ..................................... IBCAries Electronics www.arieselec.com .................................. 59ASE Group www.aseglobal.com ............................................. 7BESI www.besi.com .............................................................. 2&3Brewer Science www.brewerscience.com ........................... 57Contech Solutions www.contechsolutions.com ................. 61DL Technology www.dltechnology.com ............................... 35Emulation Technology www.emulation.com ..................... 49Essai www.essai.com ............................................................ IFCE-tec Interconnect www.e-tec.com .................................... 60EV Group www.evgroup.com ................................................ 51Assembléon - Hybrid SolutionAccording to Assembléon, its Hybrid system has a unique proposition in the PCBHCD Corp www.hcdcorp.com ............................................... 56assembly market, as it is the only system incorporating a single/pick single/place concept.Honeywell www.honeywell-radlo.com .................................. 9The advantage of such a system is that it can be fully optimized, monitored andcontrolled during the complete pick, dip and place cycle. The incorporated low-forceIMAT Inc. www.imatinc.com ................................................. 33closed-loop placement process reportedly ensures that even the thinnest devices areIndium Corporation www.indium.us/E033 ........................ 41placed accurately and its incorporated impact control takes care that no impact forces areapplied during placement. Assembléon claims it is therefore the only system that has veryIronwood Electronics www.ironwoodelectronics.com ..... 17high production yields with an established placement defect rate lower than 1defect/million placements (< 1 dpm). Besides the placement quality, it brings theIWLPC www.iwlpc.com .......................................................... 69traditional ingredients of the PCB assembly, such as application flexibility, very highJF Microtechnology www.jftech.com.my .......................... 11speed, accuracy, efficiency and cost control, along into the back-end market.KYEC www.kyec.com ............................................................. 32The company claims this cross-over platform combines high speed passive placementwith high speed flip chip placement with reported accuracies at less than 10µm at anyKyzen Corp www.kyzen.com ................................................. 4location on the PCB at any angle. The controllable placement Z-axis adapts its placementMicro Control www.microcontrol.com ................................ 47height search algorithms for different heights, optimizing its placement force for 2.5Dmounting, package on package (PoP) or embedded passive and active deviceNanium www.nanium.com .................................................... 63applications.Nordson Asymtek www.advancedjetting.com ...................... 21Plastronics www.h-pins.com ............................................... 45Quartet Mechanics www.quartetmechanics.com .............. 53Quik-Pak www.icproto.com .................................................. 42Rudolph Technologies www.rudolphtech.com .................. OBCSEMI www.semiexpos.org ..................................................... 65Sensata Technologies www.qinex.com ............................. 15Sierra Electronics www.tapesplice.com .............................. 25SMTA International www.smta.org/smtai/vip ...................... 71SMTA Pan Pac www.smta.org/panpac ................................. 64STATS ChipPAC www.statschippac.com/ewlb ..................... 37SUSS MicroTec www.suss.com ........................................... 5Syagrus Systems www.syagrussystems.com ...................... 55Advertising inquiries: ads@chipscalereview.comSpace Close for Sept Oct is August 5.rapid shift of specialized equipment, normally present intraditional PCB assembly, to move into backend packagingindustry. As a result, Assembléon, supplier of PCB assemblytools, has announced it will attend SEMICON West 2013 andSEMICON Taiwan 2013 to present its hybrid solutions to thesemiconductor manufacturing community.According to Assembléon, its Hybrid system has a uniqueproposition in the PCB assembly market, as it is the onlysystem incorporating a single/pick single/place concept.The advantage of such a system is that it can be fullyoptimized, monitored and controlled during the completepick, dip and place cycle. The incorporated low-force closedloopplacement process reportedly ensures that even thethinnest devices are placed accurately and its incorporatedimpact control takes care that no impact forces are appliedduring placement. Assembléon claims it is therefore theonly system that has very high production yields with anestablished placement defect rate lower than 1 defect/millionplacements (< 1 dpm). Besides the placement quality, itbrings the traditional ingredients of the PCB assembly, suchas application flexibility, very high speed, accuracy, efficiencyand cost control, along into the back-end market.The company claims this cross-over platform combineshigh speed passive placement with high speed flip chipplacement with reported accuracies at less than 10µm at anylocation on the PCB at any angle. The controllable placementZ-axis adapts its placement height search algorithms fordifferent heights, optimizing its placement force for 2.5Dmounting, package on package (PoP) or embedded passiveand active device applications.During the SEMICON West Exhibition, Assembléonrepresentatives will discuss the concepts, advantages, currentreferences, and technology roadmap of its hybrid equipment.72Chip Scale Review July/August 2013 [ChipScaleReview.com]

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4Chip Scale Review March/April 2012 [ChipScaleReview.com]