wideband rf signal digitising for high purity spectral analysis

WIDEBAND RF SIGNAL DIGITISING FOR HIGH PURITY SPECTRALANALYSISYuri Artyukh, Ivars Bilinskis, Eugene Boole, Alexander Rybakov, Vadim VedinInstitute of Electronics and Computer Science, University of Latvia,14 Dzerbenes Str., Riga LV-1006, LATVIA. bilinski@edi.lvABSTRACTAn advanced RF signal digitiser based on the DASPapproach is discussed. In comparison with theconventional RF signal digitising, it is characterised notonly by a wide (669 MHz) bandwidth but it also makes itpossible to obtain high purity spectrograms.1. INTRODUCTIONWideband RF signal digitising is a quite demanding task.There are two most often used typical approaches to RFsignal digitising. The first approach is based on direct RFsignal digitising at a very high (up to GHz) samplingrate, using for that wideband high-speed A/D converters.While it leads to obtaining a broad alias-free frequencybandwidth, the technical realization of such digitising ishighly complicated. In addition, the high-speed A/Dconverters usually are limited in resolution down to 6-8bits.The second well-known approach is based on RFdown-conversion with the following digitisation of theconverted signal at a relatively low sampling rate. Thisapproach is simpler in realization and provides betterresolution but it is applicable only for a limitedfrequency band.An alternative approach is suggested and discussedin this paper. It is based on usage of so called DigitalAlias-free Signal Processing (DASP) technology [1].This technology takes into account one important fact:the most of present-day A/D converters have an inputbandwidth much wider than the sampling rate. So inconventional application the maximum availablesampling rate limits the range of digital alias-free signalpresentation down to the Nyquist frequency. The DASPtechnology avoids this limitation for many importantapplications and allows utilising the actual potential ofA/D converters almost fully.Generally application of DASP is advantageous asit leads to obtaining both the wide bandwidth and thesimplicity in realization. However the DASP technologyis specific. To achieve the essential alias eliminationeffect, signal sample values are taken at predeterminednon-uniformly spaced time instants placed on a regulartiming grid. In this case the available frequencybandwidth is defined only by the step of this grid andcan reach GHz range. On the other hand the samplingintervals typically contain a relatively large number ofthese steps so that minimum sampling interval is not lessthan the A/D converter allows. Successful elimination ofaliasing is achieved by using this kind of digitisingtogether with the usage of proper signal processingalgorithms. The upper frequency of input signalsdigitised in accordance with the DASP technology, in awide application area, can substantially exceed the meansampling rate. In addition, designs of this kind ofdigitisers are relatively simple forasmuch as thecommonly used electronic devices can be employed.A few models of the DASP digitisers have beenearlier developed and made [2-4]. In combination withspecial DASP algorithms, they provide for both widebandwidth and simplicity of the hardware. For example,the DASP digitiser of “DASP-Lab System” [2] isapplicable in 1.2 GHz bandwidth while the meansampling rate is only 80 MSPS. An advanced DASPdigitiser is discussed in this paper. In comparison withthe previous models, it is characterised not only by awide (669 MHz) bandwidth but it also makes it possibleto obtain high purity spectrograms.2. THE PROBLEM TO BE SOLVEDThe Spurious-Free Dynamic Range (SFDR) is a vitaldynamic characteristic of digitisers to be used for widedynamic range and high frequency applications.By definition the SFRD is the ratio between themaximum signal component and the largest distortioncomponent in signal spectrum. Generally the maximumavailable SFDR of a digitiser is defined by dynamiccharacteristics of A/D converter being used for signaldigitising. However usually there are some additionallimitations for SFDR caused by peculiarities of the A/Dconverter application in digitiser design. Specifically,one of the possible reasons of additional SFDR limitingis a periodically repeated offset of the actual samplinginstants relative to the points of strictly uniform timinggrid. This offset causes spurious spectral components,which additionally narrow the SFDR of the digitisers.Simulation of signal sampling with a slight periodicoffset shows that even as small as picosecond offsetproduces spurious components that essentially decreasethe SFRD down to 50-60 dB in 500-700 MHz bandwidth(Figure 1).For the conventional (uniform) signal samplingsuch offset can be caused by a periodic spuriousmodulation of the clock source (such as by a switchingpower supply). However a careful PCB design andnarrow-band filtering the reference frequency can

significantly suppress such modulation (down to parts ofps) to reach a widest available SFDR.Figure 1. FFT for 533 MHz sine-wave signal sampled at1600 MHz rate; the sampling instants are displaced fromthe regular location by ±2 ps with 100 MHz periodicityAs for DASP digitisers, basically the offset can becaused by an inaccuracy at generation of the samplingpulses at the required non-uniformly spaced timeinstants.Reaching required picosecond accuracy ofsampling pulse generation is a very serious problem fordesigning the wideband DASP digitisers as the circuitsfor the sampling pulses generation are relativelycomplicated. Specifically, the most widespread approachto the non-uniform sampling pulse generation is basedon usage of digitally controllable delay lines that isdriven by a low-jitter clock source. Theoretically in thisway it is possible to spot the sampling instants in anydesired places with accuracy limited only by the delayline performance. Seeing that currently top-leveldigitally controllable delay lines offer the increment ofpicosecond range, the GHz range of equivalent samplingrate for DASP is quite practicable.In the previous models of DASP digitisers we usedfor sampling pulse generation the high-performanceprogrammable delay chips MC100EP195 from “ONSemiconductor”. This chip provides about 10 psincrement in 10 ns delay range, making it well suited todriving by the conventionally used 100 MHz clocks.Generally these digitiser models have provided thedesign frequency bandwidth but, unfortunately, theycould not support the required picosecond accuracy ofsampling pulse generation. This was, first of all, due tothe too large differential non-linearity of the delay chipsand temperature drifts of the delay range. For thesereasons, SFDR of the previous DASP digitiser modelstypically does not exceed 35-40 dBFS.To provide much better spectral purity (in terms ofSFDR), a new advanced version of DASP digitisers hasbeen designed and made. This version is subsequentlyreferred to as DIGITISER.3. DESIGN OF THE DIGITISERAs for some previous modes of DASP digitisers, thehigh-performance 12-bit A/D converter AD9433 from“Analog Devices” has been chosen for DIGITISERdesign. This converter provides 700 MHz analogbandwidth at sampling rate up to 125 MSPS. Thus, in itsconventional applications the alias-free analogbandwidth does not exceed Nyquist’s frequency 62.25MHz. The DIGITISER should be able to utilize the widebandwidth of this A/D converter almost fully.Structurally the designed DIGITISER (Figure 2)fully conforms to the patented solution [5] where thesampling pulses are formed through clock frequencycontrollable dividing and controllable delaying of thedivided pulses. A pseudo-random number generator(PRG) provides digitally such control.Generally the patented solution tolerates differentrelations between the mentioned digital (clock frequencydividing) and analog (pulse delaying) operations. In ourcase an emphasis was made on digital operations atmuch higher clock frequency (669.3266 MHz instead ofpreviously used 100 MHz). It was supposed that in thiscase a very accurate low-jitter timing grid with 1.494 nsstep could be supported exclusively by digital means.SAMPLING PULSE FORMER669.3 800 MHzClockPRGDivider by 9 to 16(MC100EP016)Digital controlShaperInputFine tuningDelay block0/625 0/747 psADC(AD9433)FIFOFigure 2. Schematic block diagram of the DIGITISERThe 1.494 ns step itself can support alias-freeanalog bandwidth up to 335 MHz approx. However toreach wider (>500 MHz) bandwidth for DASPapplications the step size must be at least halved. To dothat, an additional one-step controllable delay block isapplied. By definition this block should be extremeprecise. To provide required precision, it was designedon the basis of an adjustable with 33 ps/step delay line(VDJ1010 from ELMEC TECHNOLOGY), a specialmeans for fine delay tuning with picosecond precision,and high-speed multiplexer. Such structural solution ofthe sampling pulse former provides the following designcharacteristics of the sampling process:• Real sampling rate 53.546 MSPS• Equivalent sampling rate 1338.653 MSPS• Alias-free analog bandwidth to 669.326 MHzGenerally it was supposed that in this case the periodicoffset of sampling instants would not exceed a fewpicoseconds under temperature-variable operatingconditions, resulting in the SFDR not less than 50 dB infull input signal bandwidth.The mentioned structural solution of theDIGITIZER has been embodied as a single compact(185x162mm) board that can be connected to PC via itsparallel port supporting EPP mode of data exchanging(Figure 3). The board may be housed in a standardenclosure and powered via an external AC/DC adapter.

In the process of design a special attention has beenfocused on very careful PCB design to optimize theprinted connections between components most critical tointerference and avoid both a distortion of the input RFsignal and a ringing of high frequency digital signals.missing uniform sample values with the estimated signalvalues leads to significant improvement of accuracyespecially if the process is repeated in an iterative way.Let us consider this method for signal spectral analysisand waveform reconstruction in some detail.4.1.1. Introduction of thresholdsAt first, the spectral estimates are calculated on the basisof DFT as follows:2a π , (1)N∑ − 1( 0)( fk) = x(ti)cos(2 fkti)N i = 02b π , (2)N∑ − 1( 0)( fk) = x(ti)sin(2 fkti)N i = 0A(+ )]220)( fk) = [ a(0)( fk)] [ b(0)( f . (3)kFigure 3. Design of the DigitizerIt is important that the most of digitiser’s digitaloperations performed at low frequencies (such ascontrolling the process of sampling pulse generation,data buffering, interfacing with PC) were implementedin a specialized PLD chip. In this way it was possible notonly to simplify design but also achieve the highreliability in operation.4. EXPERIMENTAL EVALUATION OFPERFORMANCE CHARACTERISTICSEvidently the SFDR for the DIGITISER cannot be widerthan for the A/D converter being used (in our case –AD9433 from “Analog Devices”). However theproducer of this device specifies its dynamicperformance only up to 350 MHz input signalfrequencies. In particular, the converter can provideSFDR about 67 dBFS at 250 MHz and about 60 dBFS at350 MHz. Presumably the SFRD at the higherfrequencies can be considerably less. Hereby thepracticable SFDR of the DIGITIZER within the range50-60 dBFS can be considered as close to the maximumpossible. The actual dynamic characteristics of theDIGITIZER have been evaluated experimentally.4.1. Iterative approach to spectrum analysis andwaveform reconstructionLet’s note once more that specialized DASP algorithmsshould be used to process non-uniformly sampledsignals. The most popular method for processing suchsignals is so-called zero padding method.According to this method, zeroes are used forreplacing the missing signal sample values. Howeverthat actually leads to introduction of significant errorsobserved in spectrograms as high background noise. Inthe considered case, an iterative approach to spectralanalysis and waveform reconstruction was used. It isbased on substitution of zeroes at the places of theThe index in the round brackets (in this case (0)) showsthe ordering number of iteration. The estimate (3) is usedto define some initial threshold for further iterativeoperations.In general, the iterative approach to spectrumanalysis and waveform reconstruction is based on theidea that a priori information has to be used as fully aspossible. Zero padding is a crude method and itsapplication leads to introduction of substantial errors.When even approximate estimates of the signal samplevalues are used for replacement of those zeroes, thementioned errors could be reduced dramatically.Therefore it is essential how the signal value estimationis organized. A step-by-step approach to that taskdecision has been used. The more powerful signalcomponents are estimated first; then the components thatare less powerful and so on.Such an approach makes sense as the absoluteparameter estimation errors tend to be equal underspecific signal to noise ratio. Therefore the relativeerrors are smaller for the more powerful components. Torealize this approach, threshold levels are introduced.The signal components above the threshold are estimatedfirst. Then the inverse DFT is carried out and the missingsample values are substituted by the correspondinginstantaneous values of the roughly reconstructedwaveform. Then the obtained signal sample valuesequence is used for repeated DFT. Now it providesspectral estimates significantly more accurate. At thenext step, the threshold level is lowered and thecomponents above it are estimated again. The process iscontinued in this way for a given number of cycles.The first threshold is set up at the levelU0= µ(0)max ( A(0)( fk)), 0 < µ(0)< 1 (4)kwhere the initial relative threshold often is chosen at thelevel µ (0) = (0.7…0.9). The signal components exceedingthe given threshold A (0) (f k ) > U 0 are estimated at thecorresponding frequencies.All estimated signal components with power belowthe first threshold level are excluded from thespectrogram in the following way:

Y( n+1)⎪⎧Y(n)[ k][ k]= ⎨⎪⎩0ififYY( n)( n)[ k]> U[ k]≤ Unn(21)and they are processed in the same way in the nextiteration cycle: waveform reconstruction is follow as theinverse FFT:M∑ − 12πik1jMy( n + 1)[ i]= Y(n + 1)[ k]e , i = 0, M −1(22)M k = 0and the initial samples are built in the reconstructedr r rvector of waveform q = xy ( ( n + 1)) .4.2. Some experimental resultsTo evaluate the DIGITISER actual performanceevaluation software has been developed. This softwarewas based on the mentioned DASP algorithm andprovides processing of 1K samples (accumulated in realtime during 19.124 µs) in each analysis cycle, resultingboth in spectrum of input signal and its waveform.In the case of spectral analysis the software detectsand estimate up to a few tens of spectral components ofthe signal (in order of decreasing their power) withcalculated frequency resolution about a few Hz. Next issignal waveform reconstruction from these components.As a result the waveform and spectrum of the inputsignal are displayed in graphical form after eachanalyzing cycle. One can use zoom to see any selectedarea of the general views in more details. Figure 4illustrates these capabilities in the case of analyzing apulse sequence.alternatively by a high-performance digitizingoscilloscope (TDS 3052B) providing 5GHz/s real timesampling rate and 500 MHz bandwidth.Figures 5-6 show the analysis results for two-tonetest signals. Spectrums of these signals are similar to theprevious one in sense of spurious component absence,noise floor and the expected SFDR. Figure 5 directlyshows that even signal component so small as –54 dBFScan be clearly detected on the background of noises.As for evaluation of other dynamic characteristics,they were very close to the standard specifications of theA/D converter.Figure 5. Two-tone signal analysis when the tones aresimilar in amplitudeFigure 4. 100 MHz pulse sequence analyzingAs in the other cases, the waveform is shown in digits ofA/D conversion vs. time in µs; the spectrum is shown indBFS vs. frequency in MHz.The spectrum clearly shows all expected harmoniccomponents of the signal, including two aliasings from700 and 800 MHz harmonic components that exceed669.3 MHz Nyquist’s limit; spurious components in factare not detected. The observed level of the noise flow(about -60 dBFS) suggests the actual SFDR estimationas better than 60 dBFS. As for the reconstructedwaveform, it is fully defined by the spectrum and wellconforms to the view of the same signal obtainedFigure 6. Two-tone signal analysis when the tones differin amplitude considerably5. SUMMARY OF SPECIFICATIONSInput rangeAnalog bandwidthResolutionDASP sampling mode:Real sampling rateEquivalent sampling rateAlias-free analog bandwidthSFDRPeriodic sampling mode:Sampling rateAlias-free analog bandwidth2 V p-p0.1-700 MHz12 bits53.546 MSPS1338.653 MSPS0.1-669.3 MHz> 55 dBFS74.37 MSPS0.1-37.1 MHz

Trigger (programmable)FIFO sizeInterfacingConnectors:Input – SMAExternal trigger – BNCEPP Port – DB25Board dimensionEnclosure dimensionsPower supply6. CONCLUSIONexternal or internal32K Samplesvia parallel PC port185X162mm185x192x55mm7.5V/1.1AThe considered DIGITISER under DASP provides highspectral purity that is near to the achievable by the usedhigh-performance 12-bit A/D converter itself. However,it should be emphasized, that this high dynamicperformance has been achieved in alias-free way in thewhole frequency range up to 669 MHz. We are notaware of any other available technique of RF signaldigitising and digital analysing that permits to achievecomparable dynamic performance by using the indicatedtype of A/D converter.7. REFERENCES[1] I. Bilinskis, I. Mednieks. Introduction to Digital Alias-freeSignal Processing. Institute of Electronics and ComputerScience, Riga, “Dasp Lab Ltd.”, London 2001, 65.p.[2] Yu. Artyukh, I. Bilinskis, M. Greitans, V. Vedin. “SignalDigitizing and Recording in the DASP-Lab System”.Proceeding of the 1997 International Workshop onSampling Theory and Application, June, 1997, Aveiro,Portugal, p.357-360.[3] Yu. Artyukh, I. Bilinskis, V. Vedin. “Hardware core of theFamily of Digital RF Signal PC-based Analyzers”.Proceeding of the 1999 International Workshop onSampling Theory and Application, August 11-14, 1999,Loen, Norway, p.177-179.[4] Yu. Artyukh, V. Bespal’ko, E. Boole. “Analog signaldigitizer adapted to experimental evaluation of DASPalgorithms”. Proceeding of the 8 th Biennial ElectronicsConference, October 6-9, 2002, Tallinn, Estonia, p. 231-232.[5] J. Artjuhs, I. Bilinskis. “Method and apparatus for aliassuppressed digitizing of high frequency analog signal”.European patent application 02001248.8 Published23.07.2003, Bulletin 2003/30.