A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP ...

ecause of the existence of direct conducting path.No matter how to enhance the noise immunity bypreventing the dynamic nodes from floating or by raising thesource voltage of pull-down nMOS transistors, thenoise-tolerant mechanisms all are not under protection;therefore, the noise-tolerant mechanism may possibly bedestroyed by the noise interference. Consequently, all theseexisting techniques must still pay expensive design penalty interms of speed, power, and area to achieve the noise tolerantgoal. Especially as the requirement of noise tolerance isincreased along with the progress of process technology, thedesign overhead will further increase dramatically.IV. THE PROPOSED ISOLATED NOISE-TOLERANTDYNAMIC CIRCUIT TECHNIQUE(a)(b)Fig. 3. Proposed isolated noise-tolerant technique: (a) generalcircuit schematic, (b) buffer schematicA. Characteristics of the Proposed INT TechniqueFig. 3(a) is the proposed isolated noise-tolerant (INT)technique and it concludes a noise isolated mechanism and anoriginal pull-down network. Fig. 3 (b) is proposed buffercircuit, MNT1 (NT-transistor) provides a path to transmit noiseto raise the source voltage and enhances the noise immunity.MNT2 is utilized to precharge node V G to make MNT1conduct and turned off to protect the noise-tolerant mechanismfrom destroyed in the evaluation phase; MNT3 can provide adischarge path for maintaining function correction; MNT4 isutilized to prevent the occurrence of voltage overshooting. Theweak feedback keeper can assist in preventing the dynamicnode from floating. The main difference between the proposedINT technique and conventional noise-tolerant techniques isthat the noise-tolerant mechanism in the INT circuits can beprotected from being destroyed even if the noise input isenormous.B. Operation of the Proposed Noise-Tolerant TechniqueThe operation of the proposed circuits can be separatedinto pre-charge phase and evaluation phase. To simplify theexplanation of operation in the proposed noise-tolerant circuit,we take the dynamic buffer circuit as example. The sameoperation principle can be popularized to all other dynamiccircuits.1) Pre-charge Phase:In the pre-charge phase, the clock signal CLK is low andthe inverse clock signal CLKb is high. The dynamic node X ischarged to logic high and the output node OUT is logic low. Inthis phase, Fig.4(a) is a simple illustration of the buffer circuit,node V G in the buffer circuit is precharged to high to makeMNT1 conduct because MNT2 is turned on by CLKb andMNT3 is turned off by OUT. The conduction of MNT1 isessential for raising the source voltage of MN1 to enhance thenoise-tolerance in evaluation phase.2) Evaluation Phase:In the evaluation phase, CLK is switched to high and CLKb isswitched to low. The dynamic node X is floating because MP1is turned off by CLK; therefore, the noise-isolatednoise-tolerant mechanism must be activated in this phase toprevent the floating node X from being disturbed by the noise.As the input A is logic “0”, the noise-tolerant mechanism isactivated by MNT2 and MNT3. Fig. 4(c) is a simpleillustration, MNT2 will be turned off as CLKb switches to lowand MNT3 will also be turned off since the input A is logic “0”;therefore, node V G is isolated and latched in logic high tomaintain the conduction of MNT1. As noise interrupts thecircuit as illustrated in Fig.4 (b), the noise charge can bedrained away immediately through MNT1 to node V S and thesource voltage of MN1 will be raised by the disturbing signal.Hence, the noise-tolerant ability can be enhanced. Because thenoise-tolerant ability is enhanced by raising the source voltageof MN1; therefore, it is important to maintain the conductingsituation of MNT1 to achieve good noise immunity. In theevaluation phase of proposed circuit, the conduction situationof MNT1 can be hold because the node V G is isolated.Therefore, the noise-tolerant mechanism can be protected andthe noise-tolerant ability will not degrade even underenormous noise interference. As the input A is logic “1”, thenode X will be pull-down to logic low and OUT is logic high.As a result, the charge in the node V G can be discharged to turnoff MNT1 to ensure the correctness of function in normalmode, as illustrated in Fig. 4(d).(a)(c)(d)Fig. 4. The operation of the proposed noise-tolerant circuit:(a) operate in pre-charge phase (b) in evaluation phase withnoise interference operates in evaluation phase. (c) normaloperation in evaluation phase as input signal is “0” (d)normal operation in evaluation phase as input signal is “1”C. Noise-Isolated Noise-Tolerant PropertyThe gate voltage of noise-tolerant transistor(NT-transistor) dominates the capability of noise-tolerance.The degradation of gate voltage results in the descent ofnoise-tolerant ability. In the conventional noise-toleranttechniques, the gate voltage of noise-tolerant transistor usually(b)296