Design and Implementation of Digital Echo Cancellation On ...

Design and Implementation of Digital Echo Cancellation On-Channel Repeater in DVB-T/H NetworksYue Zhang 1 , KoK-Keong Loo 1 , John Cosmas 1 , Maurice Bard 2 , Jeff Gledhill 31 School of Engineering and Design, Brunel University, Uxbridge, UB8 3PH, UK2 Broadreach Systems, Devon, UK3 Videsco, UKEmail: Yue.Zhang@brunel.ac.ukAbstractThis paper is to investigate the hardware design andimplementation of digital echo cancellation on-channelrepeater (DECOCR) in DVB-T/H networks. There is aneed for high isolation between transmitter and receiverantennas for on-channel repeater (OCR) to minimizefeedback from the antenna coupling and to keep the systemstable. Therefore, the adaptive echo canceller is to removethe echoes between the transmitter and receiver antennas inOCR to minimize the coupling. The design andimplementation of DECOCR is based on the algorithm ofecho cancellation by channel equalization. The paper willinvestigate the design and implementation of DECOCRbased on digital signal processing (DSP) in FPGA device.The most important issues considered are to get shortestsystem process delay, highest SNR output and highest echorejection rate. The laboratory measurement results showthat the presented repeater can get up to 29dB echocancellation and about 1us process delay with robuststability. The work in this paper was supported by theEuropean Commission IST project – PLUTO (PhysicalLayer DVB Transmission Optimization)to get high SNR baseband DVB-T/H signals. The mostimportant item in DECOCR is the adaptive echoequalization filter. The DECOCR contains the shortestdelay complex equalization filter with a novel structure.The proposed equalizer can cancel the echoes in thereceived multipath signals effectively to minimize thecoupling loop interference and get better MER (ModulationError Rate). Furthermore, the latency of the whole processis surprisingly short when employing a carefully designedequalization filter scheme. Furthermore, the channelestimation with Constant Amplitude Zero Autocorrelation(CAZAC) sequences is also implemented in FPGA. Thechannel estimation implementation is based on 1024 pointsFFT and IFFT. The estimation process is average over from4 to 32 FFT frames. The performance of channel estimationin hardware is evaluated by different channels based on themean error between actual channel and estimated channelwith different signal noise ratio (SNR) level.KeywordsOn-Channel Repeater, Echo Canceller, DECOCR, FIR,FPGA DSP CAZAC DVB-T/H1. INTRODUCTIONTo extend the coverage of the DVB-T/H networks,repeaters were proposed for rural and suburbanenvironments [1]. The main purpose of an on-channelrepeater (OCR) is to enlarge the coverage of DVB-T/H[2][3] network. An on-channel repeater receives a signalfrom a distant transmitter and re-broadcasts an amplifiedversion of it on the same frequency in single frequencynetwork (SFN). COFDM systems such as DVB-T/H arespecifically designed to work in the presence of strongechoes [4][5]. This opens the possibility of implementingan OCR which works by receiving the signal off air,amplifying it and then retransmitting it on the samefrequency [6-8]. This paper will investigate the design andimplementation of DECOCR based on digital signalprocessing (DSP) in FPGA device. The hardware structureis based on figure1. According to Figure 1, DECOCRcontains low noise DDC, DUC and Low pass filter (LPF)Figure 1. Hardware structure of digital echo cancellation onchannel repeaterThe performance of DECOCR is evaluated under variouslaboratory conditions prior to field test. The laboratorytestbed is based on Spirent channel emulator, DVB-T/Hmodulator and ETX. According to the measurement results,as for a single echo, the DECOCR can get echo rejectionrate up to 25dB. When combined with the real-time channelestimation part, the DECOCR can remove the echo up to

29dB. Meanwhile, the latency of the whole signalprocessing is only 520ns.As for the channel estimation with CAZAC sequences, theabsolute error rate between estimated channel in hardwareand actual channel versus SNR is provided which showingthe channel estimation performance as part of theDECOCR. According to the results, the mean error ofchannel estimation for RA channel is 1.6e-3 at SNR 24dBand the mean error for TU channel is 9.827e-4 at SNR24dB.This paper is organized as follows: Section 2 discusses thecoupling interference in the on channel repeater for DVB-T/H systems and the system design for DEOCR. Section 3shows the hardware design for the OCR. Section 4 presentsthe discussions of the measurement results performed inthis study. Section 5 is the conclusion according to thedesign and measurement results.2. THE ON-CHANNEL REPEATER AND THECOUPLING INTERFERENCEIn this section, the coupling interference of the OCR inDVB-T/H systems will be investigated. Furthermore, themodel design of OCR aim to remove the couplinginterference is presented in the section as well.2.1 The Coupling Interference in On Channel RepeaterFigure 2 illustrates the principle of an OCR and the case ofcoupling loop. The receiving antenna of the OCR receivessignal from the main transmitter with a level of P. Thisreceived signal is filtered in order to remove all theunwanted out-of-band signals. The filtering may include afrequency transposition around an Intermediate Frequency(IF). The signal is then amplified with a gain of G, and it isretransmitted on the same frequency.Figure 3. Frequency selectivity due to the coupling loop effectin Rician channelThe effect of coupling interference in the frequency domainis as shown in Figure 3 as measured by TDF. Even if theecho remains in the guard interval, the C/N thresholdrequired by the receiver to demodulate the received signalis thus increased and the coverage area is reduced. If thedelay introduced by the OCR is larger than the guardinterval, the signal may even not be demodulated.2.2 The Model Design for Digital Echo CancellationOn-Channel RepeaterThe OCR is an additional transmitter in a SFN DVBnetwork [9][10]. Its output can be modeled as a first highlevel echo that depends on the actual amplifier gain usedfollowed by a delay cropped or residual cluster of rays. Inorder to cancel the echo produced by the OCR, weproposed a short delay on channel repeater with echocancellation. The basic model design is shown in Figure 4.TrainingSequence orReferenceRxChannel EstimatorTapsFIR FilterUnwantedFeedbackTxComment [J1]: Give full name.Low NoiseAmplifier-∑S∑TrainingSequenceInsertionPowerAmplifierFigure 2. The coupling interference in on channel repeaterDue to the finite isolation between the transmitting andreceiving antennas and the reflections on the nearbyenvironment, the receiving antenna receives severaldelayed replicas from the repeater's own transmit antenna.These signals correspond to the transmitted signal modifiedby the transfer function, C, which includes a strongattenuation corresponding to the isolation between therepeater antennas. This leads to the coupling loopinterference.Figure 4. The model for digital echo cancellation on channelrepeaterThe model is based on an open-loop channel estimator. Alow power training sequence such as CAZAC sequence isburied in the transmitted OFDM signal for the unwantedchannel estimation based on the correlation principal. Themain echo cancellation design issues are the maximumallowable processing delay, the sampling rate used forhardware implementation, the number of filter taps andhow it affects the performance. The maximum allowableprocessing delay of the echo canceller is selected to bebelow 30% of the guard interval duration. This means thatfor 2K mode with 7 us guard interval, the maximum

allowable delay is around 2 us. This figure impacts theperformance of the echo canceller because it sets a limit onthe maximum number of taps used by the FIR filter.3. HARDWARE CIRCUITS SYSTEM DESIGNFOR THE ON-CHANNEL REPEATERn this section, the hardware circuit system design ofDECOCR is presented. The hardware system design isbased on Figure 1. The whole system includes receivingsubsystem, echo equalization and re-transmitter subsystem.The hardware implementation is based on the Xilinx FPGAVirtex 4.3.1 Receiving Subsystem Circuit DesignThe receiving subsystem circuit design is based on Figure 5.The receiving subsystem includes low noise amplifier(LNA), IF down converter, ADC, DDC and low pass antialiasfilter (LPF). The LNA is used to boost the weakreceived signal to an appropriate power level for IF downconversion without adding much noise. ADL5530 is usedas the LNA. The ADL5530 provided by Analog Device is abroadband fixed-gain, linear amplifier that operates atfrequencies up to 1000 Mhz. The gain and noise figure ofthe LNA are important to determine the noise figure of thereceiving subsystem. In this application, ADL5530 cansupport a gain of stable 16.5dB over frequency with a noisefigure of 3dB.However, LPF is delay component. Therefore, LPF is theoptional component for the subsystem.The performance of the receiving subsystem is measuredby its ability to select a desired channel in the presence ofstrong adjacent channels, selectivity, and by its minimumdetectable signal and sensitivity.3.2 Echo Cancellation Subsystem Circuit DesignIn this subsystem, the main part is the echo cancellationfilter as shown in Figure 6. The equalizer in the system iscomposed of a novel parallel finite impulse response (FIR)filter with auto load coefficients.Figure 6. Echo Cancellation subsystemThe equalizer is used to compensate for various forms oflinear distortions in the received signal. The lineardistortions are caused by multipath distortion and couplingloop interference. In order to shorten the process delay forthe echo cancellation filter in the whole system, a kind ofparallel structure of the FIR filter is presented. There aretwo parts for the filter. One is the parallel equalizer filterwith dynamic coefficients. The other is the coefficientsauto-load control circuit. The parallel FIR filter is transposeform FIR filter which have several advantages over directform structures for high speed and parallel implementationof FIR filter.Figure 5. Structure of receiving subsystemThe down converter consists of a mixer and local oscillator.The down converter converts the desired RF signal to afixed IF band with sufficient signal level. The frequency ofthe IF that involves a trade-off can be chosen by thedesigner. A high IF leads to better image signal rejectionand a low IF need greater suppression of nearby interferes.AD6645 is used for ADC. The maximum clock for ADC is105Mhz. After the ADC, the digital IF signal is downconvertedto near baseband signal. Finally, the nearbaseband signal is converted to baseband signal by DDC.The LPF is the remove the alias from the baseband signals.Figure 7. Direct-form FIRAs for the traditional direct form FIR filter shown in Figure7, the multiplications can be performed in parallel, howeverthe accumulation of the products requires at least log 2 40adder delays. Therefore, the delay limits the maximumthroughput of a parallel implementation. But the transposeformFIR filter structure has several advantages for parallelimplementation. The worst case propagation path betweendelay elements consists of one bus, one multiplier and oneadder. The transpose-form FIR filter is also advantageous

for arithmetically efficient implementation. For fixedcoefficients and dynamic coefficients, the transpose formFIR filter can get the same performance of direct form FIR.Through simulations and practice, transpose-form adaptiveequalizer filter has shown to work with a short delay. In thesystem, the equalizer filter accepts 14 bit data in and 18 bitcoefficients for 40 taps at sample rate 25Mhz. At the outputof the filter, the result is rounded to 28 bits.6050Direct-form FIRFIR complierDistributed arithmetic FIRTranspose-form FIR40Samples (Delay)30201000 5 10 15 20 25 30 35 40 45 50TapsFigure 8. Delay analysis for different FIR filterFrom Figure 8, the delay of the transpose-form FIR isshortest delay FIR compared with other FIRs. When thesystem has 40 taps, the novel transpose-form FIR only gets4 samples delay; it’s about 160 ns. As for the distributedarithmetic FIR, the delay is 13 samples at 40 taps. As forthe traditional direct-form FIR, the delay is 43 samples at40 taps. As for the FIR complier in Xilinx FPGA, the delayis 44 samples at 40 taps.The coefficients auto-load control circuit is to write theadaptive coefficients into the equalizer FIR. Thecoefficients must be written into equalizer FIR in a timedelayedmanner so that the coefficient at tap n and time mwill be used to calculate a new partial sum at position n andtime m. The running FIR coefficients and updatecoefficients are located in different memory. When the loadflag is set by the channel estimation circuit, the updatecoefficients will transfer to the running FIR coefficientsmemory. The most important is that the transfer processcannot halt the equalizer running. After the testing, thetransfer process is adaptive for the equalization process.3.3 Re-transmitter Subsystem Circuit DesignThe re-transmitting subsystem design is based on Figure 9.The re-transmitting subsystem includes DUC (digital upconverter),DAC (digital analog converter), IF upconverter,high power amplifier (HPA) and channel filter.DUC is to convert the baseband signal to IF band and.Figure 9. Re-transmitter SubsystemThen the IF signal is fed into DAC. AD9772 is used forDAC and it can work up to 105MHz. The AD9772 is asingle-supply, oversampling, 14-bit digital-to-analogconverter optimized for baseband or IF waveformreconstruction applications requiring exceptional dynamicrange. Thus the IF signals are up-converted to the RF bandthat exactly the same frequency as the input RF signal ofthe DECOCR. Because there are harmonic components atthe output of the DAC, these components must be removedat the IF stage. A band-pass filter (BPF) can be used forremoving the unwanted signal. After IF up-converter, anHPA is used for amplifying the up-converted RF signal.After HPA, a channel filter is used for removal of adjacentchannel in the re-transmitted signal. The channel filter usedin the DECOCR must provide proper filtering to meet theRF emission mask specified by the licensed spectrum.4. MEASUREMNT RESULTSThe performance of the designed DECOCR was evaluatedvia simulations and laboratory tests. The performance ofDECOCR is evaluated under various laboratory conditionsprior to field trial. The laboratory set-up is based on Figure10. From the figure, the laboratory set-up can be dividedinto four sections such as transmitter, channel emulator,DECOCR and receiver.Figure 10. Laboratory set-upThe transmitter is the MOD-1000 DVB-T/H modulatorfrom Teamcast. The modulator IF signals are at RF UHFband through the up-converter. The channel emulator is the

Spirent wideband channel emulator. It can model UHFchannel according COST 207 RA, TU, BU and HTchannels. After the noise combiner, the UHF signals will befed into the DECOCR. The repeater will send the couplingsignals back into the input of the repeater after the echocancellation. The output signal quality from DECOCR wasmeasured with ETX and spectrum analyzer.4.1 Measurement Results for Channel EstimationThere are two different channels to evaluate theperformance of the channel estimator in the on channelrepeater. One is the three taps FIR channel, the other is theTU12 and RA6 according to COST207 [11].Figure 12 Estimated channel impulse response (CIR) for thethree taps channel profileThe channel estimation result in the on channel repeater isin Figure 12. From the figure 12, the delay between theestimated taps is 160ns. It means the channel estimationworks well. The estimator can estimate the correctly delay.As for the amplitude, the estimated taps varies from 0.49 to0.12. It means there is some noise in the estimation of theamplitude of the channel. Furthermore, there are some sideimpulse responses beside the main impulse response. Theseside responses are regarded as the noise for the channelestimation. Therefore, it is very important to take theaverage of a number of the channel estimation frames.The three taps FIR channel profile is based on Table I. Theactual channel impulse response (CIR) is shown in figure11. From figure 11, the delay between the each taps is160ns and the amplitude of the taps varies from 0.5 to 0.2.TABLE IPOWER DELAY PROFILE OF 3 TAPSTAPSRelative delay (us)Fading/relativelinear0 0 0.51 0.2 0.32 0.4 0.20.50.45Mean Error10 -210 -3SNR (dB)TU 1024FFTRA 1024FFTRelative power0.40.350.30.250.20.150.10.0500 5 10 15 20 25 30 35delay(taps)Figure 11 Actual channel impulse response (CIR) for the threetaps channel profile5 10 15 20 25 30Figure 13 The absolute error rate of estimated channel andactual channel versus SNR of CAZAC sequence by average offour framesThe Figure 13 is the result for the average of four channelestimation frames in TU12 channel and RA6 channel.According to Figure 13, the channel estimation works wellat SNR of CAZAC sequences from 10dB to 30dB.4.2 Measurement Results for Echo CancellationThe integration measurement is based on the real timechannel estimation. The power level of the feedback loop iscontrolled by the attenuator. The setup configuration isshown in figure 10.The attenuator is changed from 0 dB to 11dB as shown inTable II. According to the different power level of thefeedback coupling, the on channel repeater can get thedifferent echo cancellation rate based on the real timechannel estimator.TABLE IIATTENUATION FOR THE FEEDBACKRUNSAttenuation (dB)1 02 13 24 35 46 67 8

8 109 11As shown in Figure 13, there are three echoes in the outputof the repeater without echo canceller. The couplinginterference causes the three echoes. The main echo is theecho at 1.20us with -8.6dB power. The other two echoes at2.40us and 3.60 us are the recursive feedback of the mainecho. According to figure 14, the on channel repeater gets27dB echo cancellation with 0 dB attenuation feedback.The main echo is cancelled to -35.1dB and the two minorechoes disappear. It means the channel estimator cancorrectly get the channel state information. And echocancellation FIR filter can suppress the echo properlyaccording to the real time channel estimator.Figure 15 the Attenuation of Feedback Level V.S. EchoCancellation RateTherefore, the attenuation vs. echo cancellation rate isshown in Figure 15. From figure 15, the OCR works wellwith the real time channel estimation (RTCE). When thefeedback level is changed from 0dB to 11dB, the onchannel repeater can get the echo cancellation rate up to29dB.Figure 13 the Output CIR of the Repeater 0dB Attenuation ofthe Feedback Level without Echo CancellationFigure 14 the Output CIR of the Repeater 0dB Attenuation ofthe Feedback Level with Echo Cancellation5. CONCLUSIONSIt is very difficult to provide full coverage to the public interrestrial broadcasting. Because of the technical challengesand cost constraints, it is not possible to deployconventional signal distribution to transmitting stations. Inthese cases, the on channel repeater is the only viablesolution. This paper presented the implementation of digitalecho cancellation on channel repeater in FPGA. Thehardware design includes the transceiver subsystem,channel estimator and echo cancellation subsystems. Thispaper also presents a short delay adaptive filter design toachieve the short process delay for the whole hardwaresystem. The paper also proposes a hardware design ofchannel estimation with CAZAC sequences averaging byIIR filter in the on channel repeater. Furthermore, thepaper also provides the measurement results of theperformance analysis for the hardware design of the digitalecho cancellation on channel repeater. The performance ofDECOCR is evaluated under various laboratory conditionsprior to field test. According to the measurement results,the DECOCR can eliminate the coupling loop echo up to29dB combined with the real time channel estimationaverage. Meanwhile, the whole processing delay is only520ns.ACKNOWLEDGEMENTThe work presented in this paper was supported by theEuropean Commission IST project PLUTO [12]. Theauthors would like to express special gratitude all thePLUTO project partners for their valuable contributions tothe research.

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