Design and technology of DEPFET pixel sensors for ... - MPG HLL

1Design and technology of DEPFET pixel sensors for linearcollider applicationsR.H. Richter a* , L. Andricek a , P. Fischer b , K. Heinzinger c , P. Lechner c , G. Lutz a ,I.Peric d , M. Reiche e , G. Schaller a , M. Schnecke a , F. Schopper a , H. Soltau c , L. Strüder a ,J. Treis a , M. Trimpl d , J. Ulrici d , N. Wermes da MPI Halbleiterlabor Munich, Germanyb University of Mannheim, Germanyc PNSensor gGmbH Munich, Germanyd University of Bonn, Germanye MPI für Mikrostrukturphysik Halle, GermanyAbstractThe performance requirements of vertex detectors for future linear collider experiments is very challenging, especially for thedetector’s innermost sensor layers. The DEPleted Field Effect Transistor (DEPFET), combining detector and amplifieroperation, is capable to meet these requirements. A silicon technology is presented which allows production of large sensorarrays consisting of linear DEPFET detector structures. The envisaged pixel array offers low noise and low power operation.To ensure a high radiation length a thinning technology based on direct wafer bonding is proposed.Keywords: Active pixel detector;DEPFET;Low noise operation;Vertex detector;Linear collider1. IntroductionActive pixel detectors play a growing role in highenergy and astrophysics experiments. Futureexperiments, e.g. TESLA (Tera Electron VoltEnergy Superconducting Linear Accelerator) [1] andXEUS (X-Ray Evolving Universe SpectroscopyMission) [2], will need large area pixel detectors withvery challenging requirements. In astrophysics, thespatial resolution of the detector is less crucial thanthe energy resolution, because the degree of spatialprecision is limited more by the Wolter X-raytelescopes than by the silicon sensors. Therequirements in high energy physics are oftenopposite.———* Corresponding author. Tel.: +49-89-83940043; fax: +49-89-83940011; e-mail: rar@hll.mpg.de.

2Especially for the inner layer of the TESLA vertexdetector, a lot of partially contradictionary demandshave to be addressed. In order to meet the requiredresolution of primary and secondary vertices, theinnermost detector layer has to be placed at a radiusof 15mm from the interaction point. The pixeldetector at this place has to provide a spatialresolution of less than 5µm. The high occupancy,caused by the beamstrahlung, has to be suppressed bya very fast readout cycle of about 50MHz. To reducemultiple scattering, the material introduced in thedetector must be minimized. This means that no extramaterial for cooling pipes etc. is allowed and,additionally, the sensor substrates must be thinned to~50µm thickness. This results in a reduced signalcharge compared to that generated in standard silicondetectors, where the depletion layer extensions are ofthe order of 500µm. In summary, the ideal vertexdetector for TESLA should fulfill the competingboundary conditions simultaneously: High positionresolution should be achieved with small signalamplitudes, i.e. with thin detectors. Simultaneously,the operation must be fast, e.g. 20ns processing timewith low power dissipation in an environment of asignificant radiation level.The DEPleted Field Effect Transistor structure,abbreviated DEPFET, is a monolithic device which isintegrated onto a high ohmic fully depletable detectorsubstrate [3]. The device is one proposal for adetector design that is consistent to a large extentwith all of the above requirements [4]. While thesystem aspects and the readout concept are discussedin [5], this paper proposes a technology for theproduction of large area DEPFET arrays. Thedifferent operation modes of the device are evaluatedby process and device simulations. A thinningprocedure compatible to the DEPFET process and themodule concept is discussed.2. DEPFET operation principlesThe DEPFET combines detection and amplificationwithin one device [3]. It is based on the sidewarddepletion as used in semiconductor drift chambers,[6]. The principle of operation is shown in Fig.1. Ap-channel MOSFET or JFET (junction field effecttransistor) is integrated onto a silicon detectorsubstrate, which becomes fully depleted by theapplication of a sufficiently high negative voltage to abackside p+ contact. By means of the sidewarddepletion, a potential minimum is formed which isshifted directly underneath the transistor channel at adepth of about 1µm by an additional phosphorousimplantation underneath the external gate. Incidentparticles generate electron-hole pairs within the fullydepleted bulk. While the holes drift into the backcontact, electrons are accumulated in the potentialminimum, called the internal gate resulting, in amodulation of the channel current. The readout isnon-destructive and can be repeated several times.The removal of the signal charge and thermallygenerated electrons from the internal gate is calledClear. A neighboring n+ contact is pulsed at apositive voltage providing a punch-through into theinternal gate. This pulsed clear mechanism isdiscussed below in detail.Internal GateFig.1: Cross section of a DEPFET indicating the operationprinciple.Intrinsic advantages of the DEPFET device are theamplification of the signal charge at the position ofits generation, thus avoiding any charge transferwhere losses could occur. The entire bulk is depletedand sensitive to incident radiation. Therefore, thenon-structured backside can be used as an entrancewindow thereby improving the spectroscopicperformance, especially for low energy photons. Themain advantage of the device is its very small inputcapacitance that provide a very low noise operationeven at room temperature. Fig.2 illustrates theexcellent noise performance with a measured Fe 55spectrum.DEPFET structures can be operated individually,as an integrated on-chip amplifier, for instance in thereadout node of a silicon drift chamber, orcollectively as a pixel array.

36000K α50004000# counts30002000ENC=4.8±0.1Si-escape peak1000K β02 4 6energy [keV]Fig.2: Fe 55 spectrum measured on a single DEPFET pixel atroom temperature [8]. The equivalent noise charge was fitted tobe ENC = 4.8 ± 0.1.Fig.3 shows a DEPFET pixel matrix which isoperating with a line-by-line access via the externalgates. Note that the external gates just switch thepixel on and off while the signal amplification isachieved via the internal gate. There is no currentflow in a non-selected DEPFET row, resulting in avery low power consumption of the array [4].A first 2 x 2 pixel array was produced andoperated in 1997 [7]; results from a 64 x 64 pixelimaging system were presented in 1999 and 2000 [9-12]. The readout amplifiers at the end of the columnscan be connected either to the sources (sourcefollower) or to the drains (drain read out) of theDEPFETs. For linear collider applications we needthe faster drain (current) readout, (see also [5]). Ameasurement cycle consists of a collection stage(Collect), the read out (Read) and the reset of theinternal gate (Clear). A pedestal subtraction isobtained by a consecutive Read–Clear–Readsequence. Therefore, the clear process affects thenoise performance of the device significantly. Anyreset noise is avoided if the entire charge iscompletely removed from the internal gate. If this isnot guaranteed an additional noise contributionoccurs due to an undefined amount of remainingcharge in the internal gate.Fig.3: Basic pixel array readout scheme. Only the row addressedby the decoder gates is active while the other rows are switched offand do not contribute to power consumption of the detector.3. DEPFET technology development and designUntil now, the DEPFET device concept wasevaluated mainly on circularly shaped JFETs 1 .However, a position resolution in the range of 5µm,needed for vertexing, requires pixel cell sizes ofabout 25 x 25µm². This is impossible to achieve withJFETs at the presently given minimum technologicalfeature sizes of 2µm to 3µm. Linear structures areinnately smaller than circular ones but the fabricationof linear JFETs is very complicated due to theproblem of lateral channel isolation. Another intrinsicdifficulty of JFET technologies is the pinch-offvoltage variation over the wafer, within fabricationbatches and from batch to batch. Therefore, we aregoing to use MOS devices. In principle MOSFETscan be produced in any shape, linear as well ascircular. In terms of reliability and homogeneity theyare suitable for large area devices and have a muchhigher geometrical scaling potential than JFETs.———1’Circularly shaped’ means a closed transistor where thedrain surrounds the source region or vice versa, in contrastto linearly shaped transistors having a lateral confinement ofthe channel by an isolation structure.

4Asourcedrain_1gate_2clearclear gateAclear gatedrain_2gate_1P+ implantN+ implantPolySilicon_1PolySilicon_2Contact_1Contact_2Metal_1Metal_2Fig.4: Layout example for a linear double pixel cell. Each whiterectangle surrounds a DEPMOS.For larger area sensor arrays, the availability ofmore than one metal layer is mandatory due to thenecessity of the row- and column-wise connectionsof the pixels. At the Semiconductor Laboratory of theMax-Planck-Institutes, a 150mm silicon technologyfor MOS type DEPFETs on high ohmic substrateswith two polysilicon and two metal layers has beendeveloped. Using the two polysilicon layers, linearDEPMOS transistors can be fabricated whereby thefirst polysilicon forms a lateral isolation frame andthe second one is used for the external gate of theDEPFET. This approach is different from that used incommon MOS technologies, where the lateraltransistor isolation is provided by locally oxidizedfield regions or shallow trenches filled with oxide.The channel isolation structure of the DEPFETs mustnot collect signal electrons and has to accomplish theintegration of the clear contacts.Fig.5: Potential distribution across the section A-A in Fig.4during the clear operation simulated with the 3D-Poisson solverPoseidon [18] (VClear = 20V, VBack = -30V, VSource = 0V,VDrain = -5V, VGate = -3V, VClear-Gate = 1V).The n+ doped clear region is close-by the internalgate, separated only by the first polysilicon layer. Inthe Collect and Read modes, the region underneaththe polysilicon acts as a potential barrier between theclear region and the internal gate. The barrier has tobe overcome during the Clear cycle when the clearcontact gets positive. The first polysilicon acts notonly as an isolation frame but also as a reset (clear)gate. It is held at a constant potential or can beswitched in order to alleviate the clear process. Asshown in Fig.4, the linear cell geometry allows for avery compact pixel layout free from potential pocketswhere the signal charge could disappear (see alsoFig.6). In any case, the implanted drain, source andclear regions are shared by neighboring cells. In thisway a small pixel size is achievable even with ratherrelaxed lithographic requirements. This feature,which defines also the tolerable defect size in theprocess, is important concerning the yield of largearea detectors.We have started a production run on 6-inch waferscontaining prototype arrays of up to 128x64 pixelsfor high energy and astrophysical applications [13-15]. The smallest pixel cell size is presently30x20µm².

54. Device simulationsTwo and three dimensional simulation tools [16-19] are used to optimize the layout and thetechnology parameters. Fig.6 shows the simulatedpotential distribution (section A-A in Fig.4) duringthe clear operation.Internal GateSourceClearDrainswitching on the external gate the device current isread out. The drain current response to a given signalcharge defines the amplification of the internal gateg q = ♎ I D /♎ q. To analyze the signal response of theDEPFET, 1600 electron-hole pairs were introducedby a locally and temporally limited increase of theShockley-Read-Hall generation rate using the twodimensional device simulator TeSCA [16]. Thesimulated signal response, shown in Fig.7,demonstrates an amplification potential of more than1nA per electron for optimized DEPFET structures.Fig.7: Simulated signal response to a signal charge generation of1600 electron-hole pairs.Fig.6: Potential distribution of a 2x4 array section parallel to thesurface at a depth of z=1µm during charge collection simulatedwith Poseidon (VClear = 3V, VBack = -25V, VSource = 0V,VDrain = -5V, VGate = 2V, VClear-Gate = 1V). A single cell ismarked by the dashed line.The simulation illustrates that the electrons canflow unopposed from the internal gate into the clearcontact. The applied clear voltage of 20V can bereduced by lowering the potential barrier in the cleargate region. During charge collection, the transistor isswitched off and the potential of the internal gate canbe adjusted by the voltage of the external gate viacapacitive coupling. Fig.6 shows the potential at adepth of 1µm, as seen by drifting electrons generatedin the bulk. Note that there is not any attraction of then+ clear contact to the electrons at this depth. This isthe result of the negative space charge of a deepboron doping implanted beneath the clear region. By5. Thinning technologyThe DEPFET, as a fully depleted device, needs, inaddition to the front side structures, a p+n diode atthe backside. Therefore a standard thinning process isnot applicable because it would destroy the backsidepn – junctions. The key technology of the processsequence illustrated in Fig.8 is the direct waferbonding [20]. It starts with a sensor wafer on top anda handle wafer on bottom, which are bonded togetheron their oxidized surfaces (Fig.8 a). The top wafer,which already contains the backside p+implantations, is thinned to a thickness of ~50µm bystandard wafer grinding and polishing (Fig.8 b). Thisside is where the actual device is fabricated. Duringthe front side fabrication process, the obtainedsandwich package can be handled like a standard

6wafer without special precautions for backsideprotection (Fig.8 c). After topside metallization andpassivation, the handle wafer is partially etched back(Fig.8 d) leaving a small frame large enough toprovide mechanical stability and space for the affixedsteering and readout chips [5].Fig.9: First results of the thinning technology development -mechanical samples. The size of the upper part is 800x104mm².6. SummaryFig.8 a-d: Joint process sequence of wafer thinning andDEPFET production.An inherent advantage of this technology is thatthe inner silicon oxide acts as a stop layer for theetchant, leaving the backside diode of the sensorwafer unaffected by the etching. With the proposedconcept, the material budget per layer can be reducedto the range of 0.1-0.15% of a radiation length,including the already thinned read out and line driverchips. Pictures of the first mechanical samplesproduced with this technology are shown in Fig.9.The DEPFET is a promising candidate to fulfillthe challenging detector requirements of future highenergy physics experiments, e.g. the TESLA vertexdetector. It offers excellent low noise performance atroom temperature. Thus the DEPFET has thepotential to achieve a good spatial resolution and afast readout speed even on a thinned detectorsubstrate. The overall requirement of a minimummaterial budget is addressed by an intrinsically lowpower consumption, thereby saving material forcooling structures. At the MPI SemiconductorLaboratory, a new MOS based technology on 150mmwafer has been developed to produce large detectorarrays.Linearly shaped DEPFETs of a size of about25x25µm² can be made by using two polysiliconlayers. As a detector pixel cell consists of only onesingle DEPFET transistor, it can be produced byrather large lithographic structures with minimumsize of 2µm. Therefore the yield problem occurringespecially in large area detectors is expected to berelaxed. Technology development and detectordesign based on two and three dimensional processesand device simulations demonstrating the operationand the technological feasibility of DEPFET arrays.The first production run has been started. A thinningtechnology based on direct wafer bonding isproposed. Mechanical samples with 50µm thinnedregions were fabricated successfully.

7AcknowledgmentsWe would like to thank K. E. Ehwald and B.Heinemann from IHP, Frankfurt/Oder for helpfuldiscussions and suggestions. The simulation softwarePOSEIDON was developed by A. Castoldi, E. Gattiand P. Rehak within the INFN-RIMAX project.References[1] T. Behnke, S. Bertolucci, R.D. Heuer and R. Settles, TESLA:The superconducting electron positron linear collider with anintegrated X-ray laser laboratory. Technical design report. Pt4: A detector for TESLA’, DESY-01-011.[2] XEUS astrophysics working group, X-ray evolving universespectroscopy – the XEUS science case, ESA, SP-1238 (2000).[3] A DEPFET based pixel vertex detector for the detector atTESLA, LC-DET-2002-004, April 5 th , 2002.[4] J. Kemmer and G. Lutz, New semiconductor detectorconcepts, Nucl. Instr. & Meth. A253, 356 (1987).[5] M. Trimpl et al., A fast read out using switched currenttechniques for a DEPFET pixel based vertex detector atTESLA, these proceedings.[6] E. Gatti and P. Rehak, Semiconductor drift chamber – Anapplication of a novel charge transport scheme, Nucl. Instr. &Meth. A225, 608 (1984).[7] G. Cesura et al, New pixel detector concepts based onjunction field effecxt transistors on high resisitivity silicon,Nucl. Instr. & Meth. A377, 521 (1996).[8] J . Ulrici et al., Spectroscopic and imaging performance ofDEPFET pixel sensors, Nucl. Instr. & Meth. A465, 247(2001).[9] P. Klein et al., Study of a DEPJFET pixel matrix withcontinuos clear mechanism, Nucl. Instr. & Meth. A392, 254(1997).[10] P. Fischer et al., First operation of pixel imaging matrix basedon DEPFET pixels, Nucl. Instr. & Meth. A451, 651 (2000)[11] W. Neeser et al., The DEPFET Pixel BIOSCOPE, IEEETrans. Nucl. Sci. 47 No.3 (2000).[12] W. Neeser et al., DEPFET a pixel device with integratedamplification, Nucl. Instr. & Meth. A477, 129 (2002).[13] G. Lutz, R.H. Richter and L.Strüder, Novel Pixel detectors forX-ray astronomy and other applications, Nucl. Instr. & Meth.A461, 393 (2001).[14] L. Strüder et al., Active pixel sensors for imaging x-rayspectrometers, submitted to SPIE[15] L. Strüder et al., Fully depleted backside illuminatedspectroscopic active pixel sensors from the infrared to X-rays,Proc. SPIE Conference, Munich 2000, Vol. 4012 (2000).[16] H. Gajewski et al., TeSCA – Two DimensionalSemiconductor Analysis Package, Handbuch, WIAS, Berlin,1997.[17] ISE TCAD Release 7.0, V0l. 2b, DIOS, 2001.[18] A. Castoldi, E. Gatti and P. Rehak, Three-DimensionalAnalytical Solution of the Laplace Equation Suitable forSemiconductor Detector Design, IEEE Trans. on Nucl. Sci.,43, 256-265, (1996).[19] A. Castoldi and E. Gatti, Fast tools for 3-D design problems insemiconductor detectors, Nucl. Instr. & Meth. A377, 381(1996).[20] Q.-Y. Tong and U. Gösele, Semiconductor Wafer Bonding,John Wiley & Sons, Inc., NY, 1999.