Cisco Catalyst 6500 Supervisor 2T Architecture - Ipland

White PaperSupervisor ArchitectureThe major processing blocks of the Supervisor 2T include the crossbar switch fabric, the MSFC5, the PFC4, thefabric interface ASICs, and the bus and fabric replication ASICs. Each of these block elements and theirinterconnection can be seen in the following diagram.Figure 2.Supervisor 2T High-Level Block DiagramTheory of OperationAll packet processing is performed in a specific sequence through the different ASIC blocks. A high-level packetwalk is provided for packets that ingress and egress the local ports on the Supervisor below.Ingress Packet Processing1. Packets arriving on either the 1 G or 10 G ports have preliminary checks performed on them (by the PHY), suchas cyclic redundancy checks (CRCs), before being forwarded to the Cisco TS ASIC.2. The CTS ASIC performs ingress 802.1ae decryption (if enabled) and extracts the Security Group Tag (SGT) forRoles-Based ACL (RBACL) processing (if enabled). If CTS is disabled, this ASIC is passive. The packet is thenforwarded to the port ASIC.3. The port ASIC will store the packet in its local packet buffer and then applies an internal packet header, whichcontains information about the source port, VLAN, and more.4. The packet is then forwarded to the fabric interface and replication ASIC, where information from the packetheader is forwarded to the PFC4 or DFC4 for forwarding lookup processing.5. The Layer 2 and Layer 3 processing is performed by the PFC4 (if a CFC is used, or local uplink ports) and theforwarding result of is sent back to fabric interface and replication ASIC.© 2011-2012 Cisco and/or its affiliates. All rights reserved. This document is Cisco Partner Confidential Information. Page 9 of 46