TMS320C5X USER'S GUIDE

’C2x-to-’C5x Instruction SetC.4 ’C2x-to-’C5x Instruction SetC.4.1OverviewThe ’C5x instruction set is a superset of the ’C2x instruction set. The instructionset of the ’C2x is upward source-code compatible. This means that all of theinstruction features of the ’C2x, implemented and code written for the ’C2x, canbe reassembled to run on the ’C5x. See Chapter 6, Assembly LanguageInstructions, for the detailed discussion of the instruction set.There are a number of new instructions on the ’C5x devices. These newinstructions provide an advanced addressing scheme and exercise the newCPU enhancements. To simplify the description of the instruction set, a numberof different instructions are combined into single new instructions with additionaloperand formats, such as the ADD instruction shown in Table C–1.Table C–1. TMS320C2x Versus TMS320C5x for the ADD Instruction’C2x Instruction’C5x InstructionADD *+ ADD *+ADDK 0FFh ADD #0FFhADLK 0FFFFh ADD #0FFFFhADDH *+ ADD *+ , 16The IDLE instruction, when executed, stops the CPU from fetching andexecuting instructions until an unmasked interrupt occurs. The ’C2x automaticallyenables the interrupts globally with the execution of the IDLE instruction;this saves the extra instruction word/cycle required to execute the EINT(enable interrupts globally) instruction. Upon receipt of the interrupt, the ’C2xexecutes the interrupt vector and resumes operations.The ’C5x does not automatically enable the interrupts globally with its IDLE instruction.If the interrupts are not globally enabled (INTM = 1), then the CPUresumes execution at the instruction following the IDLE instruction, withouttaking the interrupt trap. If the interrupts are globally enabled (INTM = 0), the’C5x operates like the ’C2x. In addition, a second low-power mode is availablewith the IDLE2 instruction. This mode operates the same as IDLE, except thatthe CPU will resume only after an external interrupt. See Chapter 6, AssemblyLanguage Instructions, for IDLE and IDLE2 instruction details.The ’C5x repeat counter is 16 bits wide (the ’C2x repeat counter is 8 bits wide).This means that, when loading from RAM, the RPT instruction supports repeatcounts up to 65 536. The assembler also allows the RPT to support a16-bitimmediate repeat count. Note that RPT with long immediate addressing is,however, a two-word instruction.System MigrationC-11