pic24fj128ga010 family - Microchip

PIC24FJ128GA010 FAMILY7.4 Clock Switching OperationWith few limitations, applications are free to switchbetween any of the four clock sources (POSC, SOSC,FRC and LPRC) under software control and at anytime. To limit the possible side effects that could resultfrom this flexibility, PIC24F devices have a safeguardlock built into the switching process.Note: Primary oscillator mode has threedifferent submodes (XT, HS and EC)which are determined by the POSCMDConfiguration bits. While an applicationcan switch to and from primary oscillatormode in software, it cannot switchbetween the different primary submodeswithout reprogramming the device.7.4.1 ENABLING CLOCK SWITCHINGTo enable clock switching, the FCKSM1 Configuration bitin the Flash Configuration Word 2 register must be programmedto ‘0’. (Refer to Section 23.1 “ConfigurationBits” for further details.) If the FCKSM1 Configuration bitis unprogrammed (‘1’), the clock switching function andFail-Safe Clock Monitor function are disabled. This is thedefault setting.The NOSC control bits (OSCCON) do notcontrol the clock selection when clock switching is disabled.However, the COSC bits (OSCCON)will reflect the clock source selected by the FNOSCConfiguration bits.The OSWEN control bit (OSCCON) has no effectwhen clock switching is disabled. It is held at ‘0’ at alltimes.7.4.2 OSCILLATOR SWITCHINGSEQUENCEAt a minimum, performing a clock switch requires thisbasic sequence:1. If desired, read the COSC bits(OSCCON), to determine the currentoscillator source.2. Perform the unlock sequence to allow a write tothe OSCCON register high byte.3. Write the appropriate value to the NOSC controlbits (OSCCON) for the new oscillatorsource.4. Perform the unlock sequence to allow a write tothe OSCCON register low byte.5. Set the OSWEN bit to initiate the oscillatorswitch.Once the basic sequence is completed, the systemclock hardware responds automatically as follows:1. The clock switching hardware compares theCOSC status bits with the new value of theNOSC control bits. If they are the same, then theclock switch is a redundant operation. In thiscase, the OSWEN bit is cleared automaticallyand the clock switch is aborted.2. If a valid clock switch has been initiated, theLOCK (OSCCON) and CF (OSCCON)status bits are cleared.3. The new oscillator is turned on by the hardwareif it is not currently running. If a crystal oscillatormust be turned on, the hardware will wait untilthe OST expires. If the new source is using thePLL, then the hardware waits until a PLL lock isdetected (LOCK = 1).4. The hardware waits for 10 clock cycles from thenew clock source and then performs the clockswitch.5. The hardware clears the OSWEN bit to indicate asuccessful clock transition. In addition, the NOSCbit values are transferred to the COSC status bits.6. The old clock source is turned off at this time,with the exception of LPRC (if WDT or FSCMare enabled) or SOSC (if SOSCEN remainsset).Note 1: The processor will continue to executecode throughout the clock switchingsequence. Timing sensitive code shouldnot be executed during this time.2: Direct clock switches between anyprimary oscillator mode with PLL andFRCPLL mode are not permitted. Thisapplies to clock switches in either direction.In these instances, the applicationmust switch to FRC mode as a transitionclock source between the two PLLmodes.© 2009 Microchip Technology Inc. DS39747E-page 99