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pic24fj128ga010 family - Microchip

pic24fj128ga010 family - Microchip

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PIC24FJ128GA010 FAMILYREGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 MI2C1IP2:MI2C1IP0: Master I2C1 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 SI2C1IP2:SI2C1IP0: Slave I2C1 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledDS39747E-page 80© 2009 <strong>Microchip</strong> Technology Inc.

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